SST32LH802 FEATURES: Organized 512K Flash 128K SRAM 512K Flash 12
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Megabit Flash Megabit SRAM ComboMemory
SST32LH802
FEATURES: Organized 512K Flash 128K SRAM 512K Flash 128K SRAM Single 3.0-3.6V Read Write Operations Concurrent Operation Read from write SRAM while Erase/Program Flash Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Read Current: (typical) Flash SRAM Standby Current: (typical) Sector-Erase Capability Uniform KWord KByte sectors Fast Read Access Times: Flash: SRAM: Latched Address Data Flash Flash Fast Sector-Erase Word-Program: Sector-Erase Time: typical Bank-Erase Time: typical Word-Program Time: typical Bank Rewrite Time: seconds typical Flash Automatic Erase Program Timing Internal Generation Flash Write Detection Toggle Data# Polling CMOS Compatibility Packages Available 48-Ball LBGA (10mm 12mm) PRODUCT DESCRIPTION SST32LH802 combination memory device that consists Mbits flash memory Mbits SRAM. flash memory banks organized 512K (connecting BEFH# BEFL# together) 512K (separating BEFH# BEFL# signals). SRAM banks organized 128K (connecting BESH# BESL# together) 128K (separating BESH# BESL# signals). device fabricated using SST's proprietary, power high reliability CMOS SuperFlash technology. SST32LH802 only needs single power supply (3.0-3.6V) operate (read, write, program erase) SRAM flash memory banks. Featuring high performance Word/Byte-Program, flash memory bank provides maximum Word/ByteProgram time µsec. entire flash memory bank erased programmed word-by-word typically seconds, when using interface features such Toggle Data# Polling indicate completion Program operation. protect against inadvertent flash write, SST32LH802 device on-chip hardware software data protection schemes. Designed, manufactured, tested wide spectrum applications, SST32LH802 device offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. SST32LH802 operates four independent memory banks with respective bank enable signals. SRAM Flash memory banks superimposed same memory address space. Both SRAM flash memory share common address lines, data lines,
1999 Silicon Storage Technology, Inc. 354-11 11/99
OE#. memory bank selection done memory bank enable signals. SRAM bank enable signals, BESH# BESL# select SRAM banks flash memory bank enable signals, BEFH# BEFL# select flash memory banks. signal used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory banks. command sequence protects data stored flash memory banks from inadvertent alteration. SST32LH802 provides added functionality being able simultaneously read from write SRAM banks while erasing programming flash memory banks. SRAM memory banks read written while flash memory banks performs Sector-Erase, Bank-Erase, Word/Byte-Program concurrently. flash memory Erase Program operations will automatically latch input address data signals complete operation background without further input stimulus requirement. Once internally controlled erase program cycle flash banks commenced, SRAM bank accessed read write. SST32LH802 device suited applications that both nonvolatile flash memory volatile SRAM memory store code data. system applications, SST32LH802 device significantly improves performance reliability, while lowering power consumption, when compared with multiple chip solutions. SST32LH802 inherently uses less energy during erase program than alternative flash technologies.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. ComboMemory trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. ComboMemory architecture eliminates redundant functions when using separate memories similar architecture; therefore, reducing total power consumption. SuperFlash technology provides fixed Erase Program times, independent number Erase/ Program cycles that have occurred. Therefore system software hardware does have modified derated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. SST32LH802 device also improves flexibility using single package common signals perform functions previously requiring separate devices. meet high density, surface mount requirements, SST32LH802 device offered 48-ball, Profile Standard-pitch Ball Grid Array (LBGA) package. Figure pinout. Device Operation ComboMemory uses Bank-Enable signals BESH#/ BESL# BEFH#/BEFL# control operation either SRAM flash memory banks. contention eliminated monolithic integration flash SRAM banks will recognize both bank enables being simultaneously active. both SRAM flash bank enables asserted (i.e., BEFH#/BEFL# BESH#/ BESL# both low), BEFH#/BEFL# will dominate while BESH#/BESL# ignored appropriate operation will executed flash memory banks. does recommend that both SRAM flash bank enables simultaneously asserted. other address, data, control lines shared; which minimizes power consumption area. device goes into standby when both SRAM flash bank enables raised VIHC. SRAM Operation With BESH# BESL# while BEFH# BEFL# high, SST32LH802 operates 128K 128K CMOS SRAM, with fully static operation requiring external clocks timing strobes. SRAM mapped into first 128K address space device. Read Write cycle times equal. SRAM Read SRAM Read operation SST32LH802 controlled BESH#/BESL#, both have
1999 Silicon Storage Technology, Inc.
with high system obtain data from outputs. BESH#/BESL# used SRAM bank selection. When BESH#/BESL# BEFH#/BEFL# high, both SRAM flash memory banks deselected. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram, Figure 2A/B, further details. SRAM Write SRAM Write operation SST32LH802 controlled Bank Enable Signal (BESH# and/or BESL#), both have system write SRAM. BESH# and/or BESL# used SRAM bank selection. During Write operation, addresses data referenced rising edge either BESH#/BESL# WE#, whichever occurs first. write time measured from last falling edge first rising edge BESH#/BESL# WE#. Refer Write cycle timing diagram, Figure 3A/B, further details. Flash Operation With BEFH#/BEFL# active, SST32LH802 operates 512K 512K flash memory. flash memory bank read using common address lines, data lines, OE#. Erase Program operations initiated with command sequences. Address data latched during commands internally timed Erase Program operations. commands decoded byte-wide. Therefore, half-word flash operation take place when byte-wide command recognized. Flash Read Read operation SST32LH802 device controlled Bank Enable Signal (BEFH# and/or BEFL#) OE#, both have with high system obtain data from outputs. BEFH# and/or BEFL# used flash memory bank selection. When BEFH#/BEFL# BESH#/BESL# high, both SRAM flash memory banks deselected only standby power consumed. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram (Figure 4A/B) further details. Flash Erase/Program Operation commands used initiate flash memory bank Program Erase operations SST32LH802. commands loaded flash memory bank using standard microprocessor write sequences. command loaded asserting while keeping BEFH# and/or BEFL# high. address latched falling edge BEFH#/BEFL#, whichever occurs last. data latched rising edge BEFH#/BEFL#, whichever occurs first.
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information Flash Word/Byte-Program Operation flash memory banks SST32LH802 device programmed word-by-word byte-by-byte basis. Program operation consists three steps. first step three-word/byte-load sequence Software Data Protection. second step load word/byte address word/byte data. During Word/ByteProgram operation, addresses latched falling edge either Flash Bank Enable Signal (BEFH# and/or BEFL#) WE#, whichever occurs last. data latched rising edge either BEFH#/ BEFL# WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth BEFH#/BEFL#, whichever occurs first. Program operation, once initiated, will completed, within Figures 5A/B 6A/B BEFH#/BEFL# controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid Flash Read operations Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands loaded during internal Program operation will ignored. Flash Sector-Erase Operation Sector-Erase operation allows system erase flash memory banks sector sector basis. sector architecture based uniform sector size KWords KBytes. Sector-Erase operation initiated executing six-word/byte-command load sequence software data protection with Sector-Erase command (3030H 30H) sector address (SA) last cycle. address lines A12-A18 will used determine sector address. sector address latched falling edge sixth pulse, while command latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Erase determined using either Data# Polling Toggle methods. Figure 9A/B timing waveforms. commands loaded during Sector-Erase operation will ignored. Flash Bank-Erase Operation SST32LH802 flash memory bank provides BankErase operation, which allows user erase entire flash memory bank array "1's" state. This useful when entire bank must quickly erased. BankErase operation initiated executing six-word/byte software data protection command sequence with BankErase command (1010H 10H) with address 5555H last word sequence. internal Erase operation begins with rising edge sixth BEFH#/ BEFL# pulse, whichever occurs first. During internal Erase operation, only valid Flash Read operations
1999 Silicon Storage Technology, Inc.
Toggle Data# Polling. Table 4A/B command sequence, Figure 10A/B timing diagram, Figure flowchart. commands loaded during Bank-Erase operation will ignored. Flash Write Operation Status Detection SST32LH802 flash memory bank provides software means detect completion flash memory bank Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes four status bits: Data# Polling (DQ7 DQ15) Toggle (DQ6 DQ14). write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ7/DQ15 DQ6/DQ14. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Flash Data# Polling (DQ7 DQ15) When SST32LH802 flash memory internal Program operation, attempt read DQ7/DQ15 will produce complement true data. Once Program operation completed, DQ7/DQ15 will produce true data. flash memory then ready next operation. During internal Erase operation, attempt read DQ7/DQ15 will produce `0'. Once internal Erase operation completed, DQ7/DQ15 will produce `1'. Data# Polling valid after rising edge fourth BEFH#/BEFL#) pulse Program operation. Sector Bank-Erase, Data# Polling valid after rising edge sixth BEFH#/BEFL#) pulse. Figure Data# Polling timing diagram Figure flowchart. Flash Toggle (DQ6 DQ14) During internal Program Erase operation, consecutive attempts read DQ6/DQ14 will produce alternating 1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. flash memory then ready next operation. Toggle valid after rising edge fourth BE#) pulse Program operation. Sector Bank-Erase, Toggle valid after rising edge sixth BEFH#/BEFL#) pulse. Figure Toggle timing diagram Figure flowchart.
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information Flash Memory Data Protection SST32LH802 provides both hardware software features protect nonvolatile data flash memory from inadvertent writes. Flash Hardware Data Protection Noise/Glitch Protection: BEFH#/BEFL# pulse less than will initiate write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, BEFH# BEFL# high, high will inhibit Flash Write operation. This prevents inadvertent writes during power-up power-down. Flash Software Data Protection (SDP) SST32LH802 provides software data protection scheme flash memory data alteration operations, i.e., Program Erase. Program operation requires inclusion series three-word/byte sequence. three word/byte-load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-word/byte load sequence. SST32LH802 device shipped with software data protection permanently enabled. Table 4A/B specific software command codes. During command sequence, invalid commands will abort device read mode, within Read Cycle Time (TRC). Caution: When Word-Mode, Command sequence decoded byte-wide. Therefore, when valid byte-wide command sequence decoded addressed half-word, given flash operation (Program, Erase, Software Entry) will commence halfword (DQ15-DQ8 DQ7-DQ0) regardless whether command decoded other halfword. Concurrent Read Write Operations SST32LH802 provides unique benefit being able read from write SRAM, while simultaneously erasing programming flash memory. This allows data alteration code executed from SRAM, while altering data flash memory. following table lists valid states. CONCURRENT READ/WRITE STATE TABLE Flash Program/Erase Program/Erase
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device will ignore commands when Erase Program operation progress. Note that Product Identification commands SDP; therefore, these commands will also ignored while Erase Program operation progress. Product Identification product identification mode identifies device SST32LH802 manufacturer SST. This mode accessed hardware software operations. hardware device Read operation typically used programmer identify correct algorithm SST32LH802 flash memory banks. Users wish software product identification operation identify part (i.e., using device code) when using multiple manufacturers same socket. details, Table 3A/B hardware operation Table 4A/B software operation, Figure 11A/B software entry read timing diagram Figure entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION TABLE Address BEFH# BEFL# Manufacturer's Code Device Code 0000H Data* BFBF BFXX XXBF 1717 17XX XX17
T1.2
0001H
Data (Word) organization
Product Identification Mode Exit/Reset order return standard read mode, Software Product Identification mode must exited. Exiting accomplished issuing Exit command sequence, which returns device Read operation. Please note that software-reset command ignored during internal Program Erase operation. Table 4A/B software command codes, Figure 12A/B timing waveform Figure flowchart. Design Considerations recommends high frequency ceramic capacitor placed close possible between VSS, e.g., less than away from device. Additionally, frequency electrolytic capacitor from should placed within pin.
SRAM Read Write
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information FUNCTIONAL BLOCK DIAGRAM SST32LH802
VIEW (balls facing down)
Control Circuit
Data Buffer
BESL# BEFL#
BESL#
DQ7-DQ0
DQ14 DQ15
Address Buffers
BEFL#
DQ13 DQ12 DQ11 DQ10 BEFH# BEFL#
BESH# BESL#
A18-A17 A16-A0
Flash
Control Circuit
Address Buffers
BEFH#
Data Buffer
BESH# BEFH#
BESH#
SST32LH802
DQ15-DQ8
F01.6
FIGURE ASSIGNMENTS 48-BALL LBGA PACKAGE (10mm 12mm)
A18-A17 A16-A0
Flash
B1.4
TABLE DESCRIPTION Symbol Name A18-A0 Address Inputs Functions provide memory addresses. During Flash Sector-Erase A18-A12 address lines will select sector. A18-A0 provide flash address, A16-A0 provide SRAM addresses. output data during read cycles receive input data during write cycles. Data internally latched during Flash Erase/Program cycle. outputs tri-state when BESH# BESL# BEFH# BEFL# high. activate High Order Byte (HOB) SRAM memory bank when BESH# low. activate Order Byte (LOB) SRAM memory bank when BESL# low. BESH# BESL# connected together Word-Mode operation. activate Flash memory bank when BEFH# low. activate Flash memory bank when BEFL# low. BEFH# BEFL# connected together Word-Mode operation. gate data output buffers. control Write operations. provide 3.0-3.6V supply
T2.4 1999 Silicon Storage Technology, Inc.
DQ15-DQ8 Data Input/output DQ7-DQ0
BESH# BESL#
SRAM Memory Bank Enable SRAM Memory Bank Enable Flash Memory Bank Enable Flash Memory Bank Enable Output Enable Write Enable Power Supply Ground
BEFH# BEFL#
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information TABLE OPERATION MODES SELECTION (WORD-MODE) Mode BESH# BEFH# BESL# BEFL# Flash Read Flash Program Flash Erase SRAM Read SRAM Write Standby Flash Write Inhibit VIHC VIHC DQ15-0 DOUT DOUT High High Z/DOUT High Z/DOUT High Z/DOUT Address Sector address, Bank-Erase
Product Identification Hardware Mode Software Mode
Manufacturer VIL, Code (BFBF) Device Code (1717) VIL, Code Table
T3A.4
TABLE OPERATION MODES SELECTION (BYTE-MODE) Mode BESH# BEFH# BESL# BEFL# Flash Read Flash Program Flash Erase SRAM Read SRAM Write Standby Flash Write Inhibit VIHC VIHC
DQ15-8 DQ7-0* DOUT DOUT High High Z/DOUT High Z/DOUT High Z/DOUT Manufacturer Code (BF) Device Code (17) Code
Address Sector address, Bank-Erase VIL, VIL, Table
T3B.2
Product Identification Hardware Mode Software Mode
DQ15-8 active (BESH# BEFH# Low) DQ7-0 active (BESL# BEFL# Low)
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information TABLE SOFTWARE COMMAND SEQUENCE FLASH MEMORY BANK (WORD-MODE)
Write Cycle Addr(1) Data(4) Word-Program 5555H AAAAH Half-Word-Program 5555H XXAA AAXX Sector-Erase 5555H AAAAH Half-Word 5555H XXAA Sector-Erase AAXX Bank-Erase 5555H AAAAH Half-Word 5555H XXAA Bank-Erase AAXX Software Entry 5555H AAAAH Half-Word 5555H XXAA Software Entry AAXX Software Exit 5555H AAAAH Half-Word 5555H XXAA Software Exit AAXX Command Sequence Write Cycle Addr(1) Data(4) 2AAAH 5555H 2AAAH XX55 55XX 2AAAH 5555H 2AAAH XX55 55XX 2AAAH 5555H 2AAAH XX55 55XX 2AAAH 5555H 2AAAH XX55 55XX 2AAAH 5555H 2AAAH XX55 55XX Write Cycle Write Cycle Addr(1) Data(4) Addr(1) Data(4) 5555H A0A0H WA(3) Data 5555H XXA0 WA(3) Data A0XX 5555H 8080H 5555H AAAAH 5555H XX80 5555H XXAA 80XX AAXX 5555H 8080H 5555H AAAAH 5555H XX80 5555H XXAA 80XX AAXX 5555H 9090H 5555H XX90 90XX 5555H F0F0H 5555H XXF0 F0XX Write Cycle Write Cycle Addr(1) Data(4) Addr(1) Data(4)
2AAAH 5555H SAx(2) 3030H 2AAAH XX55 SAx(2) XX30 55XX 30XX 2AAAH 5555H 5555H XX10 2AAAH XX55 5555H 1010H 55XX 10XX
T4A.1
TABLE SOFTWARE COMMAND SEQUENCE FLASH MEMORY BANK (BYTE-MODE)
Command Sequence Byte-Program Sector-Erase Bank-Erase Software Entry Software Exit
Notes:
Write Cycle Addr(1) Data(4) 5555H 5555H 5555H 5555H 5555H
Write Cycle Write Cycle Addr(1) Data(4) Addr(1) Data(4) 2AAAH 5555H 2AAAH 5555H 2AAAH 5555H 2AAAH 5555H 2AAAH 5555H
Write Cycle Addr(1) Data(4) BA(3) Data 5555H 5555H
Write Cycle Write Cycle Addr(1) Data(4) Addr(1) Data(4) 2AAAH 2AAAH SAx(2) 5555H
T4B.0
Address format A14-A0 (Hex), Addresses A15, A16, "Don't Care" Command sequence. Sector-Erase; uses address lines Program word address, Program byte address Data (BEFL# Low) (BEFH# Low) Byte-Mode (BEFL# BEFH# both Low) Word-Mode. When Word-Mode (BEFH# BEFL# connected together). command decoded byte basis. Therefore, when byte-wide sequence decoded given flash operation will commence half-word (DQ15-DQ8 DQ7-DQ0), regardless whether sequence decoded other half-word. Notes Software Entry Command Sequence With Manufacturer Code BFBFH, read with 32LH802 Device Code 1717H, read with device does remain Software Product Mode powered down.
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+ 0.5V Transient Voltage (<20 Ground Potential -1.0V VDD+ 1.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current(1)
Note: Outputs shorted more than second. more than output shorted time.
OPERATING RANGE Range Ambient Temp Commercial Industrial
CONDITIONS TEST 3.0-3.6V 3.0-3.6V Input Rise/Fall Time Output Load Figures
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information TABLE OPERATING CHARACTERISTICS 3.0-3.6V Limits Symbol Parameter Power Supply Current Read Flash SRAM Concurrent Operation Write Flash SRAM Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage Supervoltage Supervoltage Current 0.7VDD VDD-0.3 VDD-0.2 11.4 12.6
Units
Test Conditions Max, open, Address input VIL/VIH, f=1/TRC Min. VIL, BEFH# and/or BEFL# VIL, BESH#=BESL# BEFH# and/or BEFL# VIH, BESH#=BESL# BEFH# and/or BEFL# VIH, BESH#=BESL# VIH, BEFH# and/or BEFL# VIL, BESH#=BESL# BEFH# and/or BEFL# VIH, BESH#=BESL# Max. BEFH#=BEFL# BESH#= BESL# VIHC =GND VDD, Max. VOUT =GND VDD, Max. Min. Max. Max. Min. -100µA, Min. BEFH# and/or BEFL# =VIL, BEFH# and/or BEFL# VIL, VIH, Max.
T5.7
T6.0
VIHC
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ TPU-WRITE(1)
Minimum
Units
Power-up Read Operation Power-up Write Operation
TABLE CAPACITANCE Mhz, other pins open) Parameter Description Test Condition CI/O CIN(1)
Maximum
T7.1
Capacitance Input Capacitance
VI/O
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information TABLE RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification NEND TDR(1) VZAP_HBM(1) VZAP_MM(1) ILTH(1)
Units Cycles Years Volts Volts
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T8.1
Endurance Data Retention Susceptibility Human Body Model Susceptibility Machine Model Latch
10,000 1000
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM MEMORY BANK READ CYCLE TIMING PARAMETERS 3.0-3.6V Symbol Parameter TRCS Read Cycle Time TAAS Address Access Time TBES Bank Enable Access Time TOES Output Enable Access Time TBLZS(1) BESH#/BESL# Active Output TOLZS(1) Output Enable Active Output TBHZS(1) BESH#/BESL# High-Z Output TOHZS Output Disable High-Z Output TOHS Output Hold from Address Change
Unit
T9.3
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM MEMORY BANK WRITE CYCLE TIMING PARAMETERS 3.0-3.6V Symbol Parameter TWCS Write Cycle Time TBWS Bank Enable Write TAWS Address Valid Write TASS Address Set-up Time TWPS Write Pulse Width TWRS Write recovery Time TDSS Data Set-up Time TDHS Data Hold from Write Time
Unit
T10.2
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information CHARACTERISTICS TABLE FLASH READ CYCLE TIMING PARAMETERS 3.0-3.6V Symbol Parameter Read Cycle Time Bank Enable Access Time Address Access Time Output Enable Access Time TBLZ BEFH# BEFL# Active Output TOLZ Active Output TBHZ(1) BEFH# BEFL# High High-Z Output TOHZ(1) High High-Z Output Output Hold from Address Change
Units
T11.3
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS 3.0-3.6V Symbol Parameter Word-Program Time Address Setup Time Address Hold Time BEFH# BEFL# Setup Time BEFH# BEFL# Hold Time TOES High Setup Time TOEH High Hold Time BEFH# BEFL# Pulse Width Pulse Width TWPH Pulse Width High TBPH BEFH# BEFL# Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time TIDA Sector-Erase TSBE Bank-Erase
Units
T12.2
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
TRCS ADDRESS A16-0 TBES
TAAS
BESH# BESL#
TOES TOHZS
TOLZS
DQ15-0
HIGH-Z
TBLZS
TOHS DATA VALID
TBHZS HIGH-Z DATA VALID
F02.3
FIGURE SRAM READ CYCLE TIMING DIAGRAM (WORD-MODE)
TRCS ADDRESS A16-0 TBES
TAAS
BESL# (BESH#)*
TOES TOHZS
BESH# (BESL# WE#)* DQ7-0 (DQ15-8)*
TOLZS
HIGH-Z
TBLZS
TOHS DATA VALID
TBHZS HIGH-Z DATA VALID
F20.3
FIGURE SRAM READ CYCLE TIMING DIAGRAM BYTE-MODE-LOB
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
TWCS ADDRESS A16-0 ADDRESS TAWS TOES TBWS BESH# BESL# TWPS TASS TDSS DQ15-0 DATA VALID
F03.3
TOEHS
TWRS
TDHS
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM (WORD-MODE)
TWCS ADDRESS A16-0 BESH# (BESL# OE#)* ADDRESS TAWS TOES TBWS BESL# (BESH#)* TWPS TASS TDSS DQ7-0 (DQ15-8)* DATA VALID TWRS TOEHS
TDHS
F21.3
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM BYTE-MODE-LOB
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
ADDRESS A18-0
BEFH# BEFL#
TOLZ
TOHZ TBHZ HIGH-Z DATA VALID
DQ15-0
HIGH-Z
TBLZ
DATA VALID
F18.2
FIGURE FLASH READ CYCLE TIMING DIAGRAM (WORD-MODE)
ADDRESS A18-0
BEFL# (BEFH#)*
TOLZ
TOHZ TBHZ HIGH-Z DATA VALID
BEFH# (BEFL# WE#)* DQ7-0 (DQ15-8)*
HIGH-Z
TBLZ
DATA VALID
F22.2
FIGURE FLASH READ CYCLE TIMING DIAGRAM BYTE-MODE-LOB
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
INTERNAL PROGRAM OPERATION STARTS ADDRESS A18-0 5555 BEFH# BEFL# DQ15-0 AAAA 5555 A0A0 DATA WORD (ADDR/DATA) TWPH 2AAA 5555 ADDR
F04.3
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM (WORD-MODE)
INTERNAL PROGRAM OPERATION STARTS ADDRESS A18-0 5555 BEFH# (BEFL# OE#)* BEFL# (BEFH#)* DQ7-0 (DQ15-8)* AAAA 5555 A0A0 DATA BYTE (ADDR/DATA)
F23.3
2AAA
5555
ADDR
TWPH
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM BYTE-MODE-LOB
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
INTERNAL PROGRAM OPERATION STARTS ADDRESS A18-0 5555 BEFH# BEFL# DQ15-0 AAAA 5555 A0A0 DATA WORD (ADDR/DATA) TCPH 2AAA 5555 ADDR
F05.3
FIGURE BEFH# BEFL# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM (WORD-MODE)
INTERNAL PROGRAM OPERATION STARTS ADDRESS A18-0 5555 BEFH# (BEFL# OE#)* DQ7-0 (DQ15-8)* AAAA 5555 A0A0 DATA BYTE (ADDR/DATA)
F24.3
2AAA
5555
ADDR
BEFL# (BEFH#)*
TCPH
FIGURE BEFH# BEFL# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM BYTE-MODE-LOB
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
ADDRESS A18-0 BEFH#/BEFL# TOEH TOES
F06.2
DQ15 and/or
FIGURE DATA# POLLING TIMING DIAGRAM
ADDRESS A18-0 BEFH# BEFL# TOEH TOES
DQ14 and/or
READ CYCLES WITH SAME OUTPUTS
F07.3
FIGURE TOGGLE TIMING DIAGRAM
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
SIX-WORD CODE SECTOR-ERASE ADDRESS A18-0 5555 2AAA 5555 5555 2AAA
BEFH# BEFL#
DQ15-0
AAAA
5555
8080
AAAA
5555
3030
F08.3
Note:
device also supports BEFH# BEFL# controlled Sector-Erase operation. BEFH# BEFL# signals interchangeable long minimum timings met. (See table Sector Address
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM (WORD-MODE)
SIX-BYTE CODE SECTOR-ERASE ADDRESS A18-0 5555 2AAA 5555 5555 2AAA
BEFL# (BEFH#)* BEFH# (BEFL# OE#)*
DQ7-0 (DQ15-8)*
AAAA
Note:
5555
8080
AAAA
5555
3030
F25.3
device also supports BEFH# BEFL# controlled Sector-Erase operation. BEFH# BEFL# signals interchangeable long minimum timings met. (See table Sector Address
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM BYTE-MODE-LOB
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Megabit Flash Megabit SRAM ComboMemory SST32LH802
SIX-WORD CODE BANK-ERASE ADDRESS A18-0 5555 2AAA 5555 5555 2AAA 5555
TSBE
BEFH# BEFL#
DQ15-0
AAAA
Note:
5555
8080
AAAA
5555
1010
F17.3
device also supports BEFH# BEFL# controlled Bank-Erase operation. BEFH# BEFL# signals interchangeable long minimum timings met. (See table
FIGURE 10A: CONTROLLED BANK-ERASE TIMING DIAGRAM (WORD-MODE)
SIX-BYTE CODE BANK-ERASE ADDRESS A18-0 BEFL# (BEFH#)* 5555 2AAA 5555 5555 2AAA 5555
TSBE
BEFH# (BEFL# OE#)*
5555 8080 AAAA 5555 1010
F26.3
DQ7-0 (DQ15-8)*
AAAA
Note:
device also supports BEFH# BEFL# controlled Bank-Erase operation. BEFH# BEFL# signals interchangeable long minimum timings met. (See table
FIGURE 10B: CONTROLLED BANK-ERASE TIMING DIAGRAM BYTE-MODE-LOB
1999 Silicon Storage Technology, Inc.
354-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST32LH802
Three-word sequence Software Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
BEFH# BEFL#
TWPH DQ15-0 AAAA 5555 9090 BFBF 1717 DEVICE
F09.3
TIDA
FIGURE 11A: SOFTWARE ENTRY READ (WORD-MODE)
Three-byte sequence Software Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
BEFL# (BEFH#)*
BEFH# (BEFL# OE#)* TWPH DQ7-0 (DQ15-8)* DEVICE
F27.3
TIDA
FIGURE 11B: SOFTWARE ENTRY READ BYTE-MODE-LOB
1999 Silicon Storage Technology, Inc.
354-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST32LH802
THREE-WORD SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ15-0
AAAA
5555
F0F0 TIDA
BEFH#/BEFL#
F10.2
FIGURE 12A: SOFTWARE EXIT RESET (WORD-MODE)
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0 (DQ15-8)* BEFL# (BEFH#)*
TIDA
BEFH# (BEFL# OE#)*
F28.3
FIGURE 12B: SOFTWARE EXIT RESET BYTE-MODE-LOB
1999 Silicon Storage Technology, Inc.
354-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST32LH802
VIHT
INPUT REFERENCE POINTS
OUTPUT
VILT
F11.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (1.6 V(1)) (1.4 Input rise fall times (10% 90%)
Output test level common SRAM test standards. Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE TESTER HIGH
F12.0
FIGURE TEST LOAD EXAMPLE
1999 Silicon Storage Technology, Inc.
354-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST32LH802
Start
Load data: AAAA Address: 5555
Load data: 5555 Address: 2AAA
Load data: A0A0 Address: 5555
F13.3
Load Word/Byte Address/ Word/Byte Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
FIGURE WORD-PROGRAM ALGORITHM
1999 Silicon Storage Technology, Inc.
354-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST32LH802
Internal Timer Word/Byte Program/Erase Initiated
Toggle Word/Byte Program/Erase Initiated
Data# Polling Word/Byte Program/Erase Initiated
Wait TBP, TSBE,
Read word/byte
Read
Program/Erase Completed
Read same word/byte
and/or DQ15 true data?
Does and/or DQ14 match?
Program/Erase Completed
Program/Erase Completed
F14.4
FIGURE WAIT OPTIONS
1999 Silicon Storage Technology, Inc.
354-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST32LH802
Software Product Entry Command Sequence
Software Product Exit Reset Command Sequence
Load data: AAAA Address: 5555
Load data: AAAA Address: 5555
Load data: F0F0 Address:
Load data: 5555 Address: 2AAA
Load data: 5555 Address: 2AAA
Wait TIDA
Load data: 9090 Address: 5555
Load data: F0F0 Address: 5555
Return normal operation
Wait TIDA
Wait TIDA
Read Software Return normal operation
F15.3
FIGURE SOFTWARE PRODUCT COMMAND FLOWCHARTS
1999 Silicon Storage Technology, Inc.
354-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST32LH802
Flash Bank-Erase Command Sequence Load data: AAAA Address: 5555
Sector-Erase Command Sequence Load data: AAAA Address: 5555
Load data: 5555 Address: 2AAA
Load data: 5555 Address: 2AAA
Load data: 8080 Address: 5555
Load data: 8080 Address: 5555
Load data: AAAA Address: 5555
Load data: AAAA Address: 5555
Load data: 5555 Address: 2AAA
Load data: 5555 Address: 2AAA
Load data: 1010 Address: 5555
Load data: 3030 Address:
Wait TSBE
Wait
Bank erased FFFFH
Sector erased FFFFH
F16.3
FIGURE ERASE COMMAND SEQUENCE
1999 Silicon Storage Technology, Inc.
354-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST32LH802
Concurrent Operation Load Command Sequence
Flash Program/Erase Initiated
Wait Write Indication
Read Write SRAM
Wait
Flash Operation Completed
F19.0
Concurrent Operation
FIGURE CONCURRENT OPERATION FLOWCHART
1999 Silicon Storage Technology, Inc.
354-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information Device SST32LH802 Speed Suffix1 Suffix2 Package Modifier leads Numeric modifier Package Type LBGA 10mm 12mm Temperature Range Commercial 70°C Industrial -40° 85°C Minimum Endurance 10,000 cycles Read Access Speed
SST32LH802 Valid combinations SST32LH802-70-4C-LBK SST32LH802-70-4I-LBK
Example Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
1999 Silicon Storage Technology, Inc.
354-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST32LH802
Advance Information PACKAGING DIAGRAMS
VIEW BOTTOM VIEW
12.00 0.20 7.00
CORNER 5.00 10.00 0.20
0.50 0.05 (48X) CORNER
SIDE VIEW
1.25 0.10
SEATING PLANE 0.05
0.15
48ba lbga.LBK.10x12-ILL.7
Note:
linear dimensions millimeters (min/max). Coplanarity: (±.05)
48-BALL PROFILE STANDARD-PITCH BALL GRID ARRAY (LBGA) 10MM 12MM PACKAGE CODE:
1999 Silicon Storage Technology, Inc.
354-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST32LH802
SALES OFFICES Area Offices
Customer Service Northwest USA, Rocky Mtns. West Canada Southwest East East Canada Corporate Accounts North America Distribution Asia Pacific East Asia Europe Northern Europe (408) 523-7665 (408) 523-7661 (949) 495-6437 (978) 356-3845 (727) 771-8819 (941) 505-8893 (408) 523-7762 (81) 45-471-1851 (44) 1932-230555 (45) 3833-5000
Advance Information International Sales Representatives Distributors
Australia Austria/Eastern Europe Endrich Bauelemente Vertriebs GMBH Belgium Memec Benelux China/Hong Kong Actron Technology Co., Ltd. (HQ) Hong Kong Actron Technology Co., Ltd. Shanghai Actron Technology Co., Ltd. Shenzhen Actron Technology Co., Ltd. Chengdu Actron Technology Co., Ltd. Beijing Actron Technology Co., Ltd. Wuhan Actron Technology Co., Ltd. Xian MetaTech Limited (HQ) Hong Kong MetaTech Limited Beijing MetaTech Limited Shanghai MetaTech Limited Chengdu MetaTech Limited Fuzhou MetaTech Limited Shenzhen Denmark C-88 Finland Memec Finland France Bron Sevres Germany Endrich Bauelemente Vertriebs GMBH Bramstedt Endrich Bauelemente Vertriebs GMBH Nagold India Team Technology Bangalore Team Technology Hyderabad Team Technology Delhi Ireland Curragh Technology Israel Spectec Electronics Italy Carlo Gavazzi Cefra Japan Asahi Electronics Co., Ltd. Tokyo Asahi Electronics Co., Ltd. Kitakyushu Microtek, Inc. Osaka Microtek, Inc. Tokyo Ryoden Trading Co., Ltd. Osaka Ryoden Trading Co., Ltd. Tokyo Silicon Technology Co., Ltd. Korea Bigshine Korea Co., Ltd. Malaysia MetaTech Serial System Serial System Kuala Lumpur Netherlands Memec Benelux Norway Endrich Elektronikk Philippines MetaTech Ltd. Singapore MetaTech Ltd. Serial System Ltd. (HQ) South Africa Distributors Spain Tekelec Espana S.A. Sweden Memec Scandinavia Switzerland Leading Technologies Taiwan, R.O.C. GCH-Sun Systems Co., Ltd. (GSS) Limited Tonsam Corporation United Kingdom Ambar Components, Ltd.
(61) 3-762 7644 (43) 2-236236-21 (32) 1540-0080 (852) 2727-3978 (86) 21-6482-8021 (86) 755-376-2763 (86) 28-553-2896 (86) 10-6261-0042 (86) 27-8788-7226 (86) 29-831-4585 (852) 2421-2379 (86) 10-6858-2188 (86) 21-6485-7530 (86) 28-5577-415 (86) 591-378-1033 (86) 755-321-9726 (45) 7010-4888 (358)9 8880 (33) 0414 (33) 7900
North American Sales Representatives
Alabama M-Squared, Inc. Huntsville Arizona Reptronix, Ltd. California Costar Northern Associates Diego Westar Company, Inc. Calabasas Westar Company, Inc. Irvine Colorado Lange Sales, Inc. Connecticut Delta Conn Technical Sales Florida M-Squared, Inc. Clearwater M-Squared, Inc. Longwood Georgia M-Squared, Inc. Atlanta Illinois Oasis Sales Corporation Northern Rush West Associates Southern Indiana Applied Data Management Iowa Rush West Associates Kansas Rush West Associates Maryland Nexus Technology Sales Massachusetts Innovative Applied Solutions Michigan Applied Data Management Minnesota Cahill, Schmitz Cahill Missouri Rush West Associates North Carolina M-Squared, Inc. Charlotte M-Squared, Inc. Raleigh Mexico Reptronix, Ltd. York Nova Technology Reagan/Compar Endwell Reagan/Compar Rochester Ohio Applied Data Management Cincinnati Applied Data Management Cleveland Oregon Thorson Pacific, Inc. Texas Technical Marketing, Inc. Carrollton Technical Marketing, Inc. Houston Technical Marketing, Inc. Austin Utah Lange Sales, Inc. Washington Thorson Pacific, Inc. Wisconsin Oasis Sales Corporation Canada Electronics Sales Professionals Ottawa Electronics Sales Professionals Toronto Electronics Sales Professionals Montreal Thorson Pacific, Inc. B.C.
(205) 830-0498 (602) 230-2630 (408) 946-9339 (619) 279-0420 (818) 880-0594 (949) 453-7900 (303) 795-3600 (203) 634-8558 (727) 669-2408 (407) 682-6662 (770) 447-6124 (847) 640-1850 (314) 965-3322 (317) 257-8949 (319) 398-9679 (913) 764-2700 (301) 663-4159 (781) 246-9996 (734) 741-9292 (651) 699-0200 (314) 965-3322 (704) 522-1150 (919) 848-4300 (505) 292-1718 (516) 661-1800 (607) 754-2171 (716) 218-4370 (513) 579-8108 (440) 946-6812 (503) 293-9001 (972) 387-3601 (713) 783-4497 (512) 343-6976 (801) 487-0843 (425) 603-9393 (414) 782-6660 (613) 828-6881 (905) 856-8448 (514) 344-0420 (604) 294-3999
(49) 4192-8784-0 (49) 7452-60070 (91) 80-526-1102 (91) 40-231130 (91) 11-220-5624 (353) 316116 (972) 3-6498404 (39) 2-424-1471 (81) 3-3350-5418 (81) 93-511-6471 (81) 6-6263-5080 (81) 3-5300-5515 (81) 6-6399-3443 (81) 3-5396-6218 (81) 3-3795-6461 (82) 2-832-8881 (60)4-658-4276 (60) 4-657-0204 (60) 3-737-1243 (31) 40-265-9399 (47) (65) 748-4844 (65) 748-4844 (65) 280-0200 (27) 845-5011 (34) 371-7768 (46)8-459-7900 (41) 27-721-7440/43 (886) 2-2555-0880 (886) 2-2698-0098 (886) 2-2651-0011 (44) 1296-397396
Revised 11-8-99
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873
1999 Silicon Storage Technology, Inc.
354-11 11/99
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