SST31LH021 FEATURES: Organized 256K flash 128K SRAM Single 3.0-3.
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Megabit Flash Megabit SRAM ComboMemory
SST31LH021
FEATURES: Organized 256K flash 128K SRAM Single 3.0-3.6V Read Write Operations Concurrent Operation Read from Write SRAM while Erase/Program Flash Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Flash (typical) SRAM Read Standby Current: (typical) Sector-Erase Capability Uniform KByte sectors Fast Read Access Times: Flash: SRAM: PRODUCT DESCRIPTION SST31LH021 256K CMOS flash memory bank combined with 128K CMOS SRAM memory bank manufactured with SST's proprietary, high performance SuperFlash technology. SST31LH021 device writes (SRAM flash) with 3.0-3.6V power supply. monolithic SST31LH021 device conforms JEDEC standard pinouts Software Data Protect (SDP) commands EEPROMs TSOP packages. Featuring high performance Byte-Program, flash memory bank provides maximum Byte-Program time µsec. entire flash memory bank erased programmed byte-by-byte typically seconds, when using interface features such Toggle Data# Polling indicate completion Program operation. protect against inadvertent flash write, SST31LH021 device on-chip hardware software data protection schemes. Designed, manufactured, tested wide spectrum applications, SST31LH021 device offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. SST31LH021 operates independent memory banks with respective bank enable signals. SRAM Flash memory banks superimposed same memory address space. Both memory banks share common address lines, data lines, OE#. memory bank selection done memory bank enable signals. SRAM bank enable signal, BES# selects SRAM bank flash memory bank enable
1999 Silicon Storage Technology, Inc. 353-11 11/99
Latched Address Data Flash Flash Fast Sector-Erase Byte-Program: Sector-Erase Time: (typical) Bank-Erase Time: (typical) Byte-Program Time: (typical) Bank Rewrite Time: seconds (typical) Flash Automatic Erase Program Timing Internal Generation Flash Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Command Packages Available 32-Pin TSOP (8mm 14mm) 40-Pin TSOP (10mm 14mm)
signal, BEF# selects flash memory bank. signal used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory bank. command sequence protects data stored flash memory bank from accidental alteration. SST31LH021 provides added functionality being able simultaneously read from write SRAM bank while erasing programming flash memory bank. SRAM memory bank read written while flash memory bank performs SectorErase, Bank-Erase, Byte-Program concurrently. flash memory Erase Program operations will automatically latch input address data signals complete operation background without further input stimulus requirement. Once internally controlled Erase Program cycle flash bank commenced, SRAM bank accessed Read Write. SST31LH021 device suited applications that both nonvolatile flash memory volatile SRAM memory store code data. system applications, SST31LH021 device significantly improves performance reliability, while lowering power consumption, when compared with multiple chip solutions. SST31LH021 inherently uses less energy during Erase Program than alternative flash technologies. When programming flash device, total energy consumed function applied voltage, current, time application. Since given voltage
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. ComboMemory trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
Megabit Flash Megabit SRAM ComboMemory SST31LH021
Advance Information range, SuperFlash technology uses less current program shorter Erase time, total energy consumed during Erase Program operation less than alternative flash technologies. monolithic ComboMemory eliminates redundant functions when using separate memories similar architecture; therefore, reducing total power consumption. SuperFlash technology provides fixed Erase Program times, independent number Erase/ Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. SST31LH021 device also improves flexibility using single package common signals perform functions previously requiring separate devices. meet high density, surface mount requirements, SST31LH021 device offered 32-pin 40-pin TSOP packages. Figure pinouts. Device Operation ComboMemory uses BES# BEF# control operation either SRAM flash memory bank. contention eliminated monolithic device will recognize both bank enables being simultaneously active. both bank enables asserted (i.e., BEF# BES# both low), BEF# will dominate while BES# ignored appropriate operation will executed flash memory bank. does recommend that both bank enables simultaneously asserted. other address, data, control lines shared; which minimizes power consumption area. device goes into standby when both bank enables raised VIHC. SRAM Operation With BES# BEF# high, SST31LH021 operates 128K CMOS SRAM, with fully static operation requiring external clocks timing strobes. SRAM mapped into first KByte address space device. Read Write cycle times equal. SRAM Read SRAM Read operation SST31LH021 controlled BES#, both have with high, system obtain data from outputs. BES# used SRAM bank selection. When BES# BEF# high, both memory banks deselected. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram, Figure further details. SRAM Write SRAM Write operation SST31LH021 controlled BES#, both have system write SRAM. BES# used SRAM bank selection. During Byte Write operation, addresses data referenced rising edge either BES# WE#, whichever occurs first. Write time measured from last falling edge first rising edge BES# WE#. Refer Write cycle timing diagram, Figure further details. Flash Operation With BEF# active, SST31LH021 operates 256K flash memory. flash memory bank read using common address lines, data lines, OE#. Erase Program operations initiated with JEDEC standard command sequences. Address data latched during commands internally timed Erase Program operations. Flash Read Read operation SST31LH021 device controlled BEF# OE#, both have low, with high, system obtain data from outputs. BEF# used flash memory bank selection. When BEF# BES# high, both banks deselected only standby power consumed. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram (Figure further details. Flash Erase/Program Operation commands used initiate flash memory bank Program Erase operations SST31LH021. commands loaded flash memory bank using standard microprocessor write sequences. command loaded asserting while keeping BEF# high. address latched falling edge BEF#, whichever occurs last. data latched rising edge BEF#, whichever occurs first.
1999 Silicon Storage Technology, Inc.
353-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST31LH021
Advance Information Flash Byte-Program Operation flash memory bank SST31LH021 device programmed byte-by-byte basis. Program operation consists three steps. first step three-byte-load sequence Software Data Protection. second step load byte address byte data. During Byte-Program operation, addresses latched falling edge either BEF# WE#, whichever occurs last. data latched rising edge either BEF# WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth BEF#, whichever occurs first. Program operation, once initiated, will completed, within Figures BEF# controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid Flash Read operations Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands loaded during internal Program operation will ignored. Flash Sector-Erase Operation Sector-Erase operation allows system erase flash memory bank sector sector basis. sector architecture based uniform sector size KBytes. Sector-Erase operation initiated executing six-byte-command load sequence software data protection with Sector-Erase command (30H) sector address (SA) last cycle. address lines A12-A17 will used determine sector address. sector address latched falling edge sixth pulse, while command (30H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Erase determined using either Data# Polling Toggle methods. Figure timing waveforms. commands loaded during Sector-Erase operation will ignored. Flash Bank-Erase Operation SST31LH021 flash memory bank provides BankErase operation, which allows user erase entire flash memory bank array "1's" state. This useful when entire bank must quickly erased. BankErase operation initiated executing six-byte software data protection command sequence with BankErase command (10H) with address 5555H last byte sequence. internal Erase operation begins with rising edge sixth BEF# pulse, whichever occurs first. During internal Erase operation, only valid Flash Read operations Toggle Data# Polling. Table command sequence,
1999 Silicon Storage Technology, Inc.
Figure timing diagram, Figure flowchart. commands loaded during BankErase operation will ignored. Flash Write Operation Status Detection SST31LH021 flash memory bank provides software means detect completion flash memory bank Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle Read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Flash Data# Polling (DQ7) When SST31LH021 flash memory bank internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. flash memory bank then ready next operation. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth BEF#) pulse Program operation. Sector Bank-Erase, Data# Polling valid after rising edge sixth BEF#) pulse. Figure Data# Polling timing diagram Figure flowchart. Flash Toggle (DQ6) During internal Program Erase operation, consecutive attempts read will produce alternating 1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. flash memory bank then ready next operation. Toggle valid after rising edge fourth BE#) pulse Program operation. Sector Bank-Erase, Toggle valid after rising edge sixth BEF#) pulse. Figure Toggle timing diagram Figure flowchart.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
Advance Information Flash Memory Data Protection SST31LH021 flash memory bank provides both hardware software features protect nonvolatile data from inadvertent writes. Flash Hardware Data Protection Noise/Glitch Protection: BEF# pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Flash Write operation. This prevents inadvertent writes during power-up power-down. Flash Software Data Protection (SDP) SST31LH021 provides JEDEC approved software data protection scheme flash memory bank data alteration operations, i.e., Program Erase. Program operation requires inclusion series three-byte sequence. three byte-load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte load sequence. SST31LH021 device shipped with software data protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode, within TRC. Concurrent Read Write Operations SST31LH021 provides unique benefit being able read from write SRAM, while simultaneously erasing programming Flash. device will ignore commands when Erase Program operation progress. This allows data alteration code executed from SRAM, while altering data Flash. following table lists valid states. does recommend that both bank enables, BEF# BES#, simultaneously asserted. CONCURRENT READ/WRITE STATE TABLE Flash Program/Erase Program/Erase SRAM Read Write Product Identification product identification mode identifies device SST31LH021 manufacturer SST. This mode accessed hardware software operations. hardware device Read operation typically used programmer identify correct algorithm SST31LH021 flash memory bank. Users wish software product identification operation identify part (i.e., using device code) when using multiple manufacturers same socket. details, Table hardware operation Table software operation, Figure software entry read timing diagram Figure entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION TABLE Address Manufacturer's Code Device Code 0000H 0001H Data
T1.0
Product Identification Mode Exit/Reset order return standard Read mode, Software Product Identification mode must exited. Exiting accomplished issuing Exit command sequence, which returns device Read operation. Please note that software-reset command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart. Design Considerations recommends high frequency ceramic capacitor placed close possible between VSS, e.g., less than away from device. Additionally, frequency electrolytic capacitor from should placed within pin.
Note that Product Identification commands SDP; therefore, these commands will also ignored while Erase Program operation progress.
1999 Silicon Storage Technology, Inc.
353-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST31LH021
Advance Information FUNCTIONAL BLOCK DIAGRAM SST31LH021
1,048,576 SRAM Cell Array
Address Buffers
BES# BEF#
Control Logic
Buffers
Address Buffers Latches
2,097,152 EEPROM Cell Array
B1.3
BEF#
BES#
Standard Pinout View
BEF# BES# F01A.2
Standard Pinout View
F01.1
32-PIN TSOP PACKAGE (8mm 14mm) FIGURE ASSIGNMENTS TABLE DESCRIPTION Symbol Name A17-A0 Address Inputs
40-PIN TSOP PACKAGE (10mm 14mm)
Functions provide memory addresses. During Flash Sector-Erase A17-A12 address lines will select sector. A17-A0 provide flash address, A16-A0 provide SRAM addresses. output data during read cycles receive input data during write cycles. Data internally latched during Flash Erase/Program cycle. outputs tri-state when BES# BEF# high. activate SRAM memory bank when BES# low. activate Flash memory bank when BEF# low. gate data output buffers. control Write operations. provide 3.0-3.6V supply
T2.5
DQ7-DQ0
Data Input/output
BES# BEF#
SRAM Memory Bank Enable Flash Memory Bank Enable Output Enable Write Enable Power Supply Ground
1999 Silicon Storage Technology, Inc.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
Advance Information TABLE OPERATION MODES SELECTION Mode BES# BEF# Flash Read Flash Program Flash Erase SRAM Read SRAM Write Standby Flash Write Inhibit VIHC VIHC DOUT DOUT High High Z/DOUT High Z/DOUT High Z/DOUT Manufacturer Code (BF) Device Code (18) Code Address Sector address, Bank-Erase VIL, VIL, Table
T3.5
Product Identification Hardware Mode Software Mode
TABLE SOFTWARE COMMAND SEQUENCE FLASH MEMORY BANK
Write Cycle Addr(1) Data Byte-Program 5555H Sector-Erase 5555H Bank-Erase 5555H Software Entry 5555H Software Exit 5555H
Notes: Address format A14-A0 (Hex), Addresses A15, "Don't Care" Command sequence. Sector-Erase; uses address lines Program Byte address Notes Software Entry Command Sequence With Manufacturer Code BFH, read with 31LH021 Device Code 18H, read with device does remain Software Product Mode powered down.
Command Sequence
Write Cycle Addr(1) Data 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH
Write Cycle Addr(1) Data 5555H 5555H 5555H 5555H 5555H
Write Cycle Addr(1) Data BA(3) Data 5555H 5555H
Write Cycle Addr(1) Data 2AAAH 2AAAH
Write Cycle Addr(1) Data SAx(2) 5555H
T4.1
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+ 0.5V Transient Voltage (<20 Ground Potential -1.0V VDD+ 1.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current(1)
Note: Outputs shorted more than second. more than output shorted time.
1999 Silicon Storage Technology, Inc. 353-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST31LH021
Advance Information OPERATING RANGE Range Ambient Temp Commercial Industrial CONDITIONS TEST 3.0-3.6V 3.0-3.6V Input Rise/Fall Time Output Load Figures
TABLE OPERATING CHARACTERISTICS 3.0-3.6V Limits Symbol Parameter Power Supply Current Read Flash SRAM Concurrent Operation Write Flash (Program) SRAM Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage 0.7VDD Input High Voltage (CMOS) VDD-0.3 Output Voltage Output High Voltage VDD-0.2 Supervoltage 11.4 Supervoltage Current
Units Test Conditions Max, open, Address input VIL/VIH, f=1/TRC Min. VIL, BEF# VIL, BES# BEF# VIH, BES# BEF# VIH, BES# VIH, BEF# VIL, BES# BEF# VIH, BES# Max. BEF# BES# VIHC =GND VDD, Max. VOUT =GND VDD, Max. Min. Max. Max. Min. -100µA, Min. BEF# =VIL, BEF# VIL, VIH, Max.
T5.9
VIHC
12.6
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ TPU-WRITE(1)
Minimum
Units
T6.0
Power-up Read Operation Power-up Write Operation
TABLE CAPACITANCE Mhz, other pins open) Parameter Description Test Condition CI/O CIN(1)
Maximum
T7.0
Capacitance Input Capacitance
VI/O
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
1999 Silicon Storage Technology, Inc.
353-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST31LH021
Advance Information TABLE RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification NEND TDR(1) VZAP_HBM(1) VZAP_MM(1) ILTH(1)
Units Cycles Years Volts Volts
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T8.2
Endurance Data Retention Susceptibility Human Body Model Susceptibility Machine Model Latch
10,000 1000
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM MEMORY BANK READ CYCLE TIMING PARAMETERS 3.0-3.6V Symbol Parameter TRCS Read Cycle Time TAAS Address Access Time TBES Bank Enable Access Time TOES Output Enable Access Time TBLZS(1) BES# Active Output TOLZS(1) Output Enable Active Output TBHZS(1) BES# High-Z Output TOHZS Output Disable High-Z Output TOHS Output Hold from Address Change
Unit
T9.3
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM MEMORY BANK WRITE CYCLE TIMING PARAMETERS 3.0-3.6V Symbol Parameter TWCS Write Cycle Time TBWS Bank Enable Write TAWS Address Valid Write TASTS Address Set-up Time TWPS Write Pulse Width TWRS Write recovery Time TDSS Data Set-up Time TDHS Data Hold from Write Time
Unit
T10.3
1999 Silicon Storage Technology, Inc.
353-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST31LH021
Advance Information CHARACTERISTICS TABLE FLASH READ CYCLE TIMING PARAMETERS 3.0-3.6V Symbol Parameter Read Cycle Time Bank Enable Access Time Address Access Time Output Enable Access Time TBLZ BEF# Active Output TOLZ Active Output TBHZ(1) BEF# High High-Z Output TOHZ(1) High High-Z Output Output Hold from Address Change
Units
T11.3
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS 3.0-3.6V Symbol Parameter Byte-Program Time Address Setup Time Address Hold Time BEF# Setup Time BEF# Hold Time TOES High Setup Time TOEH High Hold Time BEF# Pulse Width Pulse Width TWPH Pulse Width High TBPH BEF# Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time TIDA Sector-Erase TSBE Bank-Erase Bank Enable Setup Time Concurrent Operation
Units
T12.1
1999 Silicon Storage Technology, Inc.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
TRCS ADDRESS A16-0
TAAS
BEF# TBES BES# TOES TBLZS TOHS DATA VALID TBHZS HIGH-Z DATA VALID TOLZS TOHZS
DQ7-0
HIGH-Z
F02.3
FIGURE SRAM READ CYCLE TIMING DIAGRAM
TWCS ADDRESS A16-0 ADDRESS TAWS
BEF#
TBWS BES# TWPS TASTS TDSS DQ7-0 DATA VALID
F03.5
TWRS
TDHS
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM
1999 Silicon Storage Technology, Inc.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
ADDRESS A17-0
BES#
BEF#
TOHZ TBHZ HIGH-Z DATA VALID
TOLZ
F18.1
DQ7-0
HIGH-Z
TBLZ
DATA VALID
FIGURE FLASH READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS A17-0 5555 BEF# BES# TWPH 2AAA 5555 ADDR
DQ7-0
DATA BYTE (ADDR/DATA)
F04.1
FIGURE FLASH CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
1999 Silicon Storage Technology, Inc.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
INTERNAL PROGRAM OPERATION STARTS ADDRESS A17-0 5555 2AAA 5555 ADDR
BES# BEF# DQ7-0 DATA BYTE (ADDR/DATA)
F05.1
TCPH
FIGURE FLASH BEF# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A17-0
BES# BEF# TOEH TOES
F06.1
FIGURE FLASH DATA# POLLING TIMING DIAGRAM
1999 Silicon Storage Technology, Inc.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
ADDRESS A17-0 BES# BEF# TOEH TOES
READ CYCLES WITH SAME OUTPUTS F07.1
FIGURE FLASH TOGGLE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS A17-0 5555 2AAA 5555 5555 2AAA
BES#
BEF#
Note:
DQ7-0
F08.2
device also supports BEF# controlled Sector-Erase operation. BEF# signals interchangeable long minimum timings met. (See table Sector Address
FIGURE FLASH CONTROLLED SECTOR-ERASE TIMING DIAGRAM
1999 Silicon Storage Technology, Inc.
353-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST31LH021
SIX-BYTE CODE BANK-ERASE ADDRESS A17-0 5555 2AAA 5555 5555 2AAA 5555 TSBE
BES#
BEF#
DQ7-0
Note:
F17.3
device also supports BEF# controlled Bank-Erase operation. BEF# signals interchangeable long minimum timings met. (See table
FIGURE FLASH CONTROLLED BANK-ERASE TIMING DIAGRAM
Three-byte sequence Software Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
BES#
BEF#
TWPH DQ7-0 DEVICE
F09.3
TIDA
FIGURE FLASH SOFTWARE ENTRY READ
1999 Silicon Storage Technology, Inc.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
BES# TIDA BEF#
DQ7-0
F10.2
FIGURE FLASH SOFTWARE EXIT RESET
ADDRESS A17-0
BEj#
BEj1#
Note:
F20.0
DQ7-0
FIGURE TIMING DIAGRAM ALTERNATING BETWEEN FLASH/SRAM SRAM/FLASH
1999 Silicon Storage Technology, Inc.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
VIHT
INPUT REFERENCE POINTS
OUTPUT
VILT
F11.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (1.6 V)(1) (1.4 V)(1) Input rise fall times (10% 90%)
Output test level common SRAM test standards Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE TESTER HIGH
F12.0
FIGURE TEST LOAD EXAMPLE
1999 Silicon Storage Technology, Inc.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
Start
Load data: Address: 5555
Load data: Address: 2AAA
Load data: Address: 5555
F13.1
Load Byte Address/Byte Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
FIGURE BYTE-PROGRAM ALGORITHM
1999 Silicon Storage Technology, Inc.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
Internal Timer Byte Program/Erase Initiated
Toggle Byte Program/Erase Initiated
Data# Polling Byte Program/Erase Initiated
Wait TBP, TSBE,
Read byte
Read
Program/Erase Completed
Read same byte
true data?
Does match?
Program/Erase Completed
Program/Erase Completed
F14.0
FIGURE WAIT OPTIONS
1999 Silicon Storage Technology, Inc.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
Software Product Entry Command Sequence Software Product Exit Reset Command Sequence
Load data: Address: 5555
Load data: Address: 5555
Load data: Address:
Load data: Address: 2AAA
Load data: Address: 2AAA
Wait TIDA
Return normal operation
Load data: Address: 5555
Load data: Address: 5555
Wait TIDA
Wait TIDA
F15.1
Read Software
Return normal operation
FIGURE SOFTWARE PRODUCT COMMAND FLOWCHARTS
1999 Silicon Storage Technology, Inc.
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Megabit Flash Megabit SRAM ComboMemory SST31LH021
Chip-Erase Command Sequence Load data: Address: 5555
Sector-Erase Command Sequence Load data: Address: 5555
Load data: Address: 2AAA
Load data: Address: 2AAA
Load data: Address: 5555
Load data: Address: 5555
Load data: Address: 5555
Load data: Address: 5555
Load data: Address: 2AAA
Load data: Address: 2AAA
Load data: Address: 5555
Load data: Address:
Wait TSBE
Wait
Chip erased
Sector erased
F16.1
FIGURE ERASE COMMAND SEQUENCE
1999 Silicon Storage Technology, Inc.
353-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST31LH021
Advance Information Device SST31LH021 Speed Suffix1 Suffix2 Package Modifier leads leads Numeric modifier Package Type TSOP (die 14mm, 10mm 14mm Temperature Range Commercial 70°C Industrial -40° 85°C Minimum Endurance 10,000 cycles Read Access Speed Version
SST31LH021 Valid combinations SST31LH021-70-4C-WI SST31LH021-70-4C-WH SST31LH021-70-4I-WI SST31LH021-70-4I-WH
Example Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
1999 Silicon Storage Technology, Inc.
353-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST31LH021
Advance Information PACKAGING DIAGRAMS
IDENTIFIER 1.05 0.95
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
Note:
Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (min/max). Coplanarity: (±.05)
32.TSOP-WH-ILL.3
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 14MM PACKAGE CODE:
1999 Silicon Storage Technology, Inc.
353-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST31LH021
1.05 0.95
IDENTIFIER
.270 .170 10.10 9.90
0.15 0.05
12.50 12.30
0.60 0.40
14.20 13.80
Note:
Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (min/max). 40.TSOP-WI-ILL.2 Coplanarity: (±.05)
40-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 10MM 14MM PACKAGE CODE:
1999 Silicon Storage Technology, Inc.
353-11 11/99
Megabit Flash Megabit SRAM ComboMemory SST31LH021
SALES OFFICES
Area Offices
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(61) 3-762 7644 (43) 2-236236-21 (32) 1540-0080 (852) 2727-3978 (86) 21-6482-8021 (86) 755-376-2763 (86) 28-553-2896 (86) 10-6261-0042 (86) 27-8788-7226 (86) 29-831-4585 (852) 2421-2379 (86) 10-6858-2188 (86) 21-6485-7530 (86) 28-5577-415 (86) 591-378-1033 (86) 755-321-9726 (45) 7010-4888 (358)9 8880 (33) 0414 (33) 7900
North American Sales Representatives
Alabama M-Squared, Inc. Huntsville Arizona Reptronix, Ltd. California Costar Northern Associates Diego Westar Company, Inc. Calabasas Westar Company, Inc. Irvine Colorado Lange Sales, Inc. Connecticut Delta Conn Technical Sales Florida M-Squared, Inc. Clearwater M-Squared, Inc. Longwood Georgia M-Squared, Inc. Atlanta Illinois Oasis Sales Corporation Northern Rush West Associates Southern Indiana Applied Data Management Iowa Rush West Associates Kansas Rush West Associates Maryland Nexus Technology Sales Massachusetts Innovative Applied Solutions Michigan Applied Data Management Minnesota Cahill, Schmitz Cahill Missouri Rush West Associates North Carolina M-Squared, Inc. Charlotte M-Squared, Inc. Raleigh Mexico Reptronix, Ltd. York Nova Technology Reagan/Compar Endwell Reagan/Compar Rochester Ohio Applied Data Management Cincinnati Applied Data Management Cleveland Oregon Thorson Pacific, Inc. Texas Technical Marketing, Inc. Carrollton Technical Marketing, Inc. Houston Technical Marketing, Inc. Austin Utah Lange Sales, Inc. Washington Thorson Pacific, Inc. Wisconsin Oasis Sales Corporation Canada Electronics Sales Professionals Ottawa Electronics Sales Professionals Toronto Electronics Sales Professionals Montreal Thorson Pacific, Inc. B.C.
(205) 830-0498 (602) 230-2630 (408) 946-9339 (619) 279-0420 (818) 880-0594 (949) 453-7900 (303) 795-3600 (203) 634-8558 (727) 669-2408 (407) 682-6662 (770) 447-6124 (847) 640-1850 (314) 965-3322 (317) 257-8949 (319) 398-9679 (913) 764-2700 (301) 663-4159 (781) 246-9996 (734) 741-9292 (651) 699-0200 (314) 965-3322 (704) 522-1150 (919) 848-4300 (505) 292-1718 (516) 661-1800 (607) 754-2171 (716) 218-4370 (513) 579-8108 (440) 946-6812 (503) 293-9001 (972) 387-3601 (713) 783-4497 (512) 343-6976 (801) 487-0843 (425) 603-9393 (414) 782-6660 (613) 828-6881 (905) 856-8448 (514) 344-0420 (604) 294-3999
(49) 4192-8784-0 (49) 7452-60070 (91) 80-526-1102 (91) 40-231130 (91) 11-220-5624 (353) 316116 (972) 3-6498404 (39) 2-424-1471 (81) 3-3350-5418 (81) 93-511-6471 (81) 6-6263-5080 (81) 3-5300-5515 (81) 6-6399-3443 (81) 3-5396-6218 (81) 3-3795-6461 (82) 2-832-8881 (60)4-658-4276 (60) 4-657-0204 (60) 3-737-1243 (31) 40-265-9399 (47) (65) 748-4844 (65) 748-4844 (65) 280-0200 (27) 845-5011 (34) 371-7768 (46)8-459-7900 (41) 27-721-7440/43 (886) 2-2555-0880 (886) 2-2698-0098 (886) 2-2651-0011 (44) 1296-397396
Revised 11-8-99
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873
1999 Silicon Storage Technology, Inc.
353-11 11/99
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