System Clock Buffer PRODUCT DESCRIPTION device high fanout s
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CB683
System Clock Buffer
PRODUCT DESCRIPTION
device high fanout system clock buffer. primary application create large quantity clocks needed support wide range applications that requires those clock loads signal that referenced single existing clock. Loads supported. chief applications this component where long traces used transport clocks from their generating devices their loads. creation degradation waveform rise fall times greatly reduced running single reference clock trace this device then using regenerate clock that drives shorter traces. Using these devices therefore minimized board real estate saved.
output buffer divided into groups high clock fanout applications clocks. Each output internally disabled reduction further reduced requiring only single long trace clock source. VDD= volts each clock group Output frequency range skew between output clocks derived from same input pin. skew between output clocks when input pins connected together. 52-pin package
CONNECTION DIAGRAM
BLOCK DIAGRAM
VDD1 VDD2 CLK[3:4] CIN1 VDD3 CLK[5:6] VDD4 CLK[7:8] VDD5 CLK[9:10] VDD6 CLK[11:12] VDD7 SDATA SCLK CLK[1:2]
CLK19 CLK18 CLK17 VDD9 CLK16 CLK15 VDD8 CLK14 CLK13 VDD7
Control Logic
CLK[13:14] VDD8 CLK[15:16] VDD9 CLK[17,18] VDD10 CLK[19:21] VDD11 CLK[22,23]
CLK20 CLK21 VDD10 CIN1 SCLK SDATA CIN2 CIN3 VDD11 CLK24 CLK23
CLK12 CLK11 VDD6 CLK10 CLK9 VDD5 CLK8 CLK7 VDD4
CIN2
CIN3
CLK24
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
CLK22 VDD1 CLK1 CLK2 VDD2 CLK3 CLK4 VDD3 CLK5 CLK6
Rev.2.1
11/20/98 Page
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