Organization Bits Single Power Supply Industry Standard 32-Pin Dual In

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Organization Bits Single Power Supply Industry Standard 32-Pin Dual In

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TMS27C040 524288 8-BIT ERASABLE TMS27PC040 524288 8-BIT PROGRAMMABLE READ-ONLY MEMORY
Organization Bits Single Power Supply Industry Standard 32-Pin Dual In-Line Package 32-Lead Plastic Leaded Chip Carrier Inputs Outputs Fully Compatible Static Operation Clocks, Refresh) Access Cycle Time '27C/ PC040-10 '27C/ PC040-12 '27C/ PC040-15 8-Bit Output Microprocessor-Based Systems Power-Saving CMOS Technology 3-State Output Buffers 400-mV Assured Noise Immunity With Standard Loads Latchup Immunity Input Output Pins Pullup Resistors Required Power Dissipation (VCC Active Worst Case Standby 0.55 Worst (CMOS-Input Levels) Temperature Range Options
TMS27C040 PACKAGE VIEW
TMS27PC040 PACKAGE VIEW
description
TMS27C040 devices 8-bit 304-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories (EPROMs). TMS27PC040 devices 8-bit 304-bit), one-time programmable (OTP) electrically programmable read-only memories (PROMs). These devices fabricated using CMOS technology high speed simple interface with bipolar circuits. inputs including program data inputs) driven Series circuits. Each output drive Series circuit without external resistors.
NOMENCLATURE Address Inputs Inputs (programming) Outputs Chip Enable Output Enable Ground Supply 13-V Power Supply
Only program mode. Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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TMS27C040 524288 8-BIT ERASABLE TMS27PC040 524288 8-BIT PROGRAMMABLE READ-ONLY MEMORY
description (continued)
data outputs 3-state connecting multiple devices common TMS27C040 offered 600-mil ceramic dual-in-line package suffix). TMS27C040 offered with choices temperature ranges 70°C suffix) 40°C 85°C suffix). (See Table TMS27PC040 offered 32-lead plastic leaded chip carrier package suffix). TMS27PC040 offered with choices temperature ranges 70°C suffix) -40°C 85°C suffix). Table Temperature Range Suffixes
SUFFIX OPERATING FREE-AIR TEMPERATURE RANGES 70°C TMS27C040-XXX TMS27PC040-XXX 40°C 85°C
FUNCTION
These EPROMs PROMS operate from single supply read mode), they ideal microprocessor-based systems. other supply needed programming. programming signals level. programming outside system, existing EPROM programmers used.
operation
seven modes operation listed Table read mode requires single supply. inputs level except during programming signature mode. Table Operation Modes
MODE Read Output Disable Standby Programming Program Inhibit Verify Signature Mode FUNCTION Data Hi-Z Hi-Z Data Hi-Z Data Code Device Code
read/ output disable When outputs more TMS27C040s TMS27PC040s connected parallel same bus, output particular device circuit read with interference from competing outputs other devices. read output single device, level signal applied pins. other devices circuit should have their outputs disabled applying high level signal these pins. latchup immunity Latchup immunity TMS27C040 TMS27PC040 minimum inputs outputs. This feature provides latchup immunity beyond potential transients P.C. board level when EPROM interfaced industry standard logic devices. input output layout approach controls latchup without compromising performance packing density.
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TMS27C040 524288 8-BIT ERASABLE TMS27PC040 524288 8-BIT PROGRAMMABLE READ-ONLY MEMORY
power down Active supply current reduced from applying high input applying high CMOS input this mode outputs high-impedance state. erasure TMS27C040) Before programming, TMS27C040 EPROM erased exposing chip through transparent high intensity UV-light (wavelength 2537 recommended minimum exposure dose intensity exposure time) 15-Ws typical 12-mW cm2, filterless lamp erases device minutes. lamp must located about above chip during erasure. After erasure, bits high state. Normal ambient light contains correct wavelength erasure; therefore, when using TMS27C040, window must covered with opaque label. After erasure (all bits logic high state), logic lows programmed into desired locations. programmed erased only light. initializing TMS27PC040) TMS27PC040 PROM provided with bits logic high state, then logic lows programmed into desired locations. Logic lows programmed into PROM cannot erased. SNAP! Pulse programming TMS27C040 TMS27PC040 programmed using SNAP! Pulse programming algorithm. programming sequence shown SNAP! Pulse programming flow chart shown Figure initial setup VIH, VIH. Once initial location selected, data presented parallel (eight bits) pins through DQ7. Once addresses data stable, programming mode achieved when pulsed (VIL) with pulse duration tw(PGM). Every location programmed only once before going interactive mode. interactive mode, word verified VIH, VIL. correct data read, programming performed pulling with pulse duration tw(PGM). This sequence verification programming performed maximum times. When device fully programmed, bytes verified with 10%. program inhibit Programming inhibited maintaining high level inputs pins. program verify Programmed bits verified with when VIL, VIH. signature mode signature mode provides access binary code identifying manufacturer type. This mode activated when (pin forced identifier bytes accessed toggling other addresses must held low. signature code TMS27C040 9750. selects manufacturer's code (Hex), high selects device code (Hex), shown Table Table Signature Mode
IDENTIFIER MANUFACTURER CODE DEVICE CODE PINS
VIL, A1-A8 VIL, A10-A18 VIL, VCC.
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TMS27C040 524288 8-BIT ERASABLE TMS27PC040 524288 8-BIT PROGRAMMABLE READ-ONLY MEMORY
Start
Address First Location 0.25 0.25 Program Pulse Increment Address Program Mode
Last Address?
Address First Location Program Pulse
Increment Address
Verify Byte
Fail X=X+1 Interactive Mode
Pass
Last Address?
Device Failed
Compare Bytes Original Data Pass Device Passed
Fail
Final Verification
Figure SNAP! Pulse Programming Flow Chart
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TMS27C040 524288 8-BIT ERASABLE TMS27PC040 524288 8-BIT PROGRAMMABLE READ-ONLY MEMORY
logic symbol
EPROM
[PWR DWN]
This symbol accordance with ANSI IEEE 91-1984 Publication 617-12. numbers package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Supply voltage range, (see Note Input voltage range (see Note inputs except Output voltage range, with respect (see Note Operating free-air temperature range ('27C040-_ '27PC040-_ _FML) 70°C Operating free-air temperature range ('27C040-_ '27PC040 FME) 40°C 85°C Storage temperature range, Tstg 65°C 125°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect GND.
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TMS27C040 524288 8-BIT ERASABLE TMS27PC040 524288 8-BIT PROGRAMMABLE READ-ONLY MEMORY
recommended operating conditions
Supply voltage Supply voltage High-level High level input voltage Low-level level input voltage Operating free-air temperature '27C040-_ '27PC040-_ _FML Read mode (see Note SNAP! Pulse programming algorithm Read mode SNAP! Pulse programming algorithm CMOS CMOS 6.25 12.75 6.75 13.25 UNIT
Operating free-air temperature '27C040-_ NOTE must applied before same time removed after same time VPP. device must inserted into removed from board when applied.
electrical characteristics over recommended ranges supply voltage operating free-air temperature
PARAMETER IPP1 IPP2 ICC1 High-level High level output voltage level output voltage Low-level Input current (leakage) Output current (leakage) supply current supply current (during program pulse) supply current (standby) TTL-Input level CMOS-Input level TEST CONDITIONS 12.75 UNIT
ICC2
supply current (active)
VIL, tcycle minimum cycle time, outputs open
Minimum cycle time maximum access time.
capacitance over recommended ranges supply voltage operating free-air temperature,
PARAMETER Input capacitance Output capacitance typical values 25°C nominal voltages. Capacitance measurements made sample basis only. TEST CONDITIONS UNIT
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TMS27C040 524288 8-BIT ERASABLE TMS27PC040 524288 8-BIT PROGRAMMABLE READ-ONLY MEMORY
switching characteristics over recommended ranges operating conditions (see Notes
PARAMETER ta(A) ta(E) ten(G) tdis tv(A) Access time from address Access time from chip enable Output enable time from Output disable time from whichever occurs first Output data valid time after change address, whichever occurs first Series load, Input Input TEST CONDITIONS '27C040-10 PC040-10 '27C040-12 PC040-12 '27C040-15 PC040-15 UNIT
Value calculated from 0.5-V delta measured output level. NOTES: switching characteristics input pulse levels Timing measurements made logic high logic low. (See Figure Common test conditions apply tdis except during programming.
switching characteristics programming: (SNAP! Pulse), 25°C (see Note
PARAMETER tdis(G) ten(G) Output disable time from Output enable time from UNIT
NOTE switching characteristics input pulse levels Timing measurements made logic high logic low. (See Figure
timing requirements programming
tw(PGM) tsu(A) tsu(E) tsu(G) tsu(D) tsu(VPP) tsu(VCC) th(A) th(D) Pulse duration, program Setup time, address Setup time, Setup time, Setup time, data Setup time, Setup time, Hold time, address Hold time, data SNAP! Pulse programming algorithm UNIT
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TMS27C040 524288 8-BIT ERASABLE TMS27PC040 524288 8-BIT PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.08 Output Under Test (see Note
NOTES: includes probe fixture capacitance. testing inputs driven logic high logic low. Timing measurements made logic high logic both inputs outputs.
Figure Testing Output Load Circuit Waveform
Addresses Valid ta(A) ta(E) tdis ten(G) Hi-Z tv(A) Output Valid Hi-Z
Figure Read-Cycle Timing
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TMS27C040 524288 8-BIT ERASABLE TMS27PC040 524288 8-BIT PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
Verify Program tsu(A) Data-In Stable tsu(D) tsu(VPP) tsu(E) th(D) tsu(VCC) tsu(G) tw(PGM) 13-V 6.5-V SNAP! Pulse programming Hi-Z ten(G) Data-Out Stable tdis(G) Address Stable th(A)
Figure Program-Cycle Timing (SNAP! Pulse Programming)
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TMS27C040 524288 8-BIT ERASABLE TMS27PC040 524288 8-BIT PROGRAMMABLE READ-ONLY MEMORY
(R-PQCC-J32)
PLASTIC J-LEADED CHIP CARRIER
Seating Plane 0.004 (0,10) 0.140 (3,56) 0.132 (3,35) 0.495 (12,57) 0.485 (12,32) 0.453 (11,51) 0.447 (11,35) 0.129 (3,28) 0.123 (3,12) 0.049 (1,24) 0.043 (1,09) 0.008 (0,20)
0.020 (0,51) 0.015 (0,38) 0.595 (15,11) 0.585 (14,86) 0.553 (14,05) 0.547 (13,89) 0.030 (0,76)
0.050 (1,27)
4040201-4 03/95 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-016
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TMS27C040 524288 8-BIT ERASABLE TMS27PC040 524288 8-BIT PROGRAMMABLE READ-ONLY MEMORY
(R-CDIP-T**)
SHOWN
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
0.065 (1,65) 0.045 (1,14) 0.090 (2,29) 0.060 (1,53)
Lens Protrusion 0.010 (0,25) 0.175 (4,45) 0.140 (3,56)
0.018 (0,46)
Seating Plane 0.125 (3,18) 0.100 (2,54) 0.022 (0,56) 0.014 (0,36) 0.012 (0,30) 0.008 (0,20)
PINS** NARR
WIDE NARR 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.265(32,13) 1.265(32,13) 1.235(31,37) 1.235(31,37) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50)
WIDE NARR 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.465(37,21) 1.465(37,21) 1.435(36,45) 1.435(36,45) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50)
WIDE NARR 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.668(42,37) 1.668(42,37) 1.632(41,45) 1.632(41,45) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50)
WIDE 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 2.068(52,53) 2.068(52,53) 2.032(51,61) 2.032(51,61) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50) 4040084 04/95
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with ceramic using glass frit. Index point provided terminal identification only press ceramic glass frit seal only.
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Copyright 1998, Texas Instruments Incorporated

Organization Bits Single Power Supply Industry Standard 32-Pin Dual In

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