Organization Bits Single Power Supply Operationally Compatible With Ex

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Organization Bits Single Power Supply Operationally Compatible With Ex

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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
Organization Bits Single Power Supply Operationally Compatible With Existing Megabit EPROMs Industry Standard 32-Pin Dual-In-line Package 32-Lead Plastic Leaded Chip Carrier Inputs Outputs Fully Compatible ±10% Tolerance Access Cycle Time '27C/ PC020-10 '27C/ PC020-12 '27C/ PC020-15 '27C/ PC020-20 '27C/ PC020-25 8-Bit Output Microprocessor-Based Systems Very High-Speed SNAP! Pulse Programming Power Saving CMOS Technology 3-State Output Buffers Minimum Noise Immunity With Standard Loads Latchup Immunity Input Output Pins Pullup Resistors Required Power Dissipation (VCC Active Worst Case Standby 0.55 Worst Case (CMOS-Input Levels) Temperature Range Options
PACKAGE VIEW
TMS27PC020 PACKAGE VIEW
description
TMS27C020 series 8-bit 152-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories (EPROMs). TMS27PC020 series one-time programmable (OTP) electrically programmable read-only memories (PROMs).
NOMENCLATURE Address Inputs Inputs (programming) Outputs Chip Enable Output Enable Ground Program Power Supply 13-V Power Supply
Only program mode
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
description (continued)
These devices fabricated using power-saving CMOS technology high speed simple interface with bipolar circuits. inputs including program data inputs) driven Series circuits without external pullup resistors. Each output drive Series circuit without external resistors. TMS27C020 EPROM offered dual-in-line ceramic package suffix) designed insertion mounting hole rows 15,2-mm (600-mil) centers. TMS27C020 also offered with choices temperature ranges 70°C suffix) 40°C 85°C suffix). Table TMS27PC020 offered 32-lead plastic leaded chip carrier using 1,25 mil) lead spacing suffix). TMS27PC020 offered with choices temperature ranges 70°C (FML suffix) 40°C 85°C (FME suffix). Table Table Temperature Range Suffixes
SUFFIX OPERATING TEMPERATURE RANGES 70°C TMS27C040-XXX TMS27PC040-XXX 85°C
FUNCTION
These EPROMs operate from single supply read mode), they ideal microprocessor-based systems. other supply needed programming. programming signals level. programming outside system, existing EPROM programmers used.
operation
seven modes operation TMS27C020 TMS27PC020 listed Table read mode requires single supply. inputs level except during programming signature mode. Table Operation Modes
MODE FUNCTION READ OUTPUT DISABLE STANDBY PROGRAMMING VERIFY PROGRAM INHIBIT SIGNATURE MODE CODE Data Hi-Z Hi-Z Data Data Hi-Z DEVICE
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
read/ output disable When outputs more TMS27C020s TMS27PC020s connected parallel same bus, output particular device circuit read with interference from competing outputs other devices. read output single device, level signal applied pins. other devices circuit should have their outputs disabled applying high level signal these pins. latchup immunity Latchup immunity TMS27C020 TMS72PC020 minimum inputs outputs. This feature provides latchup immunity beyond potential transients P.C. board level when EPROM interfaced industry standard logic devices. input output layout approach controls latchup without compromising performance packing density. power down Active supply current reduced from applying high input applying high CMOS input this mode outputs high-impedance state. erasure Before programming, TMS27C020 erased exposing chip through transparent high intensity ultraviolet light (wavelength 2537 recommended minimum exposure dose intensity exposure time) 15-Ws cm2. typical 12-mW cm2, filterless lamp erases device minutes. lamp should located about above chip during erasure. After erasure, bits high state. should noted that normal ambient light contains correct wavelength erasure. Therefore, when using TMS27C020, window should covered with opaque label. After erasure (all bits logic high state), logic lows programmed into desired locations. programmed erased only ultraviolet light. SNAP! Pulse programming TMS27C020 TMS27PC020 programmed using SNAP! Pulse programming algorithm, illustrated flowchart Figure which programs nominal time twenty-six seconds. Actual programming time varies function programmer used. SNAP! Pulse programming algorithm uses initial pulse microseconds (µs) followed byte verification determine when addressed byte been successfully programmed. 100-µs pulses byte provided before failure recognized. programming mode achieved when equals VIL, VIH. Data presented parallel (eight bits) pins through DQ7. Once addresses data stable, pulsed low. More than device programmed when devices connected parallel. Locations programmed order. When SNAP! Pulse programming routine complete, bits verified with 10%. program inhibit Programming inhibited maintaining high level input pins. program verify Programmed bits verified with equals when VIL, VIL, VIH. signature mode signature mode provides access binary code identifying manufacturer type. This mode activated when (pin forced identifier bytes accessed toggling other addresses must held low. signature code TMS27C020 9732. selects manufacturer's code Hex), high selects device code Hex), shown Table
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
signature mode (continued)
Table Signature Mode
IDENTIFIER MANUFACTURER CODE PINS
DEVICE CODE VIL, VIL, VIL, VCC.
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
Start
Address First Location 0.25 0.25 Program Pulse Increment Address Program Mode
Last Address?
Address First Location Program Pulse
Increment Address
Verify Byte
Fail X=X+1 Interactive Mode
Pass
Last Address?
Device Failed
Compare Bytes Original Data Pass Device Passed
Fail
Final Verification
Figure SNAP! Pulse Programming Flowchart
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
logic symbol
EPROM
[PWR DOWN]
This symbol accordance with ANSI IEEE 91-1984 Publication 617-12. numbers package.
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Supply voltage range, Input voltage range (see Note inputs except 13.5 Output voltage range, with respect (see Note Operating free-air temperature range ('27C020-_ '27PC020_ _FML) 70°C Operating free-air temperature range ('27C020-_ _JE, '27PC020-_ _FME) 40°C 85°C Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect GND.
recommended operating conditions
Supply voltage Supply voltage High-level High level input voltage Low-level level input voltage Operating free-air temperature Operating free-air temperature Read mode (see Note SNAP! Pulse programming algorithm Read mode SNAP! Pulse programming algorithm CMOS CMOS '27C020-_ _JL, '27PC020-_ _FML '27C020-_ _JE, '27PC020-_ _FME 6.25 12.75 6.75 13.25 UNIT
NOTE must applied before same time removed after same time VPP. device must inserted into removed from board when applied.
electrical characteristics over full ranges operating conditions
PARAMETER IPP1 IPP2 ICC1 High-level High level output voltage Low-level level output voltage Input current (leakage) Output current (leakage) supply current supply current (during program pulse) supply current (standby) TTL-input level CMOS-input level TEST CONDITIONS tcycle minimum cycle time, outputs open UNIT
ICC2
supply current (active)
Minimum cycle time maximum access time.
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
capacitance over recommended ranges supply voltage operating free-air temperature,
PARAMETER Input capacitance Output capacitance Capacitance measurements made sample basis only. typical values 25°C nominal voltages. TEST CONDITIONS UNIT
switching characteristics over full ranges recommended operating conditions (see Notes
PARAMETER Access time from address Access time from chip enable Output enable time from Output disable time from whichever occurs first Output data valid time after change address, whichever occurs Series load, Input Input TEST CONDITIONS '27C020-10 '27PC020-10 ta(A) '27C020-12 '27PC020-12 '27C020-15 '27PC020-15 27C020-20 27PC020-20 '27C020-25 '27PC020-25 UNIT
ta(E)
ten(G)
tdis
tv(A)
Value calculated from 0.5-V delta measured output level. This parameter sampled 100% tested. NOTES: switching characteristics, input pulse levels Timing measurements made logic high logic low. (See Figure Common test conditions apply tdis except during programming.
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
switching characteristics programming: (SNAP! Pulse), 25°C (see Note
PARAMETER tdis(G) ten(G) Output disable time from Output enable time from UNIT
NOTE switching characteristics input pulse levels Timing measurements made logic high logic (See Figure
timing requirements programming
tw(PGM) tsu(A) tsu(E) tsu(G) tsu(D) tsu(VPP) tsu(VCC) th(A) th(D) Pulse duration, program Setup time, address Setup time, Setup time, Setup time, data Setup time, Setup time, Hold time, address Hold time, data SNAP! Pulse programming algorithm UNIT
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
PARAMETER MEASUREMENT INFORMATION
2.08 Output Under Test (see Note
NOTES: includes probe fixture capacitance. testing inputs driven logic high logic low. Timing measurements made logic high logic both inputs outputs.
Figure Testing Output Load Circuit Waveform
Addresses Valid ta(A)
ta(E) ten(G) Hi-Z tdis tv(A) Output Valid Hi-Z
Figure Read-Cycle Timing
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
PARAMETER MEASUREMENT INFORMATION
Verify Program tsu(A) Data-In Stable tsu(D) tsu(VPP) tsu(VCC) tsu(E) tsu(G) tw(PGM) tdis(G) ten(G) characteristics device must accommodated programmer. 13-V 6.5-V SNAP! Pulse programming. ten(G) th(D) Address Stable th(A) Data-Out Valid tdis(G) Address
Figure Program-Cycle Timing (SNAP! Pulse Programming)
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
(R-PQCC-J32)
PLASTIC J-LEADED CHIP CARRIER
Seating Plane 0.004 (0,10) 0.140 (3,56) 0.132 (3,35) 0.495 (12,57) 0.485 (12,32) 0.453 (11,51) 0.447 (11,35) 0.129 (3,28) 0.123 (3,12) 0.049 (1,24) 0.043 (1,09) 0.008 (0,20)
0.020 (0,51) 0.015 (0,38) 0.595 (15,11) 0.585 (14,86) 0.553 (14,05) 0.547 (13,89) 0.030 (0,76)
0.050 (1,27)
4040201-4 03/95 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-016
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
(R-CDIP-T**)
SHOWN
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
0.065 (1,65) 0.045 (1,14) 0.090 (2,29) 0.060 (1,53)
Lens Protrusion 0.010 (0,25) 0.175 (4,45) 0.140 (3,56)
0.018 (0,46)
Seating Plane 0.125 (3,18) 0.100 (2,54) 0.022 (0,56) 0.014 (0,36) 0.012 (0,30) 0.008 (0,20)
PINS** NARR
WIDE NARR 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.265(32,13) 1.265(32,13) 1.235(31,37) 1.235(31,37) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50)
WIDE NARR 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.465(37,21) 1.465(37,21) 1.435(36,45) 1.435(36,45) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50)
WIDE NARR 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.668(42,37) 1.668(42,37) 1.632(41,45) 1.632(41,45) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50)
WIDE 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 2.068(52,53) 2.068(52,53) 2.032(51,61) 2.032(51,61) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50) 4040084 04/95
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with ceramic using glass frit. Index point provided terminal identification only press ceramic glass frit seal only.
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TMS27C020 262144 8-BIT ERASABLE TMS27PC020 262144 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
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IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated

Organization Bits Single Power Supply Operationally Compatible With Ex

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