Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs App
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SC674
Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs
Approved Product PRODUCT FEATURES
Supports Pentium& PentiumII using 440LX chipset. clocks SDRAM clocks DIMMs. synchronous clocks. Optional common mixed supply mode: (VDD VDDP VDDC 3.3V) (VDD VDDP 3.3V, VDDC 2.5V) Supports Power Management 250ps skew SDRAM clocks. 250ps skew among clocks. 2-Wire serial interface Programmable registers featuring: enable/disable each output mode tri-state, test, normal IOAPIC clocks multiprocessor support. 56-pin SSOP package
FREQUENCY TABLE
60.0 66.6 30.0 33.3
CONNECTION DIAGRAM
IOAPIC3 XOUT VDDP PCICLK_F PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 VDDP PCICLK6 SDRAM12 SDRAM11 VDDP SDRAM10 SDRAM9 SDRAM16 SDRAM15 VDDP SDATA SDCLK VDDC IOAPIC1 IOAPIC2 CPUCLK1 CPUCLK2 VDDC CPUCLK3 CPUCLK4 CPUCLK5 SDRAM1 SDRAM2 VDDP SDRAM3 SDRAM4 SDRAM5 SDRAM6/ VDDP SDRAM7 SDRAM8 SDRAM13 SDRAM14 Mode
BLOCK DIAGRAM
XOUT IOAPIC(1:3) VDDC VDDC
Sdata Sclock
Clock Gen.
CPUCLK(1:5)
PCICLK(1:6) PCICLK_F
SDRAM(1:5, 9:16) SDRAM(1:16)
Mode
PCI_STOP# CPU_STOP# PWR_DWN#
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.
4/23/97 Page
SC674
Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs
Approved Product DESCRIPTION
Name
TYPE
OSC1
Description
On-chip reference oscillator input pin. Requires either external crystal (nominally 14.318 MHz) externally generated reference signal O-chip reference oscillator output pin. Drives external crystal When externally generated reference signal used, left unconnected Frequency select input pin. frequency select table page Clock outputs. frequency table specified page IOAPIC clock multi processor support. Fixed frequency 14.31818 Mhz. (2.5 supply VDDI) clocks. frequency select table page clock that ceases only when (pin ascerted. frequency select table page Input Output mode control pins Serial control interface data pin. Serial control interface clock pin. Ground pins device.
Xout
OSC1
CPUCLK(1:5) IOAPIC(1:2) PCICLK(1:6) PCI_F MODE SDATA SCLK
VDDC VDDC VDDP VDDP
PADI4 BUF1 BUF2 BUF4 BUF4
VDDP VDDC SDRAM(1:5), (8:16)
VDDP VDDP
Buffered copy 14.31818 reference oscillator. Volt power supply SDRAM, PCI_F clock output buffers. power supply IOAPIC clock buffers. Power supply pins analog circuits core logic High drive SDRAM output clocks.
SDRAM7
VDDP
SDRAM6
VDDP
SDRAM5
VDDP
Bidirectional pin. When MODE HIGH, acts SDRAM clock. When MODE HIGH, acts input when driven low, will synchronously stop clocks (except PCI_F) logic level. Bidirectional pin. When MODE HIGH (logic this acts SDRAM clock. When MODE (logic HIGH this acts input when driven logic level, will synchronously stop clocks logic level. Bi-directional pin. When MODE HIGH (logic this acts SDRAM clock. When MODE (logic high this acts input when driven logic level will enter shutdown mode internal circuitry turned off.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.
4/23/97 Page
SC674
Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs
Approved Product POWER MANAGEMENT FUNCTIONS
clocks individually enabled stopped 2-wire control interface. clocks stopped state. clocks maintain valid high period transitions from running stopped transitions from stopped running when chip powered down. power VCOs will stabilize correct pulse widths within about CPU, clocks transition between running stopped waiting positive edge PCICLK_F followed negative edge clock interest, after which high levels output either enabled disabled. When MODE=0, pins inputs PCI_STOP# CPU_STOP# respectively (when MODE=1, these functions available). particular output enabled only when both serial interface these pins indicate that should enabled. devices clocks disabled according following table order reduce power consumption. clocks stopped state. clocks maintain valid high period transitions from running stopped. high transitions PWR_DWN#, external circuitry should allow VCOs stabilize prior assuming clock periods correct. clocks transition between running stopped waiting positive edge PCICLK_F followed negative edge clock interest, after which high levels output either enabled disabled. CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK RUNNING RUNNING PCICLK RUNNING RUNNING OTHER CLKs RUNNING RUNNING RUNNING RUNNING XTAL VCOs RUNNING RUNNING RUNNING RUNNING
POWER MANAGEMENT TIMING
PCICLK_F
PCI_STOP#
PCICLK(0:5)
CPU_STOP#
CPUCLK(0:3)
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.
4/23/97 Page
SC674
Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs
Approved Product 2-WIRE CONTROL INTERFACE
2-wire control interface implements write only slave interface. IMISC674 cannot read back. Subaddressing supported, thus preceding bytes must sent order change control bytes. 2wire control interface allows each clock output individually enabled disabled. During normal data transfer, SDATA signal only changes when SDCLK signal low, stable when SDCLK high. There exceptions this. high transition SDATA while SDCLK high used indicate start data transfer cycle. high transition SDATA while SDCLK high indicates data transfer cycle. Data always sent complete 8-bit bytes, after which acknowledge generated. first byte transfer cycle 7-bit address with Read/Write LSB. Data transferred first. IMISC674 will respond writes bytes (max) data address generating acknowledge (low) signal SDATA wire following reception each byte. IMISC674 will respond other control interface conditions. Previously control registers retained.
SERIAL CONTROL REGISTERS
NOTE: Pin# column lists affected number where applicable. @Pup column gives state true power Bytes values shown only true power when PWR_DWN# activated. Following acknowledge Address Byte (D2), additional bytes must sent: "Command Code byte, "Byte Count" byte. Although data (bits) these bytes considered "don't care", they must sent will acknowledged.
Byte Function Select Register enable, Stopped)
@Pup
Pin#
Description
Reserved, Don't Reserved, Don't Reserved, Don't Reserved, Don't 48/24 48/24 Bit1 Bit0 Tri-State Reserved Test Mode Normal
IMPORTANT NOTE
Reserved bits intended possible future functions. important that they left their Power logic times. Otherwise data sheet specifications cannot guaranteed.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.
4/23/97 Page
SC674
Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs
Approved Product SERIAL CONTROL REGISTERS (Continued) Function Table Function Description Tri-State Test Mode Normal SEL=1 Normal SEL=0 Outputs Hi-Z Tclk/2 Hi-Z Tclk/4 CPU/2 CPU/2
SDRAM
Hi-Z Tclk/2
Hi-Z Tclk 14.318 14.318
IOAPIC Hi-Z Tclk 14.318 14.318
Notes: Tclk test clock over driven input during test mode.
Byte Clock Register enable, Stopped) @Pup Pin# Description Reserved Reserved Reserved CPUCLK5 enable/Stopped CPUCLK4 enable/Stopped CPUCLK3 enable/Stopped CPUCLK2 enable/Stopped CPUCLK1 enable/Stopped
Byte Clock Register enable, Stopped) @Pup Pin# Description Reserved PCICLK_F enable/Stopped PCICLK6 enable/Stopped PCICLK5 enable/Stopped PCICLK4 enable/Stopped PCICLK3 enable/Stopped PCICLK2 enable/Stopped PCICLK1 enable/Stopped
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.
4/23/97 Page
SC674
Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs
Approved Product SERIAL CONTROL REGISTERS(Continued) Byte SDRAM Clock Register enable, Stopped @Pup Pin# Description SDRAM8 enable/Stopped SDRAM7 enable/Stopped SDRAM6 enable/Stopped SDRAM5 enable/Stopped SDRAM4 enable/Stopped SDRAM3 enable/Stopped SDRAM2 enable/Stopped SDRAM1 enable/Stopped
Byte Additional SDRAM Clock Register enable, Stopped) @Pup Pin# Description SDRAM16 enable/Stopped SDRAM15 enable/Stopped SDRAM14 enable/Stopped SDRAM13 enable/Stopped SDRAM12 enable/Stopped SDRAM11 enable/Stopped SDRAM10 enable/Stopped SDRAM9 enable/Stopped
Byte Peripheral Control enable, Stopped) @Pup Pin# Description Reserved IOAPIC3 enable/Stopped IOAPIC2 enable/Stopped IOAPIC1 enable/Stopped Reserved Reserved Reserved enable/Stopped
Rev. 4/23/97 Page
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
SC674
Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs
Approved Product SERIAL CONTROL REGISTERS(Continued) Byte Reserved Register @Pup Pin# Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MAXIMUM RATINGS
This device contains circuitry protect inputs against damage high static voltages electric field; however, precautions should taken avoid application voltage higher than maximum rated voltages this circuit. proper operation, Vout should constrained range: VSS<(Vin Vout)<VDD Unused inputs must always tied appropriate logic voltage level (either VDD).
Voltage Relative VSS: Voltage Relative VDD: Storage Temperature: Ambient Temperature: Maximum Power Supply:
-0.3V 0.3V
ELECTRICAL CHARACTERISTICS
Characteristic Input Voltage Input High Voltage Input Current Input High Current Tri-State leakage Current Dynamic Supply Current Static Supply Current Short Circuit Current Symbol Isdd Units Conditions
66.6 MHz, 33.3 MODE output time seconds
VDDP =3.3V ±5%, VDDC 2.5V ±5%,, INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571 Rev. 4/23/97 Page
SC674
Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs
Approved Product SWITCHING CHARACTERISTICS
Characteristic Output Duty Cycle Offset Skew (CPU-CPU,SDRAMSDRAM,PCI-PCI) Skew (CPU-SDRAM) Symbol tOFF tSKEW1 tSKEW2 200* 300** 500* 600** +250 Units Conditions Measured 1.5V Load Measured 1.5V Load Measured 1.5V CPU, SDRAM load VDDC 3.3V VDDC 2.5V ±5%,
Period Adjacent Cycles Jitter Spectrum Bandwidth from Center
VDDP =3.3V ±5%, VDDC 2.5V ±5%,, note Ring Back must enter this range.
TYPE BUFFER CHARACTERISTICS CPUCLK(1:4)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Between Rise/Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax Units Conditions Vout Vout Vout Vout Load Load
VDDP =3.3V ±5%, VDDC 2.5V ±5%,,
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.
4/23/97 Page
SC674
Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs
Approved Product TYPE BUFFER CHARACTERISTICS IOAPIC(1:2)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Between Rise/Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax Units Conditions Vout Vout Vout Vout Load Load
VDDP =3.3V ±5%, VDDC 2.5V ±5%,,
TYPE BUFFER CHARACTERISTICS SDRAM(1:16)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Between Rise/Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax Units Conditions Vout 1.65 Vout 3.135 Vout 1.65 Vout Load Load
VDDP =3.3V ±5%, VDDC 2.5V ±5%,,
TYPE BUFFER CHARACTERISTICS PCICLK(1:6,
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Between Rise/Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax Units Conditions Vout Vout 3.135 Vout 1.95 Vout Load Load
VDDP =3.3V ±5%, VDDC 2.5V ±5%,,
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.
4/23/97 Page
SC674
Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs
Approved Product CRYSTAL REFERENCE OSCILLATOR PARAMETERS
Characteristic Frequency Tolerance Symbol VBIAS 12.00 14.31818 Vdd/2 16.00 +/-100 Units 0.7Vdd Ohms crystals rated load. note Conditions Calibration note Stability +60C) note Aging (first year 25C) note Parallel Resonant Capacitance Xout pins ground (each)
Mode Capacitance Bias Voltage Startup time Load Capacitance Effective Series resonant resistance Power Dissipation Shunt Capacitance
0.3Vdd
0.10
note
crystals internal package capacitance (total) maximum accuracy, total circuit loading capacitance should equal This loading capacitance effective capacitance across crystal pins includes device capacitance (CP) parallel with circuit traces, clock generator onboard discrete load capacitors. Budgeting Calculations Typical trace capacitance, half inch) Load crystal therefore Clock generator internal capacitance Load crystal therefore External crystal loading capacitors (connected ground) each) 15.0 total parasitic capacitance would therefore 20.0.0 Note recommended mandatory that crystal meets these specifications.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.
4/23/97 Page
SC674
Clock Generator Pentiumand PentiumII with 440LX Chipset DIMMs
Approved Product PACKAGE DRAWING DIMENSIONS SSOP OUTLINE DIMENSIONS
INCHES SYMBOL
MILLIMETERS 0.110 0.016 0.092 0.0135 0.010 .730 0.299 0.410 0.016 0.040 0.100 2.41 0.20 2.24 0.203 0.127 18.29 7.42 10.16 0.25 0.61 2.16 2.59 0.31 2.29 0.254 18.42 7.52 0.635 10.31 0.33 0.81 2.36 10.41 0.41 1.02 2.54 2.79 0.41 2.34 0.343 0.254 18.54 7.59
0.095 0.008 0.088 0.008 0.005 .720 0.292 0.400 0.10 0.024 0.085
0.102 0.012 0.090 0.010 .725 0.296 0.025 0.406 0.013 0.032 0.093
ORDERING INFORMATION
Part Number IMISC674BYB Note:
Marking:
Package Type SSOP
Production Flow Commercial,
ordering part number formed combination device number, device revision, package style, screening shown below.
Example: SC674BYB Date Code, Flow Commercial, Package SSOP Revision Device Number
IMISC674BYB
Purchase components International Microcircuits, Inc. sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.
4/23/97 Page
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