Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs Suppor
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SC673
Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs
Supports Pentium Pentium using 440LX chipset. clocks. SDRAM clocks DIMs. synchronous clocks. Optional common mixed supply mode: (VDD VDDP VDDC 3.3V) (VDD VDDP 3.3V, VDDC 2.5V) Supports Power Management 250ps skew SDRAM clocks. 250ps skew among clocks. 2-Wire serial interface Programmable registers featuring: enable/disable each output mode tri-state, test, normal IOAPIC clocks multiprocessor support. 48-pin SSOP package
FREQUENCY TABLE
60.0 66.6 30.0 33.3
CONNECTION DIAGRAM
XOUT VDDP PCICLK_F PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 VDDP PCICLK6 SDRAM12 SDRAM11 VDDP SDRAM10 SDRAM9 SDATA SDCLK VDDC IOAPIC1 IOAPIC2 CPUCLK1 CPUCLK2 VDDC CPUCLK3 CPUCLK4 SDRAM1 SDRAM2 VDDP SDRAM3 SDRAM4 SDRAM5 SDRAM6/ VDDP SDRAM7/ SDRAM8/ MODE
BLOCK DIAGRAM
XOUT IOAPIC (1:2)
SDATA SDCLK
Clock Gen.
VDDC
CPUCLK(1:4) PCICLK(1:6) PCICLK_F SDRAM(1:5,9:12) SDRAM(1:12)
PCI_STOP, CPU_STOP, PWR_DWN
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.9
6/12/97 Page
SC673
Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs
DESCRIPTION
Name
TYPE
OSC1
Description
On-chip reference oscillator input pin. Requires either external parallel resonant crystal (nominally 14.318 MHz) externally generated reference signal O-chip reference oscillator output pin. Drives external parallel resonant crystal when externally generated reference signal used, left unconnected Frequency select input pins. frequency select table page 1.This internal pull-up Buffered output on-chip reference oscillator. Clock outputs. frequency table specified. serial clock 2-wire control interface. internal pull-up resistor. serial data 2-wire control interface. internal pull-up resistor. clock outputs. frequency select table page clock output that does stop until power down mode. synchronous with other clocks. Buffered outputs 14.3MHZ multiprocessor support. They powered VDDP MODE=1, this Synchronous DRAM DIMs clock output powered VDDP. MODE=1, this Synchronous DRAM DIMs clock output powered VDDP. MODE=0, this input signal, where level stops clocks. internal pull-up. MODE=1, this Synchronous DRAM DIMs clock output powered VDDP. MODE=0, SEL=1 this input signal, where level stops clocks. internal pull-up. MODE=1, this Synchronous DRAM DIMs clock output powered VDDP. MODE=0, SEL=1 this input signal, where level stops SDRAM clocks will stay active) internal pull-up. This controls functionality pins enables Tristate mode. Frequency Table page functionality discription. internal pull-up. note Ground pins power supplies,
Xout
OSC1
CPU(1:4) SDCLK SDATA PCICLK(1:6) PCIF_F IOAPIC(1:2) SDRAM (1:5) (9:12) SDRAM6
VDDC VDDP VDDP VDDC VDDP
PADI4 PADI4 PADI4
VDDP VDDP VDDP
SDRAM5 SDRAM6
MODE
VDDC VDDP
Power supply pins fixed clocks core logic Power supply pins 2.5V/3.3V IOAPIC clock pins. Power supply pins 3.3V SDRAM clock clock pins.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.9
6/12/97 Page
SC673
Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs
POWER MANAGEMENT FUNCTIONS
clocks individually enabled stopped 2-wire control interface. clocks stopped state. clocks maintain valid high period transitions from running stopped transitions from stopped running when chip powered down. power VCOs will stabilize correct pulse widths within about CPU, clocks transition between running stopped waiting positive edge PCICLK_F followed negative edge clock interest, after which high levels output either enabled disabled. When MODE=0 SEL=1, pins inputs PCI_STOP# CPU_STOP# respectively (when MODE=1, these functions available). particular output enabled only when both serial interface these pins indicate that should enabled. device clocks disabled according following table order reduce power consumption. clocks stopped state. clocks maintain valid high period transitions from running stopped. high transitions PWR_DWN#, external circuitry should allow VCOs stabilize prior assuming clock periods correct. clocks transition between running stopped waiting positive edge PCICLK_F followed negative edge clock interest, after which high levels output either enabled disabled. CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK RUNNING RUNNING PCICLK RUNNING RUNNING OTHER CLKs RUNNING RUNNING RUNNING RUNNING XTAL VCOs RUNNING RUNNING RUNNING RUNNING
POWER MANAGEMENT TIMING
PCICLK_F
PCI_STOP#
PCICLK(0:5)
CPU_STOP#
CPUCLK(0:3)
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.9
6/12/97 Page
SC673
Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs
2-WIRE CONTROL INTERFACE
2-wire control interface implements write only slave interface. IMISC673 cannot read back. Subaddressing supported, thus preceding bytes must sent order change control bytes. 2wire control interface allows each clock output individually enabled disabled. During normal data transfer, SDATA signal only changes when SDCLK signal low, stable when SDCLK high. There exceptions this. high transition SDATA while SDCLK high used indicate start data transfer cycle. high transition SDATA while SDCLK high indicates data transfer cycle. Data always sent complete 8-bit bytes, after which acknowledge generated. first byte transfer cycle 7-bit address with Read/Write LSB. Data transferred first. IMISC673 will respond writes bytes (max) data address generating acknowledge (low) signal SDATA wire following reception each byte. IMISC673 will respond other control interface conditions. Previously control registers retained.
SERIAL CONTROL REGISTERS
NOTE: Pin# column lists affected number where applicable. @Pup column gives state true power Bytes values shown only true power when PWR_DWN# activated. Following acknowledge Address Byte (D2), additional bytes must sent: "Command Code byte, "Byte Count" byte. Although data (bits) these bytes considered "don't care", they must sent will acknowledged.
Byte Function Select Register enable, Stopped)
@Pup
Pin#
Description
Reserved, Don't Reserved, Don't Reserved, Don't Reserved, Don't 48/24 48/24 Bit1 Bit0 Tri-State Reserved Test Mode Normal
IMPORTANT NOTE
Reserved bits intended possible future functions. important that they left their Power logic times. Otherwise data sheet specifications cannot guaranteed.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.9
6/12/97 Page
SC673
Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs
SERIAL CONTROL REGISTERS (Cont.)
Function Table
Function Description Tri-State Test Mode Normal SEL=1 Normal SEL=0 Outputs SDRAM Hi-Z Tclk/2
Hi-Z Tclk/2
Hi-Z Tclk/4 CPU/2 CPU/2
Hi-Z Tclk 14.318 14.318
IOAPIC Hi-Z Tclk 14.318 14.318
Notes: Tclk test clock over driven input during test mode.
Byte Clock Register enable, Stopped)
@Pup Pin# Description Reserved Reserved Reserved Reserved CPUCLK4 enable/Stopped CPUCLK3 enable/Stopped CPUCLK2 enable/Stopped CPUCLK1 enable/Stopped
Byte Clock Register enable, Stopped)
@Pup Pin# Description Reserved PCICLK_F enable/Stopped PCICLK6 enable/Stopped PCICLK5 enable/Stopped PCICLK4 enable/Stopped PCICLK3 enable/Stopped PCICLK2 enable/Stopped PCICLK1 enable/Stopped
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.9
6/12/97 Page
SC673
Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs
SERIAL CONTROL REGISTERS(Cont.)
Byte SDRAM Clock Register enable, Stopped
@Pup Pin# Description SDRAM8 enable/Stopped SDRAM7 enable/Stopped SDRAM6 enable/Stopped SDRAM5 enable/Stopped SDRAM4 enable/Stopped SDRAM3 enable/Stopped SDRAM2 enable/Stopped SDRAM1 enable/Stopped
*This acts don't care when MODE (logic low) (input mode)
Byte Additional SDRAM Clock Register enable, Stopped)
@Pup Pin# Description Reserved Reserved Reserved Reserved SDRAM12 enable/Stopped SDRAM11 enable/Stopped SDRAM10 enable/Stopped SDRAM9 enable/Stopped
Byte Peripheral Control enable, Stopped)
@Pup Pin# Description Reserved Reserved IOAPIC2 enable/Stopped IOAPIC1 enable/Stopped Reserved Reserved Reserved enable/Stopped
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.9
6/12/97 Page
SC673
Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs
SERIAL CONTROL REGISTERS(Cont.)
Byte Reserved Register
@Pup Pin# Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
MAXIMUM RATINGS
This device contains circuitry protect inputs against damage high static voltages electric field; however, precautions should taken avoid application voltage higher than maximum rated voltages this circuit. proper operation, Vout should constrained range: VSS<(Vin Vout)<VDD Unused inputs must always tied appropriate logic voltage level (either VDD).
Voltage Relative VSS: Voltage Relative VDD: Storage Temperature: Ambient Temperature: Maximum Power Supply:
-0.3V 0.3V
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.9
6/12/97 Page
SC673
Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs
ELECTRICAL CHARACTERISTICS
Characteristic Input Voltage Input High Voltage Input Current Input High Current Tri-State leakage Current Dynamic Supply Current Symbol Units 66.6 MHz, 33.3 fully loaded Power down mode output time seconds Conditions
Static Supply Current Short Circuit Current
Isdd
VDDP =3.3V ±5%, VDDC 2.5V ±5%,
SWITCHING CHARACTERISTICS
Characteristic Output Duty Cycle Offset Symbol tOFF Units Conditions Measured 1.5V Load CPU, load PCI, Measured 1.25 Load CPU, load PCI, Measured 1.25 SDRAM CPU, SDRAM load VDDC 3.3V VDDC
Skew (CPU-CPU,SDRAMSDRAM,PCI-PCI) Skew (CPU-SDRAM)
tSKEW1
tSKEW2
200* 300**
500* 600** +250
Period Adjacent Cycles Jitter Spectrum Bandwidth from Center
VDDP =3.3V ±5%, VDDC 2.5V ±5%,
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.9
6/12/97 Page
SC673
Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs
TYPE BUFFER CHARACTERISTICS CPUCLK(1:4)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Between Rise/Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax Units Conditions Vout Vout Vout Vout Load Load
VDDP =3.3V ±5%, VDDC 2.5V ±5%,
TYPE BUFFER CHARACTERISTICS IOAPIC(1:2)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Between Rise/Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax Units Conditions Vout Vout Vout Vout Load Load
VDDP =3.3V ±5%, VDDC 2.5V ±5%,
TYPE BUFFER CHARACTERISTICS SDRAM(1:12)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Between Rise/Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax Units Conditions Vout 1.65 Vout 3.135 Vout 1.65 Vout Load Load
VDDP =3.3V ±5%, VDDC 2.5V ±5%,
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571 Rev.1.9 6/12/97 Page
SC673
Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs
TYPE BUFFER CHARACTERISTICS PCICLK(1:6,F)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Between Rise/Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax Units Conditions Vout Vout 3.135 Vout 1.95 Vout Load Load
VDDP =3.3V ±5%, VDDC 2.5V ±5%,
CRYSTAL REFERENCE OSCILLATOR PARAMETERS
Characteristic Frequency Tolerence Symbol VBIAS 12.00 14.31818 Vdd/2 16.00 +/-100 Units 0.7Vdd Ohms crystals rated load. note Conditions Calibration note Stability +60C) note Aging (first year 25C) note Parallell Resonant Capacitance Xout pins ground (each)
Mode Capacitance Bias Voltage Startup time Load Capacitance Effective Series resonant resistance Power Dissipation Shunt Capacitance
0.3Vdd
note crystals internal package capacitance (total) maximum accuracy,the total circuit loading capacitance should equal This loading capacitance effective capacitance across crystal pins includes device capacitance (CP) parallel with circuit traces, clock generator onboard discrete load capacitors. Budgeting Calculations Typical trace capacitance, half inch) Load crystal therefore Clock generator internal capacitance Load crystal therefore 15.0 External crystal loading capacitors (connect ground) total parasitic capacitance would therefore 20.0.0 Note recommended manditory that crystal meets these specifications. INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571 Rev.1.9 6/12/97 Page
0.10
SC673
Clock Generator Pentium® Pentium® with 440LX Chipset DIMMs
PACKAGE DRAWING DIMENSIONS
SSOP OUTLINE DIMENSIONS
SYMBOL
INCHES 0.008 0.085 0.008 0.006 0.291 0.395 0.025 0.012 0.090 0.010 0.008 0.625 0.295 0.025 0.408 0.030 0.420 0.040 0.110 0.016 0.095 0.013 0.010 0.637 0.299 0.20 2.16 0.20 0.15 7.39
MILLIMETERS 0.30 2.29 0.25 0.20 15.88 7.49 0.64 10.03 0.64 10.36 0.76 10.67 1.02 2.79 0.41 2.41 0.33 0.25 16.18 7.59
ORDERING INFORMATION
Part Number IMISC673DYB Note:
Marking:
Package Type SSOP
Production Flow Commercial,
ordering part number formed combination device number, device revision, package style, screening shown below.
Example: SC673DYB Date Code,
IMISC673DYB Flow Commercial, Package SSOP Revision Device Number
Purchase components International Microcircuits, Inc. sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.9
6/12/97 Page
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