System Clock Buffer Mobile Applications Approved Product Product

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System Clock Buffer Mobile Applications Approved Product Product

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SC660E
System Clock Buffer Mobile Applications
Approved Product Product Features
Product Description
device high fanout system clock distributor. primary application create large quantity clocks needed support wide range clock loads that referenced single existing clock. Loads supported. Primary application this component where long traces used transport clocks from their generating devices their loads. creation degradation waveform rise fall times greatly reduced running single reference clock trace this device then using regenerate clock that drives shorter traces using IMISC660 generate clocks target devices therefore minimized board real estate saved.
output buffers high clock fanout applications Each output internally disabled power consumption reduction. Separate power supply each group clock outputs mixed voltage application. 250ps skew between output clocks. 28-pin SSOP package minimum board space Single output Tristate testability
Block Diagram
VDDB
Configuration
SDRAM(0:1)
SDRAM(2:3)
SDRAM4 SDRAM5
SDATA SCLOCK
SDRAM(6:7) SDRAM(8:9)
VDDB SDRAM0 SDRAM1 VDDB SDRAM2 SDRAM3 VDDB SDRAM4 SDATA
VDDB SDRAM9 SDRAM8 VDDB SDRAM7 SDRAM6 VDDB SDRAM5 SCLOCK
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.2.5
2/17/2000 Page
SC660E
System Clock Buffer Mobile Applications
Approved Product Description
2,3,6,7,1 1,18,22,2 3,26,27 Name SDRAM(0:9) VDDB TYPE BUF1 Description This connected input reference clock. This clock must range 10.0 100.0 Mhz. skew output clocks
SDATA
SCLOCK
Buffer Output Enable pin. This used place output clocks (CLK1:10) state condition. This feature facilitates production board level testing easily implemented clocks that this device produces. internal pull-up resistor. Serial Data control interface. This receives data streams from outputs acknowledge valid data. Serial Clock control interface. Ground pins clock output buffers. These pins must returned same potential reduce output clock skew. Power output clock buffers.
VDDB
device core logic.
Maximum Ratings
This device contains circuitry protect inputs against damage high static voltages electric Voltage Relative VSS: Voltage Relative VDD: Storage Temperature: Operating Temperature: Maximum Power Supply: -0.3V 0.3V field; however, precautions should taken avoid application voltage higher than maximum rated voltages this circuit. proper operation, Vout should constrained range: VSS<(Vin Vout)<VDD Unused inputs must always tied appropriate logic voltage level (either VDD).
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.2.5
2/17/2000 Page
SC660E
System Clock Buffer Mobile Applications
Approved Product
2-Wire Control Interface
2-wire control interface implements write only slave interface. device cannot read back. Subaddressing supported, thus preceeding bytes must sent order change control bytes. 2wire control interface allows each clock output individually enabled disabled. During normal data transfer, SDATA signal only changes when SDCLK signal low, stable when SDCLK high. There exceptions this. high transition SDATA while SDCLK high used indicate start data transfer cycle. high transition SDATA while SDCLK high indicates data transfer cycle. Data always sent complete 8-bit bytes, after which acknowledge generated. first byte transfer cycle 7-bit address with Read/Write LSB. Data transferred first. device will respond writes bytes (max) data address generating acknowledge (low) signal SDATA wire following reception each byte. device will respond other control interface conditions. Previously control registers retained.
Serial Control Registers
NOTE: Pin# column lists affected number where applicable. @Pup column gives state true power Bytes values shown only true power when PWR_DWN# activated. Following acknowledge Address Byte (D2), additional bytes must sent: "Command Code byte, "Byte Count" byte. Although data (bits) these bytes considered "don't care", they must sent will acknowledged. After Command Code Count bytes have been acknowledged, below desrcibed sequence (Byte Byte Byte2, will valid acknowledged. Byte Function Select Register enable, Stopped)
@Pup
Pin#
Description reserved reserved reserved reserved SDRAM3 (Active Forced SDRAM2 (Active Forced SDRAM1 (Active Forced SDRAM0 (Active Forced
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.2.5
2/17/2000 Page
SC660E
System Clock Buffer Mobile Applications
Approved Product Serial Control Registers (Cont.)
Byte Clock Register enable, Stopped) @Pup Pin# Description SDRAM9 (Active Forced SDRAM8 (Active Forced SDRAM7 (Active Forced SDRAM6 (Active Forced reserved reserved reserved reserved
Byte Clock Register enable, Stopped
@Pup
Pin#
Description SDRAM5 (Active Forced SDRAM4 (Active Forced Used Used Used Used Used Used
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.2.5
2/17/2000 Page
SC660E
System Clock Buffer Mobile Applications
Approved Product
Electrical Characteristics
Characteristic Input Voltage Input High Voltage Input Current Input High Current Output Voltage 40mA Output High Voltage 30mA Tri-State leakage Current Dynamic Supply Current Idd100 Static Supply Current Short Circuit Current Input Rise Time Isdd Symbol Idd66 Units Input frequency outputs load Input frequency outputs load outputs disabled input clock output time seconds volts Outputs (see buffer spec) Outputs Using 3.3V Power (see buffer spec) Conditions
VDD1 thru VDD5 =3.3V ±5%,
Switching Characteristics
Characteristic Output Duty Cycle Buffer out/out Skew Buffer Outputs Buffer input output Skew Jitter Cycle Cycle* Jitter Absolute (Peak Peak)* Symbol tSKEW tSKEW TJCC TJabs Units loading loading Conditions Measured 1.5V (50/50 Load Measured 1.5V
VDD1 thru VDD5 3.3V ±5%, *This jitter additive input clock's jitter.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.2.5
2/17/2000 Page
SC660E
System Clock Buffer Mobile Applications
Approved Product
TB40_ Type Buffer Characteristics (All Clock Outputs)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Dynamic Output Impedance Rise/Fall Time Between Rise/Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax 1.33 1.33 Units Ohms Conditions Vout Vout 1.5V Vout Vout 1.2V Load Load
VDD1 thru VDD5 =3.3V ±5%,
Package Drawing Dimensions SSOP Outline Dimensions
SYMBOL
INCHES 0.068 0.002 0.066 0.010 0.005 0.397 0.205 0.073 0.005 0.068 0.012 0.006 0.402 0.209 0.0256 0.301` 0.022 0.307 0.030 0.311 0.037 7.65 0.55 0.078 0.008 0.070 0.015 0.009 0.407 0.212 1.73 0.05 1.68 0.25 0.13 10.07 5.20
MILLIMETERS 1.86 0.13 1.73 0.30 0.15 10.20 5.30 0.65 7.80 0.75 7.90 0.95 1.99 0.21 1.78 0.38 0.22 10.33 5.38
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.2.5
2/17/2000 Page
SC660E
System Clock Buffer Mobile Applications
Approved Product
Ordering Information
Part Number Package Type Production Flow IMISC660EYB SSOP Commercial, Note: ordering part number formed combination device number, device revision, package style, screening shown below. Marking: Example: SC660EYB Date Code,
IMISC660EYB Flow Commercial, Package SSOP Revision Device Number
Purchase components International Microcircuits, Inc. sublicensed Associated Companies conveys license under Phillips Patent Rights these components system, provided that system conforms Standard Specification defined Phillips.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.2.5
2/17/2000 Page

System Clock Buffer Mobile Applications Approved Product Product

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