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Clock Generator Pentium Based Designs DIMM Support Approved Produ


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SC652
Clock Generator Pentium Based Designs DIMM Support
Approved Product PRODUCT FEATURES
SEL1
FREQUENCY TABLE
SEL0 55.0 75.0 60.0 66.6 27.5 37.5 30.0 33.3
Supports Pentium® series, 6X86 CPUs. Supports Intel VIA, Opti chipset requirements. Supports Sychronous DRAM designs host (CPU/AGP) clocks SDRAM clocks. Optional common mixed supply mode (Vdd Vddq3 Vddq4 Vddq2 3.3V) (Vdd Vddq3 Vddq4 3.3V, Vddq2 2.5V)
CONNECTION DIAGRAM
skew buffers skew buffers Supports Single Power Management. SSOP package minimum board space
REF1 REF0 Xout Vddq4 PCICLK_F
REF2 Vddq2 IOAPIC PWR_DWN# CPUCLK0 CPUCLK1 Vddq2 CPUCLK2 CPUCLK3 SDRAM0 SDRAM1 Vddq3 SDRAM2 SDRAM3 SDRAM4 SDRAM5 Vddq3 SDRAM6 SDRAM7
BLOCK DIAGRAM
Buffers Xout Vddq2 IOAPIC Buffer Vddq2 PWR_DWN# Buffers Vddq3 Buffers Buffers PCICLK_F Buffer Vddq4 Buffer 48MHZ PLL2 Buffer 24MHZ SDRAM0~7 PCICLK0~5 CPUCLK0~3 REF0,1,2
PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 Vddq4 PCICLK5 SEL0 SEL1 Vddq4 48MHZ 24MHZ
SEL0,1
PLL1
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.2
4/24/97 Page
SC652
Clock Generator Pentium Based Designs DIMM Support
Approved Product DESCRIPTION
Xin, Xout These pins form on-chip reference oscillator when connected terminals external parallel resonant crystal (nominally 14.318 MHz). also serve input externally generated reference signal. 48MHz Frequency output USB. SEL(0:1) Standard frequency select inputs. They have internal pull-ups. CPUCLK(0:3) skew (<250 clock outputs host frequencies such CPU, Chipset, Cache. Vddq2 supply voltage these outputs. SDRAM(0:7) Synchronous DRAM DIMs clocks. They powered Vddq3. Power supply pins analog circuit core PCICLK(0:5) skew (<250pS) clock outputs frequencies. controlled Vddq3. PCICLK_F clock output that does stop until power down mode. synchronous with other clocks. connection pins. These buffers voltage level Vddq3 Power supply pins 3.3V pins. Vddq2 Power supply pins 2.5V/3.3V pins. logic. PWR_DWN# Power down turn power whole chip down including VCOs PCICLK_F output pin. internal pull-up Ground pins chip. 24MHz Frequency output super I/O. IOAPIC Buffered output 14.3MHZ multiprocessor support. powered Vddq2. REF(0:2) Buffered outputs reference 14.3MHZ.
POWER MANAGEMENT FUNCTIONS
IMISC652 clocks disabled using PWR_DWN# order reduce power consumption. clocks stopped state. clocks maintain valid high period transitions from running stopped. When powered down, reference oscillator VCOs stopped. high transitions PWR_DWN#, external circuitry should allow VCOs stabilize prior assuming pulse widths correct.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.2
4/24/97 Page
SC652
Clock Generator Pentium Based Designs DIMM Support
Approved Product MAXIMUM RATINGS
This device contains circuitry protect inputs against damage high static voltages electric Voltage Relative VSS: Voltage Relative VDD: Storage Temperature: Ambient Temperature: Maximum Power Supply: -0.3V 0.3V field; however, precautions should taken avoid application voltage higher than maximum rated voltages this circuit. proper operation, Vout should constrained range: VSS<(Vin Vout)<VDD Unused inputs must always tied appropriate logic voltage level (either VDD).
ELECTRICAL CHARACTERISTICS
Characteristic Input Voltage Input High Voltage Input Current Input High Current Output Current Output High Current Output Current Output High Current Tri-State leakage Current Dynamic Supply Current Static Supply Current Short Circuit Current Symbol IOL1 IOH1 IOL2 IOH2 Units 66.6 Mhz, Load PWR_DWN# output time seconds VOL1 1.6V CPU, SDRAM, PCI, IOAPIC REF0 clocks) VOH1 1.0V CPU, SDRAM, PCI, IOAPIC REF0 clocks) VOL2 1.9V 48Mhz, Mhz, REF2 REF1 clocks) VOH2 1.0V 48Mhz, Mhz, REF2 REF1 clocks) Conditions
VDDq2 VDDq3 3.3V+5%, Contact IBIS models.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.2
4/24/97 Page
SC652
Clock Generator Pentium Based Designs DIMM Support
Approved Product SWITCHING CHARACTERISTICS
Characteristic Output Rise (0.4V 2.0V) Fall (2.0V-0.4V) time Output Duty Cycle CPU/SDRAM Offset Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) Skew (CPU-SDRAM) Period Cycles, Jitter Absolute, Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion Symbol tTLH, tTHL tOFF tSKEW1 tSKEW2 tjab Vover VRBE +250 Units Conditions Load outputs Measured 1.5V Load Measured 1.5V Load Measured 1.5V Load Measured 1.5V ohms source inch load note1
VDDq2 VDDq3 3.3V+5%, note Ring Back must enter this range.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.2
4/24/97 Page
SC652
Clock Generator Pentium Based Designs DIMM Support
Approved Product LAYOUT RECOMMENDATION
Island plane plane
VCC1
IMISC652
10µF
VCC2
10µF
This only layout recommendation best performance lower EMI. designer choose differnent approach C10, C11and (all 0.1µf) should always used placed close their pins.
PACKAGE DRAWING DIMENSIONS
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571 Rev.1.2 4/24/97 Page
SC652
Clock Generator Pentium Based Designs DIMM Support
Approved Product SSOP OUTLINE DIMENSIONS
INCHES SYMBOL
MILLIMETERS 0.110 0.016 0.092 0.0135 0.010 0.630 0.299 0.410 0.016 0.040 0.100 2.41 0.20 2.24 0.203 0.127 15.75 7.42 10.16 0.25 0.61 2.16 2.59 0.31 2.29 0.254 15.88 7.52 0.635 10.31 0.33 0.81 2.36 10.41 0.41 1.02 2.54 2.79 0.41 2.34 0.343 0.254 16.00 7.59
0.095 0.008 0.088 0.008 0.005 0.620 0.292 0.400 0.10 0.024 0.085
0.102 0.012 0.090 0.010 0.625 0.296 0.025 0.406 0.013 0.032 0.093
ORDERING INFORMATION
Part Number IMISC652EYB Note: Package Type SSOP Production Flow Commercial,
ordering part number formed combination device number, device revision, package style, screening shown below. SC652EYB Date Code,
Marking: Example:
IMISC652EYB Flow Commercial, Package SSOP Revision Device Number
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.2
4/24/97 Page

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