NM27C128 131,072-Bit (16K High Performance CMOS EPROM NM27C128 hi
|
|
|
Top Searches for this datasheet
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
NM27C128 high performance 128K Erasable Electrically Programmable Read Only Memory. manufactured with Fairchild's latest CMOS split gate EPROM technology which enables operate speeds fast access time over full operating range. NM27C128 provides microprocessor-based systems extensive storage capacity large portions operating system application software. access time provides high speed operation with high-performance CPUs. NM27C128 offers single chip solution code storage requirements 100% firmware-based equipment. Frequently-used software routines quickly executed from EPROM storage, greatly enhancing system utility. NM27C128 configured standard EPROM pinout which provides easy upgrade path systems which currently using standard EPROMs. NM27C128 member high density EPROM Family which range densities
Features
High performance CMOS access time Fast turn-off microprocessor compatibility JEDEC standard configuration 28-pin PDIP package 32-pin chip carrier 28-pin CERDIP package Drop-in replacement 27C128 27128 faster programming time with Fairchild's turbo algorithm
Block Diagram
Data Outputs
Output Enable, Chip Enable Logic
Output Buffers
Gating
Decoder
Address Inputs 131,072-Bit Cell Matrix
Decoder
DS011329-1
1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
Connection Diagrams
27C080 27C040 27C020 27C010 27C512 27C256
NM27C128
27C256
27C512 27C010 27C020
27C040 27C080
OE/VPP CE/PGM
OE/VPP CE/PGM CE/PGM
DS011329-8
Note: Compatible EPROM configurations shown blocks adjacent NM27C128 pins.
Commercial Temp. Range (0°C +70°C) ±10%
Parameter/Order Number
NM27C128 NM27C128 NM27C128 NM27C128
Extended Temp. Range (-40°C +85°C) ±10%
Access Time (ns)
Parameter/Order Number
NM27C128 NM27C128 NM27C128
Access Time (ns)
Note: Surface mount PLCC package available commercial extended temperature ranges only.
Names
Symbol
A0-A13 O0-O7
Package Types: NM27C128
Description
Addresses Chip Enable Output Enable Outputs Program Connect
Quartz-Windowed Ceramic Plastic Surface-Mount PLCC packages conform JEDEC standard. versions guaranteed function slower speeds.
PLCC
DS011329-3
www.fairchildsemi.com
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
Absolute Maximum Ratings (Note
Storage Temperature Input Voltages except with Respect Ground with Respect Ground Supply Voltage with Respect Ground Protection -65°C +150°C
Output Voltages with Respect Ground
1.0V -0.6V
Operating Range
-0.6V -0.7V +14V -0.6V 2000V
Range
Comm'l Industrial
Temperature
+70°C -40°C +85°C
±10% ±10%
Read Operation Electrical Characteristics Over Operating Range with
Symbol
ISB1 ISB2 ICC1
Parameter
Input Level Input High Level Output Voltage Output High Voltage Standby Current (CMOS) Standby Current (T2L) Active Current, Inputs Supply Current Read Voltage Input Load Current Output Leakage Current
Test Conditions
-0.5
Units
-2.5 ±0.3V 0.3V, ±0.3V VIL, 5.5V VOUT 5.5V
Electrical Characteristics Over Operating Range with
Symbol
tACC (Note (Note (Note
Parameter
Address Output Delay Output Delay Output Delay High Output Float High Output Float Output Hold from Addresses, Whichever Occurred First
Units
www.fairchildsemi.com
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
Capacitance +25°C, (Note
Symbol
COUT
Parameter
Input Capacitance Output Capacitance
Conditions
VOUT
Units
Test Conditions
Output Load Gate (Note 0.45 2.4V Input Rise Fall Times Input Pulse Levels
Timing Measurement Reference Level (Note Inputs 0.8V 2.0V Outputs 0.8V 2.0V
Waveforms (Notes
ADDRESSES
0.8V
Addresses Valid
0.8V
(Note (Notes
0.8V
(Notes
Valid Output
OUTPUT
0.8V
Hi-Z
(Note
Hi-Z
DS011329-4
Note Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Note This parameter only sampled 100% tested. Note delayed tACC after falling edge without impacting tACC. Note compare level determined follows: High TRI-STATE®, measured VOH1 (DC) 0.10V; TRI-STATE, measured VOL1 (DC) 0.10V. Note TRI-STATE attained using Note power switching characteristics EPROMs require careful device decoupling. recommended that least ceramic capacitor used every device between GND. Note outputs must restricted 1.0V avoid latch-up device damage. Note Gate: -400 includes fixture capacitance. Note connected except during programming. Note Inputs outputs undershoot -2.0V Max.
www.fairchildsemi.com
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
Programming Characteristics (Notes
Symbol
tOES tCES tVPS tVCS tOUT Setup Time Setup Time Setup Time Setup Time Data Setup Time Address Hold Time Data Hold Time Output Enable Output Float Delay Program Pulse Width Data Valid from Supply Current during Programming Pulse Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise, Fall Time Input Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage 6.25 12.5 0.45 12.75
Parameter
Address Setup Time
Conditions
Units
6.75 13.0
Programming Waveforms (Note
Program ADDRESS
0.8V
Program Verify
Address
DATA
0.8V
Data Stable
Hi-Z
Data Valid
6.0V
13.0V
tVCS
0.8V
0.8V
0.8V
DS011329-5 Note Fairchild's standard product warranty applies devices programmed specifications described herein. Note must applied simultaneously before removed simultaneously after VPP. EPROM must inserted into removed from board with voltage applied VCC. Note maximum absolute allowable voltage which applied during programming 14V. Care must taken when switching supply prevent overshoot from exceeding this maximum specification. least capacitor required across VPP, suppress spurious voltage transients which damage device. Note During power must brought high VIH) either coincident with before power applied VPP.
www.fairchildsemi.com
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
6.5V 12.75V ADDRESS FIRST LOCATION
PROGRAM 50µs PULSE INCREMENT
DEVICE FAILED
FAIL
VERIFY BYTE
PASS
LAST ADDRESS
INCREMENT ADDRESS
ADDRESS FIRST LOCATION
VERIFY BYTE INCREMENT ADDRESS
PASS
FAIL
PROGRAM PULSE
LAST ADDRESS
CHECK BYTES 1ST: 6.0V 2ND: 4.3V
Note: standard National Semiconductor algorithm also used will have longer programming time. DS011329-6
FIGURE
www.fairchildsemi.com
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
Functional Description
DEVICE OPERATION
modes operation EPROM listed Table should noted that inputs modes levels. power supplies required VPP. power supply must 12.75V during three programming modes, must other three modes. power supply must 6.5V during three programming modes, other three modes.
Programming
CAUTION: Exceeding (VPP) will damage EPROM. Initially, after each erasure, bits EPROM "1's" state. Data introduced selectively programming "0's" into desired locations. Although only "0's" will programmed, both "1's" "0's" presented data word. only change ultraviolet light erasure. EPROM programming mode when power supply 12.75V, VIL, VIH. required that least capacitor placed across VPP, ground suppress spurious voltage transients which damage device. data programmed applied bits parallel data output pins. levels required address data inputs TTL. When address data stable, active low, program pulse applied input. program pulse must applied each address location programmed. EPROM programmed with Turbo Programming Algorithm shown Figure Each Address programmed with series pulses until verifies good, maximum pulses. Most memory cells will program with single pulse. (The standard National Semiconductor algorithm also used will have longer programming time.) EPROM must programmed with signal applied input. Programming multiple EPROM parallel with same data easily accomplished simplicity programming requirments. Like inputs parallel EPROM connected together when they programmed with same data. level pulse applied input programs paralleled EPROM.
Read Mode
EPROM control functions, both which must logically active order obtain data outputs. Chip Enable (CE) power control should used device selection. Output Enable (OE) output control should used gate data output pins, independent device selection. Assuming that addresses stable, address access time (tACC) equal delay from output (tCE). Data available outputs after falling edge assuming that been addresses have been stable least tACC -tOE.
Standby Mode
EPROM standby mode which reduces active power dissipation over 99%, from 0.55 EPROM placed standby mode applying CMOS high signal input. When standby mode, outputs high impedance state, independent input.
Output Disable
EPROM placed output disable applying high signal input. When output disable circuitry enabled, except outputs high impedance state (TRISTATE).
Output OR-Typing
Because EPROM usually used larger memory arrays, Fairchild provided 2-line control function that accommodates this multiple memory connections. 2-line control function allows for: lowest possible memory power dissipation, complete assurance that output contention will occur. most efficiently these control lines, recommended that decoded used primary device selecting function, while made common connection devices array connected READ line from system control bus. This assures that deselected memory devices their power standby modes that output pins active only when data desired from particular memory device.
Program Inhibit
Programming multiple EPROMs parallel with different data also easily accomplished. Except like inputs (including parallel EPROMs common. level program pulse applied EPROM's input with 12.75V will program that EPROM. high level input inhibits other EPROMs from being programmed.
www.fairchildsemi.com
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
Functional Description (Continued)
Program Verify
verify should performed programmed bits determine whether they were correctly programmed. verify performed with 12.75V. must VCC, except during programming program verify.
EPROM should placed within inch lamp tubes during erasure. Some lamps have filter their tubes which should removed before erasure. Table shows minimum EPROM erasure time various light intensities. erasure system should calibrated periodically. distance from lamp device should maintained inch. erasure time increases square distance from lamp distance doubled erasure time increases factor Lamps lose intensity they age. When lamp changed, distance changed, lamp aged, system should checked make certain full erasure occurring. Incomplete erasure will cause symptoms that misleading. Programmers, components, even system designs have been erroneously suspected when incomplete erasure problem.
AFTER PROGRAMMING
Opaque labels should placed over EPROM window prevent unintentional erasure. Covering window will also prevent temporary functional failure generation photo currents.
MANUFACTURER'S IDENTIFICATION CODE
EPROM manufacturer's identification code programming. When device inserted EPROM programmer socket, programmer reads code then automatically calls specific programming algorithm part. This automatic programming control only possible with programmers which have capability reading code. Manufacturer's Identification code, shown Table specifically identifies manufacture device type. code NM27C128 "8F83", where "8F" designates that made Fairchild Semiconductor, "83" designates 128K part. code accessed applying ±0.5V address Addresses A1-A8, A10-A13, control pins held VIL. Address held manufacturer's code, held device code. code read eight data pins, Proper code access only guaranteed 25°C ±5°C.
SYSTEM CONSIDERATION
power switching characteristics EPROMs require careful decoupling devices. supply current, ICC, three segments that interest system designer: standby current level, active current level, transient current peaks that produced voltage transitions input pins. magnitude these transient current peaks dependent output capacitance loading device. associated transient voltage peaks suppressed properly selected decoupling capacitors. recommended that least ceramic capacitor used every device between GND. This should high frequency capacitor inherent inductance. addition, least bulk electrolytic capacitor should used between each eight devices. bulk capacitor should located near where power supply connected array. purpose bulk capacitor overcome voltage drop caused inductive effects board traces.
ERASURE CHARACTERISTICS
erasure characteristics device such that erasure begins occur when exposed light with wavelengths shorter than approximately 4000 Angstroms should noted that sunlight certain types fluorescent lamps have wavelengths range. recommended erasure procedure EPROM exposure short wave ultraviolet light which wavelength integrated dose (i.e., intensity exposure time) erasure should minimum 15W-sec/cm2
www.fairchildsemi.com
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
Mode Selection
modes operation NM27C128 listed Table single power supply required read mode. inputs levels except device signature.
TABLE Modes Selection Pins Mode
Read Output Disable Standby Programming Program Verify Program Inhibit
Note VIH.
12.75V 12.75V 12.75V
5.0V 5.0V 5.0V 6.5V 6.5V 6.5V
Outputs
DOUT High-Z High-Z DOUT High-Z
TABLE Manufacturer's Identification Code Pins
Manufacturer Code Device Code
(10)
(24)
(19)
(18)
(17)
(16)
(15)
(13)
(12)
(11)
Data
www.fairchildsemi.com
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.465 (37.08)
0.025 (0.64)
0.515 0.530 (13.08 13.46)
0.030-0.055 (0.76 1.40)
0.280 ±0.010 (7.11 ±0.25) WINDOW
0.225 (5.72)
0.050-0.060 (1.27 1.52)
Glass Sealant
0.180 (4.57)
0.10 (2.54)
0.590-0.620 (14.99 (15.75)
0.125 (3.18)
0.090-0.110 0.015-0.021 (2.29 2.79) 0.060-0.100 (0.38 0.53) 0.035 0.045 (1.52 2.54) (0.76 1.14)
86°-94°
0.015 -0.060 (0.38 1.52)
100°
0.008-0.012 (0.20 0.25)TYP +0.025 (0.64) -0.060 (-1.523)
0.685 (17.40)
Window Cavity Dual-In-Line CerDIP Package (JQ) Order Number NM27C128QXXX Package Number J28CQ
0.062 (1.575)
0.490 0.550 (12.446 13.97)
IDENT
1.360 1.470 (34.544 37.34)
0.030 (0.762)
0.583 0.640 (14.81 16.26)
0.145 0.210 (3.683 5.334)
0.050 (1.270) 0.125 0.165 (3.175-4.191) 0.015 (0.381)
90°-105° 0.580 (14.73) 0.008 0.015 (0.203 0.381) 0.065 ±0.025 (1.65 ±0.635) 0.100 ±0.010 (2.54 ±-0.254) 0.018 ±0.003 (0.457 ±0.076) 0.120 0.150 (3.048 3.81)
0.035 0.070 (0.889 1.778)
28-Lead Plastic One-Time-Programmable Dual-In-Line Package Order Number NM27C128NXXX Package Number N28B
www.fairchildsemi.com
NM27C128 131,072-Bit (16K High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.485-0.495 [12.32-12.57] 0.007[0.18] 0.449-0.453 [11.40-11.51] -A0.045 [1.143] 0.000-0.010 [0.00-0.25] Polished Optional 0.549-0.553 [13.94-14.05] -B0.585-0.595 [14.86-15.11] 0.013-0.021 [0.33-0.53] detail -J13 0.002[0.05] 0.007[0.18] 0.007[0.18] -E20 0.007[0.18] 0.078-0.095 [1.98-2.41] -C0.004[0.10] 0.020 [0.51] 0.005 [0.13] 0.0100 [0.254] D-E, 0.106-0.112 [2.69-2.84] 0.023-0.029 [0.58-0.74] -HBase Plane
0.015 [0.38]
0.007[0.18] 0.002[0.05] 0.541-0.545 [13.74-13-84]
[10.16]
0.400
0.490-0530 [12.45-13.46] 0.015[0.38] D-E,
0.118-0.129 [3.00-3.28] 0.010[0.25] D-E, 0.042-0.048 45°X [1.07-1.22]
0.026-0.032 [0.66-0.81] 0.007[0.18] D-E,
0.025 [0.64] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64]
0.050
0.123-0.140 [3.12-3.56]
0.045 [1.14] 0.025 [0.64] 0.021-0.027 [0.53-0.69]
Detail Typical Rotated
0.030-0.040 [0.76-1.02]
0.065-0.071 [1.65-1.80]
0.053-0.059 [1.65-1.80] 0.031-0.037 [0.79-0.94] 0.027-0.033 [0.69-0.84]
Section Typical
32-Lead Plastic Leaded Chip Carrier (PLCC) Order Number NM27C128VXXX Package Number VA32A
Life Support Policy
Fairchild's products authorized critical components life support devices systems without express written approval President Fairchild Semiconductor Corporation. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: 1793-856858 Deutsch Tel: 8141-6102-0 English Tel: 1793-856856 Tel: 1-6930-3696 Italiano Tel: 2-249111-1
critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications.
www.fairchildsemi.com
Other recent searches
PHP9NQ20T - PHP9NQ20T PHP9NQ20T Datasheet
PHB9NQ20T - PHB9NQ20T PHB9NQ20T Datasheet
PHD9NQ20T - PHD9NQ20T PHD9NQ20T Datasheet
M48T02 - M48T02 M48T02 Datasheet
M48T12 - M48T12 M48T12 Datasheet
LUG25C - LUG25C LUG25C Datasheet
LE260 - LE260 LE260 Datasheet
ICS83021I - ICS83021I ICS83021I Datasheet
2SA1566 - 2SA1566 2SA1566 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
