NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM NM27C040
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NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
NM27C040 high performance, 4,194,304-bit Electrically Programmable Erasable Read Only Memory. organized 512K words bits each. pin-compatibility with byte-wide JEDEC EPROMs enables upgrades through Mbit EPROMs. "Don't Care" feature during read operations allows memory expansions from Mbits with printed circuit board changes. NM27C040 provides microprocessor-based systems extensive storage capacity large portions operating system application software. 120ns access time provides high speed operation with high-performance CPUs. NM27C040 offers single chip solution code storage requirements 100% firmware-based equipment. Frequently used software routines quickly executed from EPROM storage, greatly enhancing system utility. NM27C040 manufactured using Fairchild's advanced CMOS AMGEPROM technology.
Features
High performance CMOS 120, 150ns access time* Simplified upgrade path -VPP "Don't Care" during normal read operation Manufacturer's identification code JEDEC standard configuration 32-pin PDIP 32-pin PLCC 32-pin CERDIP
*Note: revision meets 70ns. Please check with factory availability.
Block Diagram
CE/PGM Output Enable, Chip Enable, Program Logic Data Outputs
Output Buffers
Decoder
Gating
Address Inputs
4,194,304-Bit Cell Matrix
Decoder
DS010836-1
AMGis trademark WSI, Inc.
1999 Fairchild Semiconductor Corporation NM27C040 Rev.
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NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
Connection Diagrams
27C080 27C020 27C010
NM27C040
XX/VPP
27C010
27C020
27C080
Note:
XX/VPP
XX/VPP
CE/PGM
XX/PGM XX/PGM OE/VPP CE/PGM
DS010836-2
Compatible EPROM configurations shown blocks adjacent NM27C040 pin.
Commercial Temperature Range (0°C +70°C) ±10%
Parameter/Order Number
NM27C040 NM27C040
Extended Temperature Range (-40°C +85°C) ±10%
Parameter/Order Number
NM27C040 Package Types: NM27C040 Quartz-Windowed Ceramic Plastic
Access Time (ns)
Access Time (ns)
Names
A0-A18 CE/PGM O0-O7 Addresses Chip Enable/Program Output Enable Outputs Don't Care (During Read)
PLCC packages conform JEDEC standard. versions guaranteed function slower speeds.
NM27C040 Rev.
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NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
Absolute Maximum Ratings (Note
Storage Temperature Input Voltages except with Respect Ground with Respect Ground Supply Voltage with Respect Ground Protection -65°C +150°C
Output Voltages with Respect Ground
+1.0V 0.6V
Operating Range
-0.6V -0.6V +14V -0.6V >2000V
Range
Commercial Industrial
Temperature
+70°C -40°C +85°C
Tolerance
±10% ±10%
Read Operation Electrical Characteristics Over operating range with
Symbol
ISB1 ISB2
Parameter
Input Level Input High Level Output Voltage Output High Voltage Standby Current (CMOS) Standby Current Active Current Supply Current Read Voltage Input Load Current Output Leakage Current
Test Conditions
-0.5
Units
-2.5 0.3V VIL, 5.5V VOUT 5.5V
Electrical Characteristics Over operating range with
Symbol
tACC (Note (Note
Parameter
Address Output Delay Output Delay Output Delay Output Disable Output Float Output Hold from Addresses Whichever Occurred First
Units
Capacitance +25°C, (Note
Symbol
COUT
Parameter
Input Capacitance Output Capacitance
Conditions
VOUT
Units
NM27C040 Rev.
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NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
Test Conditions
Output Load Gate (Note 0.45V 2.4V Input Rise Fall Times Input Pulse Levels
Timing Measurement Reference Level (Note Inputs 0.8V Outputs` 0.8V
Waveforms (Notes
ADDRESSES 0.8V Addresses Valid
0.8V
(Note
0.8V (Note
(Note Valid Output Hi-Z
DS010836-4
OUTPUT
0.8V
Hi-Z (Note
Note Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Note This parameter only sampled 100% tested. Note delayed tACC after falling edge without impacting tACC. Note compare level determined follows: High TRI-STATE®, measured VOH1 (DC) 0.10V; TRI-STATE, measured VOL1 (DC) 0.10V. Note TRI-STATE attained using Note power switching characteristics EPROMs require careful device decoupling. recommended that least ceramic capacitor used every device between GND. Note outputs must restricted 1.0V avoid latch-up device damage. Note Gate: -400 includes fixture capacitance. Note connected except during programming. Note Inputs outputs undershoot -2.0V Max.
NM27C040 Rev.
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NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
Programming Waveform (Note
Program ADDRESSES
0.8V
Program Verify
Address
DATA
0.8V
Data Stable
Hi-Z
Data Valid
6.25V
12.75V
0.8V
CE/PGM
0.8V
DS010836-5
Programming Characteristics (Notes
Symbol
tOES tVPS tVCS tOUT
Parameter
Address Setup Time Setup Time Data Setup Time Setup Time Setup Time Address Hold Time Data Hold Time Output Enable Output Float Delay Program Pulse Width Data Valid from Supply Current during Programming Pulse Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise, Fall Time Input Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage
Conditions
Units
CE/PGM
CE/PGM CE/PGM
6.25 12.5 -0.1
12.75
6.75 13.0
0.45
Note Fairchild's standard product warranty applies only devices programmed specifications described herein. Note must applied simultaneously before removed simultaneously after VPP. EPROM must inserted into removed from board with voltage applied VCC. Note maximum absolute allowable voltage which applied during programming 14V. Care must taken when switching supply prevent overshoot from exceeding this maximum specification. least capacitor required across VPP, suppress spurious voltage transients which damage device. Note During power CE/PGM must brought high (VIH) either coincident with before power applied VPP.
NM27C040 Rev.
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NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
6.5V 12.75V ADDRESS FIRST LOCATION
PROGRAM 50µs PULSE INCREMENT
DEVICE FAILED
FAIL
VERIFY BYTE
PASS
LAST ADDRESS
INCREMENT ADDRESS
ADDRESS FIRST LOCATION
VERIFY BYTE INCREMENT ADDRESS
PASS
FAIL
PROGRAM PULSE
LAST ADDRESS
CHECK BYTES 1ST: 6.0V 2ND: 4.3V
DS010836-6 Note: standard National Semiconductor algorithm also used with will have longer programming time.
FIGURE
NM27C040 Rev.
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NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
Functional Description
DEVICE OPERATION
modes operation EPROM listed Table should noted that inputs modes levels. power supplies required VPP. power supply must 12.75V during three programming modes, must other three modes. power supply must 6.25V during three programming modes, other three modes.
supply 12.75V VIH. required that least capacitor placed across VPP, ground suppress spurious voltage transients which damage device. data programmed applied bits parallel data output pins. levels required address data inputs TTL. When address data stable, active low, program pulse applied CE/PGM input. program pulse must applied each address location programmed. EPROM programmed with Turbo Programming Algorithm shown Figure Each Address programmed with series pulses until verifies good, maximum pulses. Most memory cells will program with single pulse. (The standard National Semiconductor Algorithm also used will have longer programming time.) EPROM must programmed with signal applied CE/PGM input. Programming multiple EPROM parallel with same data easily accomplished simplicity pro-gramming requirements. Like inputs parallel EPROM connected together when they programmed with same data. level pulse applied CE/PGM input programs paralleled EPROM.
Read Mode
EPROM control functions, both which must logically active order obtain data outputs. Chip Enable (CE/PGM) power control should used device selection. Output Enable (OE) output control should used gate data output pins, independent device selection. Assuming that addresses stable, address access time (tACC) equal delay from output (tCE). Data available outputs after falling edge assuming that CE/PGM been addresses have been stable least tACC -tOE.
Standby Mode
EPROM standby mode which reduces active power dissipation over 99%, from 0.55 EPROM placed standby mode applying CMOS high signal CE/PGM input. When standby mode, outputs high impedance state, independent input.
Program Inhibit
Programming multiple EPROMs parallel with different data also easily accomplished. Except CE/PGM like in-puts (including parallel EPROMs com-mon. level program pulse applied EPROM's CE/PGM input with 12.75V will program that EPROM. high level input inhibits other EPROMs from being programmed.
Output Disable
EPROM placed output disable applying high signal input. When output disable circuitry enabled, except outputs high impedance state (TRISTATE).
Program Verify
verify should performed programmed bits determine whether they were correctly programmed. verify performed with 12.75V. must VCC, except during programming program verify.
Output OR-Typing
Because EPROM usually used larger memory arrays, Fairchild provided 2-line control function that accommodates this multiple memory connections. 2-line control function allows for: lowest possible memory power dissipation, complete assurance that output contention will occur. most efficiently these control lines, recommended that CE/PGM decoded used primary device selecting function, while made common connection devices array connected READ line from system control bus. This assures that deselected memory devices their power standby modes that output pins active only when data desired from particular memory device.
AFTER PROGRAMMING
Opaque labels should placed over EPROM window prevent unintentional erasure. Covering window will also prevent temporary functional failure generation photo currents.
MANUFACTURER'S IDENTIFICATION CODE
EPROM manufacturer's identification code programming. When device inserted EPROM programmer socket, programmer reads code then automatically calls specific programming algorithm part. This automatic programming control only possible with programmers which have capability reading code. Manufacturer's Identification code, shown Table specifically identifies manufacturer device type. code NM27C040 "8F08", where "8F" designates that made Fairchild Semiconductor, "08" designates Megabit (512K part. code accessed applying ±0.5V address Addresses A1-A8, A10-A18, control pins held VIL. Address held manufacturer's code, held device code. code read eight data pins, Proper code access only guaranteed 25°C 5°C.
Programming
CAUTION: Exceeding (VPP) will damage EPROM. Initially, after each erasure, bits EPROM "1's" state. Data introduced selectively programming "0's" into desired locations. Although only "0's" will programmed, both "1's" "0's" presented data word. only change ultraviolet light erasure. EPROM programming mode when power
NM27C040 Rev.
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NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
Functional Description (Continued)
ERASURE CHARACTERISTICS
erasure characteristics device such that erasure begins occur when exposed light with wavelengths shorter than approximately 4000 Angstroms should noted that sunlight certain types fluorescent lamps have wavelengths range. recommended erasure procedure EPROM exposure short wave ultraviolet light which wavelength integrated dose (i.e., intensity exposure time) erasure should minimum 15W-sec/cm2. EPROM should placed within inch lamp tubes during erasure. Some lamps have filter their tubes which should removed before erasure. erasure system should calibrated periodically. distance from lamp device should maintained inch. erasure time increase square distance from lamp. distance doubled erasure time increases factor Lamps lose intensity they age. When lamp changed, distance changed, lamp aged, system should
checked make certain full erasure occurring. Incomplete erasure will cause symptoms that misleading. Programmers, components, even system designs have been erroneously suspected when incomplete erasure problem.
SYSTEM CONSIDERATION
power switching characteristics EPROMs require careful decoupling devices. supply current, ICC, three segments that interest system designer: standby current level, active current level, transient current peaks that produced voltage transitions input pins. magnitude these transient current peaks dependent output capacitance loading device. associated transient voltage peaks suppressed properly selected decoupling capacitors. recommended that least ceramic capacitor used every device between GND. This should high frequency capacitor inherent inductance. addition, least bulk electrolytic capacitor should used between each eight devices. bulk capacitor should located near where power supply connected array. purpose bulk capacitor overcome voltage drop caused inductive effects board traces.
Mode Selection
modes operation NM27C040 listed Table single power supply required read mode. inputs levels except device signature.
TABLE Modes Selection Pins Mode
Read Output Disable Standby Programming Program Verify Program Inhibit
Note
CE/PGM
(Note 12.75V 12.75V 12.75V
5.0V 5.0V 5.0V 6.25V 6.25V 6.25V
Outputs
DOUT High High DOUT High
TABLE Manufacturer's Identification Code Pins
Manufacturer Code Device Code
(12)
(26)
(21)
(20)
(19)
(18)
(17)
(15)
(14)
(13)
Data
NM27C040 Rev.
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NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.660
0.025
0.585
0.030-0.055
WINDOW SIZE CONFIGURATION DETERMINED DEVICE SIZE
0.005 0.225 0.125
0.050-0.060 Glass Sealant
0.175
0.10
0.590-0.620
0.015 -0.060 86°-94° 0.150
100°
0.008-0.012 +0.025 -0.060
0.060-0.100
0.090-0.110
0.015-0.021
0.685
32-Lead EPROM Ceramic Dual-In-Line Package Order Number NM27C040QXXX Package Number J32AQ
NM27C040 Rev.
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NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.485-0.495 [12.32-12.57]
0.007[0.18]
0.449-0.453 [11.40-11.51] -A0.045 [1.143] 0.000-0.010 [0.00-0.25] Polished Optional
0.106-0.112 [2.69-2.84] 0.023-0.029 [0.58-0.74]
Base Plane
0.015 [0.38]
0.007[0.18] 0.002[0.05] 0.541-0.545 [13.74-13-84]
[10.16]
0.400
0.490-0530 [12.45-13.46] 0.015[0.38] D-E,
0.549-0.553 [13.94-14.05] -B0.585-0.595 [14.86-15.11]
-FSee detail -J13
0.002[0.05] 0.007[0.18]
0.013-0.021 [0.33-0.53] 0.007[0.18] 0.078-0.095 [1.98-2.41] -C0.004[0.10] 0.020 [0.51] 0.005 [0.13] 0.0100 [0.254] D-E,
0.007[0.18]
0.118-0.129 [3.00-3.28] 0.010[0.25] D-E, 0.042-0.048 45°X [1.07-1.22]
0.026-0.032 [0.66-0.81]
0.007[0.18] D-E,
0.025 [0.64] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64]
0.050
0.123-0.140 [3.12-3.56]
0.045 [1.14] 0.025 [0.64] 0.021-0.027 [0.53-0.69]
Detail Typical Rotated
0.030-0.040 [0.76-1.02]
0.065-0.071 [1.65-1.80]
0.053-0.059 [1.65-1.80] 0.031-0.037 [0.79-0.94] 0.027-0.033 [0.69-0.84]
Section Typical
32-Lead PLCC Package Order Number NM27C040VXXX Package Number VA32A
NM27C040 Rev.
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NM27C040 4,194,304-Bit (512K High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.64 1.66 (41.66 42.164)
0.062 (1.575)
0.490 0.550 (12.446 13.97)
IDENT
0.580 (14.73) 0.600 0.620 (15.240 15.748)
0.050 (1.270)
0.125 0.165 (3.175 4.191)
0.145 0.210 (3.683 5.334)
90°-105° 0.008 0.015 (0.203 0.381) 0.040 0.090 (1.016 2.286)
86°- 0.018 ±0.003 (0.457 ±0.078)
0.015 (0.381) 0.120 0.150 (3.048 3.81)
0.100 ±0.010 (2.540 ±0.254) 0.035 0.07 (0.889 1.778)
32-Lead PDIP Package Order Number NM27C040NXXX
Life Support Policy
Fairchild's products authorized critical components life support devices systems without express written approval President Fairchild Semiconductor Corporation. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: 1793-856858 Deutsch Tel: 8141-6102-0 English Tel: 1793-856856 Tel: 1-6930-3696 Italiano Tel: 2-249111-1
critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications.
NM27C040 Rev.
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