Offering core frequencies MHz, MHz, MHz, MHz, 256K on-die level cache
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Pentium® Processor With On-die Cache Mobile Module Connector (MMC-2)
Offering core frequencies MHz, MHz, MHz, MHz, 256K on-die level cache 66-MHz processor system speed Processor core voltage regulation supports input voltages from Above percent peak efficiency Integrated Active Thermal Feedback (ATF) system ACPI Specification Rev. compliant Internal digital signaling (SMBus) across module interface Programmable trip point interrupt poll mode temperature reading Supports single 66-MHz, 3.3V device Thermal transfer plate Intel® 82433BX heat dissipation Intel® 82433BX Host Bridge system controller DRAM controller supports SDRAM 3.3V Supports CLKRUN# protocol SDRAM clock support self-refresh SDRAM during Suspend mode 3.3V only control, compliant
Information this document provided solely enable Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Information contained herein supersedes previously published specifications these devices from Intel. INTEL CORPORATION 1999,2000 February 2000 Order Number: 245110-03
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel' Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life-saving, life-sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked reserved" undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium processor with on-die cache mobile module contain design defects errors known errata. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800548-4725 visiting Intel' site http://www.intel.com Copyright Intel Corporation1999, 2000. *Third-party brands names property their respective owners.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
CONTENTS
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.1.9 3.1.10 INTRODUCTION Revision History ARCHITECTURE OVERVIEW.5 CONNECTOR INTERFACE Signal Definitions Signal List.8 Memory (109 Signals).9 Signals) Signals).11 Geyserville Signals).12 Processor/PIIX4E/M Sideband Signals)13 Power Management Signals).14 Clock Signals).15 Voltages Signals).16 ITP/JTAG Signals).17 4.7.1 4.7.2 4.4.8 4.6.1 4.6.2 Deep Sleep State Typical POS/STR Power. Electrical Requirements Requirements. 4.6.2.1 Requirements. Clock Signal Quality Specifications Measurement Guidelines Voltage Regulator Voltage Regulator Efficiency.
Control Voltage Regulator Voltage Signal Definition Sequencing 4.7.3 Power Planes: Bulk Capacitance Requirements 4.7.2.1 Surge Current Guidelines Slew-rate Control: Circuit Description. Undervoltage Lockout: Circuit Description (V_uv_lockout) 4.7.4.3 Overvoltage Lockout: Circuit Description (V_ov_lockout). 4.7.4.4 Overcurrent Protection: Circuit Description Active Thermal Feedback Thermal Sensor Configuration Register MECHANICAL SPECIFICATION. Module Dimensions. 5.1.2 Location MMC-2 Connector 4.7.4.1 4.7.4.2 5.1.3 5.1.4 5.3.1 5.3.2 Printed Circuit Board Thickness Height Restrictions Thermal Transfer Plate. Module Physical Support Module Mounting Requirements. Module Weight THERMAL SPECIFICATION Thermal Design Power. Thermal Sensor Setpoint LABELING INFORMATION ENVIRONMENTAL STANDARDS. 4.7.4
3.1.11 Miscellaneous Signals).17 Connector Assignments Assignments.21 FUNCTIONAL DESCRIPTION Pentium Processor With On-Die Cache Mobile Module MMC-2.22 Cache 82433BX Host Bridge System Controller.22 4.3.1 Memory Organization 4.3.2 4.3.3 4.3.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 Reset Strap Options Interface Interface.23 Power Management.23 Clock Control Architecture.23 Normal State Auto Halt State.25 Stop Grant State Quick Start State.25 HALT/Grant Snoop State.25 Sleep State.25
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
FIGURES
Figure Block Diagram Pentium Processor With On-die Cache Mobile Module MMC-2 Figure 400-Pin Connector Footprint Numbers.21 Figure Clock Control States Figure BCLK, TCK, PICCLK Generic Clock Waveform Processor Core Pins.29 Figure Power-on Sequence Timing Figure Instantaneous In-rush Current Model.34 Figure Instantaneous In-rush Current.35 Figure Overcurrent Protection Circuit Figure Spice Simulation Using In-rush Protection (Example ONLY)).37 Figure Board Dimensions with 400-Pin Connector Orientation Figure Board Dimensions with 400-Pin ConnectorPin Orientation.41 Figure Printed Circuit Board Thickness Figure Keep-out Zone Figure Thermal Transfer Plate Figure Thermal Transfer Plate Figure Standoff Holes, Board Edge Clearance, Containment Ring Figure Product Tracking Information
TABLES
Table Connector Signal Summary Table Memory Signal Descriptions Table Signal Descriptions. Table Signal Descriptions. Table Geyserville Descriptions. Table Processor/PIIX4E/M Sideband Signal Descriptions. Table Power Management Signal Descriptions. Table Clock Signal Descriptions Table Voltage Descriptions Table ITP/JTAG Pins. Table Miscellaneous Pins. Table Connector Assignments. Table Connector Specifications Table Configuration Straps 82433BX Host Bridge System Controller. Table Clock State Characteristics. Table POS/STR Power. Table Power Supply Design Specifications Table Specifications Processor Core Pins Table BCLK Signal Quality Specifications Processor Core. Table Typical Voltage Regulator Efficiency Table Voltage Signal Definitions Sequences Table VR_ON In-rush Current. Table Capacitance Requirement Power Plane Table Thermal Sensor SMBus Address Table Table Thermal Sensor Configuration Register Table Thermal Design Power Specification. Table Environmental Standards.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
INTRODUCTION modes power management. E_SMRAM mode supports write-back cacheable SMRAM megabyte. thermal transfer plate (TTP) 82433BX Host Bridge provides heat dissipation thermal attach point system manufacturer' thermal solution. on-board voltage regulator converts system voltage processor' core voltage. Isolating processor voltage requirements allows system manufacturer incorporate different processor variants into single notebook system. Supporting input voltages from volts volts, processor core voltage regulation enables above percent peak efficiency decouples processor voltage requirements from system. Pentium processor with on-die cache mobile module MMC-2 also incorporates Active Thermal Feedback (ATF) sensing, compliant ACPI Specification 1.0. system management (SMBus) supports internal external temperature sensing with programmable trip points.
This document provides technical information integrating Pentium processor with on-die cache mobile module Connector (MMC-2) into latest notebook systems today' notebook market. Building around this design gives system manufacturer these advantages: Avoids complexities associated with designing highspeed processor core logic boards. Provides upgrade path from previous Intel® Mobile Modules using standard interface. Revision History Revision Updates Initial release Updates include: Addition 400-MHz processor speed POS/STR measurement corrections specification clarification VR_ON VR_PWRGD specification correction cache specification correction Power sequence clarification Revised Table
Date 1999 1999
2000
ARCHITECTURE OVERVIEW
highly integrated assembly, Pentium processor with on-die cache mobile module MMC-2 contains mobile Pentium processor with on-die cache core immediate system-level support. Pentium processor with on-die cache mobile module MMC-2 offers core speeds megahertz, megahertz, megahertz, megahertz, megahertz. processor speeds have 66-megahertz processor system speed (PSB). PIIX4E/M PCI/ISA Bridge large-scale integrated devices Intel 440BX AGPset. notebook' system electronics must include PIIX4E/M device connect Pentium processor with on-die cache mobile module MMC-2. PIIX4E/M provides extensive power management capabilities supports Intel® 82433BX Host Bridge, second integrated device. features 82433BX Host Bridge include DRAM controller, which supports volts with burst read 7-2-2-2 nanoseconds) SDRAM volts with burst read 8-1-1-1 megahertz, CL=2). 82433BX Host Bridge also provides CLKRUN# signal request PIIX4E/M regulate clock bus. 82433BX clock enables Self Refresh mode SDRAM during Suspend mode compatible with SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM)
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Figure illustrates block diagram Pentium processor with on-die cache mobile module MMC-2.
Processor Core Voltage
Mobile Dixon Processor Core
Sense
V_CPUPU 2.5V
V_DC 5V-21V
443BX
Memory
GCLKO GCLKI
400-Pin Connector
Figure Block Diagram Pentium Processor With On-die Cache Mobile Module MMC-2
PCLK1
SMBus
SMBus
DCLKRD DCLKWR DCLKO
PIIX4E/M Sidebands
HCLK0
Volt. Reg.
R_GTL
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
CONNECTOR INTERFACE Signal Definitions
This section provides information signal groups corresponding information. signals defined compatibility with future Intel mobile modules.
Table provides list signals category corresponding number signals each category. proper signal termination, please contact your Intel sales representative further information.
Table Connector Signal Summary
Signal Group
Memory Processor/PIIX4E/M Sideband Geyserville Technology Power Management Clocks Voltage: V_DC Voltage: V_3S Voltage: Voltage: Voltage: VCCAGP Voltage: V_CPUPU Voltage: V_CLK ITP/JTAG Module Ground Reserved Total
Number Pins
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
3.1.1
Signal List
following notations used denote signal type: Input Output Open-drain output requiring pullup resistor Open-drain input requiring pullup resistor Input/Open-drain output requiring pullup resistor Bi-directional input/output
signal description also includes type buffer used particular signal: GTL+ CMOS Open-drain GTL+ interface signal interface signals interface signals CMOS buffers voltage compatible signals with 3.3-volt outputs with 5.0-volt tolerant inputs.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
3.1.2
Memory (109 Signals)
Table lists memory interface signals. Table Memory Signal Descriptions
Name
MECC[7:0]
Type
CMOS
Voltage
Description
Memory Data: These signals carry Memory data during access DRAM. supported Pentium processor with on-die cache mobile module.
RASA[5:0]# CSA[5:0]#
CMOS
Address Strobe (EDO): These pins select DRAM row. Chip Select (SDRAM): These pins activate SDRAMs. SDRAM accepts command when active low.
CASA[7:0]# DQMA[7:0]
CMOS CMOS
Column Address Strobe (EDO): These pins select DRAM column. Input/Output Data Mask (SDRAM): These pins synchronized output enables during read cycle byte mask during write cycle.
MAB[9:0]# MAB[10] MAB[12:11]# MAB[13] MWEA# SRASA#
Memory Address (EDO/SDRAM): This column address DRAM. 82433BX Host Bridge system controller identical sets address lines (MAA MAB#). Pentium processor with on-die cache mobile module MMC-2 supports only address lines. additional addressing features, please refer Intel® 440BX AGPset Datasheet. Memory Write Enable (EDO/SDRAM): MWEA# should used write enable memory data bus. SDRAM Address Strobe (SDRAM): When active low, this signal latches Address positive edge clock. This signal also allows access precharge. SDRAM Column Address Strobe (SDRAM): When active low, this signal latches Column Address positive edge clock. This signal also allows Column access. SDRAM Clock Enable (SDRAM): SDRAM clock enable pin. When these signals deasserted, SDRAM enters power-down mode. Each individually controlled clock enable. Memory Data: These signals connected DRAM data bus. They terminated Pentium processor with on-die cache mobile module MMC-2.
CMOS CMOS
SCASA#
CMOS
CKE[5:0]
CMOS
MD[63:0]
CMOS
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
3.1.3
Signals)
Table lists interface signals. Table Signal Descriptions
Name
GAD[31:0]
Type
Voltage
Description
Address/Data: standard address data lines. This functions same AD[31:0] bus. address driven with FRAME# assertion data driven received following clocks. Command/Byte Enable: This carries command information during cycles when PIPE# used. During write, this contains byte enable information. command driven with FRAME# assertion byte enables corresponding supplied requested data driven following clocks. Frame: used during transactions. Remains deasserted internal pullup resistor. Assertion indicates address phase transfer. Negation indicates that cycle initiator desires more data transfer. Device Select: Same function DEVSEL#. used during transactions. 82433BX Host Bridge system controller drives this signal when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: Indicates compliant target ready provide write data current transaction. Asserted when initiator ready data transfer. Target Ready: Indicates compliant master ready provide write data current transaction. Asserted when target ready data transfer. Stop: Same function STOP#. used during transactions. Asserted target request master stop current transaction. Request: master requests AGP.
GC/BE[3:0]#
GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GREQ#
GGNT#
Grant: Same function PCI. Additional information provided ST[2:0] bus. Grant: Permission given master PCI. Parity: single parity provided over GAD[31:0] GC/BE[3:0]. This signal used during transactions. Pipelined Request: Asserted current master indicate full width address that queued target. master queues request each rising clock edge while PIPE# asserted. Sideband Address: This provides additional conduit pass address commands 82433BX Host Bridge System Controller from master. Read Buffer Full: Indicates master ready accept previously requested, lowpriority read data. Status Bus: Provides information from arbiter Master what These bits only have meaning when GGNT asserted. Strobes: Provide timing double-clocked data bus. agent providing data drives these signals. These identical copies each other. Sideband Strobe: Provides timing sideband bus. SBA[7:0] (AGP master) drives sideband strobe.
GPAR
PIPE#
SBA[7:0]
RBF#
ST[2:0]
ADSTB[B:A]
SBSTB
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
3.1.4
Signals)
Table lists interface signals. Table Signal Descriptions
Name
AD[31:0] C/BE[3:0]# FRAME# DEVSEL# IRDY# TRDY# STOP# PLOCK#
Type
Voltage
Description
Address/Data: standard address data lines. address driven with FRAME# assertion data driven received following clocks. Command/Byte Enable: command driven with FRAME# assertion byte enables corresponding supplied requested data driven following clocks. Frame: Assertion indicates address phase transfer. Negation indicates that cycle initiator desires more data transfer. Device Select: 82433BX Host Bridge drives this signal when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: Asserted when initiator ready data transfer. Target Ready: Asserted when target ready data transfer. Stop: Asserted target request master stop current transaction. Lock: Indicates exclusive operation require multiple transactions complete. When LOCK# asserted, nonexclusive transactions proceed. 82433BX supports lock initiated cycles only. initiated locked cycles supported. Request: master requests PCI. Grant: Permission given master PCI. Hold: This signal comes from expansion bridge; bridge request PCI. 82433BX Host Bridge will drain DRAM write buffers, drain processor-to-PCI posting buffers, acquire host before granting request PHLDA#. This ensures that timing masters. PHOLD# protocol been modified include support passive release. Hold Acknowledge: This signal driven 82433BX Host Bridge grant expansion bridge. PHLDA# protocol been modified include support passive release. Parity: single parity provided over AD[31:0] C/BE[3:0]#. System Error: 82433BX asserts this signal indicate error condition. Refer Intel® 440BX AGPset Datasheet further information. Clock Run: open-drain output input. 82433BX Host Bridge requests central resource (PIIX4E/M) start maintain clock asserting CLKRUN#. 82433BX Host Bridge tri-states CLKRUN# upon deassertion Reset (since running upon deassertion Reset). Reset: When asserted, this signal asynchronously resets 82433BX Host Bridge. signals also tri-state, compliant with Specifications.
REQ[4:0]# GNT[4:0]# PHOLD#
PHLDA#
SERR# CLKRUN#
PCI_RST#
CMOS
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
3.1.5
Geyserville Signals)
Table lists Geyserville signal definitions. Pentium processor with on-die cache mobile module MMC-2 does support Geyserville technology. Table Geyserville Descriptions
Name
G_LO/HI#
Type
CMOS
Voltage
Description
Geyserville State Transition: Generated PIIX4E/M, this signal defines Geyserville state change Geyserville state machine. This signal implemented module defined upgrade purposes only. Geyserville CPU_STP#: CPU_STP# signal gated Geyserville state machine becomes G_CPU_STP#. This signal implemented module defined upgrade purposes only. Voltage Changing: Geyserville state machine signal that indicates that actual state change progress setpoint changed settling. When this signal deasserts, state sent processor. system electronics will this signal generate force transition deep sleep. This signal implemented module defined upgrade purposes only. G_SUS_STAT1#: SUS_STAT1# signal gated Geyserville control logic. G_SUS_STAT1# should used place SUS_STAT1# signal system electronics design. This signal implemented module defined upgrade purposes only.
G_CPU_STP#
CMOS
VRCHGNG#
CMOS
G_SUS_STAT1#
CMOS
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
3.1.6
Processor/PIIX4E/M Sideband Signals)
Table lists signals processor PIIX4E/M sideband signals. voltage level these signals determined V_CPUPU. Table Processor/PIIX4E/M Sideband Signal Descriptions
Name
FERR#
Type
CMOS
Voltage
V_CPUPU
Description
Numeric Coprocessor Error: This functions FERR# signal supporting coprocessor errors. This signal tied coprocessor error signal processor driven processor PIIX4E/M. Ignore Error: This open-drain signal connected Ignore Error processor driven PIIX4E/M. Initialization: INIT# asserted PIIX4E/M processor system initialization. This signal open-drain. Processor Interrupt: INTR driven PIIX4E/M signal processor that interrupt request pending needs serviced. This signal open-drain. Non-maskable Interrupt: used force non-maskable interrupt processor. PIIX4E/M bridge generates when either SERR# IOCHK# asserted, depending Status Control Register programmed. This signal open-drain. Address Mask: When enabled, this open-drain signal causes processor emulate address wraparound which occurs Intel 8086 processor. System Management Interrupt: SMI# active synchronous output from PIIX4E/M that asserted response many enabled hardware software events. SMI# open-drain signal asynchronous input processor. However, this chip SMI# synchronous PCLK. Stop Clock: STPCLK# active synchronous open-drain output from PIIX4E/M that asserted response many hardware software events. STPCLK# connects directly processor synchronous PCICLK. When processor samples STPCLK# asserted, responds entering power state (Quick Start). processor will only exit this mode when this signal deasserted.
IGNNE# INIT# INTR
CMOS CMOS CMOS CMOS
V_CPUPU V_CPUPU V_CPUPU V_CPUPU
A20M# SMI#
CMOS CMOS
V_CPUPU V_CPUPU
STPCLK#
CMOS
V_CPUPU
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
3.1.7
Power Management Signals)
Table lists power management signals. SM_CLK SM_DATA signals refer two-wire serial SMBus
interface. Although this interface currently used solely digital thermal sensor, SMBus contains reserved serial addresses future use. section 4.9, Thermal Sensor Configuration Register" more details.
Table Power Management Signal Descriptions
Name
SUS_STAT1#
Type
CMOS
Voltage
V_3ALWAY
Description
Suspend Status: This signal connects SUS_STAT1# output PIIX4E/M. provides information host clock status asserted during suspend states. VR_ON: Voltage regulator This 3.3-V (5.0-V tolerant) signal controls operation voltage regulator. VR_ON should generated function PIIX4E/M SUSB# signal which used controlling Suspend State voltage planes. This signal should driven digital signal with rise/fall time less than equal Refer Section 4.7.2.1 `Voltage Signal Definitions Sequences."(VIL (max)=0.4V, (min)=3.0V.) VR_PWRGD: This signal driven high Pentium processor with on-die cache mobile module MMC-2 indicate that voltage regulator stable. signal pulled using 100K resistor when inactive. used some combination generate system PWRGOOD signal. Power This signal must active after power rail stable, prior deassertion PCIRST#. Serial Clock: This clock signal used SMBus interface digital thermal sensor. Serial Data: Open-drain data signal SMBus interface digital thermal sensor. Interrupt: This signal open-drain output signal digital thermal sensor.
VR_ON
CMOS
VR_PWRGD
BXPWROK SM_CLK SM_DATA ATF_INT#
CMOS CMOS CMOS CMOS
NOTE: V_3ALWAYS: 3.3-V supply. generated whenever V_DC available supplied PIIX4E/M resume well.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
3.1.8
Clock Signals)
Table lists clock signals. Table Clock Signal Descriptions
Name
PCLK
Type
Voltage
Description
Clock PCLK input module system' clocks. This clock used 82433BX Host Bridge logic clock domain. This clock stopped when PIIX4E/M PCI_STP# signal asserted and/or during suspend states. Host Clock These clocks inputs module from CK97-M clock source. processor 82433BX Host Bridge system controller HCLK[0]. This clock stopped when PIIX4E/M CPU_STP# signal asserted and/or during suspend states. SDRAM Clock Out: 66-MHz SDRAM clock reference generated internally 82433BX Host Bridge system controller onboard PLL. feeds external buffer that produces multiple copies SO-DIMMs. SDRAM Read Clock: Feedback reference from SDRAM clock buffer. 82433BX Host Bridge System Controller uses this clock when reading data from SDRAM array. This signal implemented module. SDRAM Write Clock: Feedback reference from SDRAM clock buffer. 82433BX Host Bridge system controller uses this clock when writing data SDRAM array. Clock GCLKIN input feedback reference from GCLKO signal. Clock Out: This signal generated 82433BX Host Bridge system controller onboard from HCLK0 host clock reference. frequency GCLKO MHz. GCLKO output used feed both reference input pins 82433BX Host Bridge system controller device. board layout must maintain complete symmetry loading trace geometry minimize clock skew. Frequency Select: This output signal provides status host clock frequency system electronics. This signal static pulled either high V_CLK voltage supply through 10-K resistor. This module designed 66-MHz strapping option shown below. FQS=0 indicates FQS=1 indicates (for future Intel mobile modules)
HCLK[1:0]
CMOS
V_CLK
DCLKO
CMOS
DCLKRD
CMOS
V_CLK
DCLKWR GCLKIN GCLKO
CMOS CMOS CMOS
V_CLK
CMOS
V_CLK
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
3.1.9
Voltages Signals)
Table lists voltage signal definitions. Table Voltage Descriptions
Name
V_DC V_3S
Type
Number
Pins Input: 5V-21V
Description
SUSB# controlled 3.3V: This rail used module. However, power managed 3.3-V supply. output voltage regulator system electronics. This rail during STR, STD, Soff. SUSC# controlled Power managed 5.0-V supply. output voltage regulator system electronics. This rail during Soff. SUSC# controlled 3.3V: Power managed 3.3-V supply. output voltage regulator system electronics. This rail during Soff. Voltage: This voltage rail implemented module defined upgrade purposes only. Intel recommends that this voltage rail connected system electronics. Processor Ring: Driven module power processor interface signals such PIIX4E/M open-drain pullups processor/PIIX4E/M sideband signals. Processor Clock Rail: Driven module power CK100-M VDDCPU rail.
VCCAGP
V_CPUPU V_CLK
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
3.1.10
JTAG Signals)
Table lists JTAG signals, which system manufacturer implement JTAG chain port desired. Table JTAG Pins
Name
TCLK TRST# FS_RESET#
Type
Voltage
V_CPUPU V_CPUPU V_CPUPU V_CPUPU V_CPUPU GTL+ V_CORE
Description
JTAG Test Data Out: Serial output port. instructions data shifted processor from this port. JTAG Test Data Serial input port. instructions data shifted into processor from this port. JTAG Test Mode Select: Controls controller change sequence. JTAG Test Clock: estability clock clocking JTAG boundary scan sequence. JTAG Test Reset: Asynchronously resets controller processor. Processor Reset: Processor reset status ITP. GTL+ Termination Voltage: Used POWERON debug port determine when target system POWERON pulled using resistor VTT. Debug Mode Request: Driven makes request enter debug mode. Debug Mode Ready: Driven processor informs that processor debug mode.
FS_PREQ# FS_PRDY#
V_CPUPU GTL+
NOTE: DBREST# (reset target system) debug port logically ANDed"with VR_PWRGD PIIX4E/M' PWROK.
3.1.11
Miscellaneous Signals)
Table lists miscellaneous signal pins. Table Miscellaneous Pins
Name
Module ID[3:0]
Type
CMOS
Number
Description
Module Revision These pins track revision level Pentium processor with on-die cache mobile module MMC-2. 100-K pullup resistor V_3S must placed system electronics these signals. Section 7.0, Labeling Information"for more information. Ground. Unallocated Reserved pins should connected.
Ground Reserved
RSVD
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Connector Assignments Assignments"for assignments pads connector.
Table lists signals each connector system electronics. Refer Section 3.3,
Table Connector Assignments
Number
ADSTBB GAD24 GAD29 VCCAGP GAD1 Reserved MD33 MD38 MD42 MD11 MD45 MECC0 MWEA# MID1 DQMA4 CSA2# CSA5# Reserved MAB4# Reserved Reserved MAB11# MID2 CKE2 G_LO/HI# SMCLK
SBA6 GAD26 GAD4 GAD3 GAD2 MD37 MD40 MD44 MD15 MECC5 DQMA0 MID0 CSA4# MAB0# MAB2# MAB5# Reserved MAB12# CKE3 MID3 DQMA2 Reserved MD26 MD58
GAD31 SBA4 GAD27 GAD6 GAD5 ADSTBA CLKRUN# MD32 MD35 MD39 MD10 MD13 MD47 Reserved DQMA1 DQMA5 CSA3# MAB1# Reserved Reserved Reserved MAB9# Reserved CKE0 CKE4 G_CPU_STP# DCLKWR FS_PREQ# MD57 TCLK
SBA7 SBA0 GAD8 GC/BE0# GAD7 GAD0 MD34 MD12 MD46 Reserved CSA0# Reserved MAB3# MAB6# MAB7# MAB10 DCLKO DCLKRD VRCHGNG# DQMA3 MD25 MD60 FERR#
SBA5 GAD25 GAD30 RBF# BXPWROK MD36 MD41 MD43 MD14 MECC4 SCASA# CSA1# SRASA# Reserved Reserved Reserved MAB8# Reserved MAB13 CKE1 CKE5 Reserved FS_RESET# FS_PRDY# G_SUS_STAT1#
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Number
Reserved Reserved Reserved V_CPUPU V_CLK Reserved V_DC V_DC
SMDAT Reserved V_DC V_DC
Reserved V_3S V_3S V_3S Reserved V_DC V_DC
TRST# V_3S V_3S V_3S Reserved V_DC V_DC
IGNNE# ATF_INT# V_3S V_3S V_3S Reserved V_DC V_DC
Number
GREQ# GGNT# GAD13 GAD12 GAD10 GAD11 GAD9 VCCAGP MECC1 SERR# AD16 AD19 AD23 AD27 PCI_RST# Reserved IRDY# GNT1# DQMA6
GSTOP# GPAR GAD15 GC/BE1# GAD14 VCCAGP C/BE0# AD10 AD13 TRDY# AD30 AD22 PHOLD# FRAME# GNT2# GNT4# PHLDA# MECC7
PIPE# SBA1 SBA2 GAD16 GAD18 GFRAME# GTRDY# GDEVSEL# AD15 STOP# AD17 AD24 C/BE3# AD20 AD31 REQ2# GNT0# MD50
SBA3 SBSTB GAD20 GAD17 GC/BE2# GIRDY# VCCAGP AD12 C/BE1# DEVSEL# C/BE2# AD26 AD28 AD29 REQ1# REQ3# REQ4# MD51
GCLKI GCLKO GAD23 GC/BE3# GAD22 GAD21 GAD19 GAD28 AD11 AD14 PLOCK# AD18 AD21 PCLK AD25 REQ0# GNT3# MD59 MD54
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Number
MECC2 DQMA7 MECC6 MECC3 MD27 SMI# A20M# Reserved V_DC V_DC
MD48 MD16 MD17 MD49 MD28 MD29 INTR SUS_STAT1# STPCLK# Reserved V_DC V_DC
MD18 MD19 MD21 MD20 MD61 VR_ON VR_PWRGD INIT# Reserved V_DC V_DC
MD52 MD53 MD22 MD62 MD30 Reserved V_DC V_DC
MD24 MD23 MD55 MD56 MD63 MD31 HCLK0 HCLK1 Reserved V_DC V_DC
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Assignments Figure shows assignments MMC-2 connector.
MMC-2 connector pins, 1.27-millimeter pitch, style surface mount. Refer Section 5.1.4, Height Requirements"for connector size information.
400-Pin Connector Assignments
(Viewed from Secondary Side)
Figure 400-Pin Connector Footprint Numbers
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Table summarizes some specifications connector. Table Connector Specifications
Parameter
Material Contact Housing Electrical Current Voltage
Condition
Copper Alloy
Specification
Thermo Plastic Molded Compound: 0.5A minimum maximum maximum contact cycles maximum contact minimum contact
Insulation Resistance Termination Resistance Capacitance Mechanical Mating Cycles Connector Mating Force Contact Unmating Force
FUNCTIONAL DESCRIPTION E_SMRAM feature that supports write-back cacheable SMRAM space megabyte. minimize power consumption while system idle, internal 82433BX Host Bridge clock turned (gated off) when there processor activity. This accomplished setting G_CLK enable power management register 82433BX through system BIOS. 4.3.1 Memory Organization
Pentium Processor With On-die Cache Mobile Module MMC-2
Pentium processor with on-die cache mobile module MMC-2 offers core speeds megahertz, megahertz, megahertz, megahertz, megahertz. processor speeds have 66-megahertz speed.
Cache
memory interface 82433BX Host Bridge available connector. This allows following: memory control signals, sufficient support three SO-DIMM sockets banks SDRAM megahertz. signal each bank. Memory features supported 82433BX Host Bridge system controller standard MMC-2 mode are: Support eight banks memory. Second memory address lines (MAA[13:0]). DRAM technologies supported 82433BX Host Bridge system controller include SDRAM. These memory types mixed system, that DRAM rows (RAS[5:0]#) must same technology. 82433BX Host Bridge system controller targets nanoseconds DRAMs 66-megahertz SDRAMs. Pentium processor with on-die cache mobile module MMC-2' clocking architecture supports SDRAM. Tight timing requirements 66-megahertz SDRAM clocks allow host SDRAM clocks generated from same clocking architecture. complete details about using SDRAM memory trace length guidelines, refer Mobile Pentium® processor 82433BX AGPset
on-die cache kilobytes, four-way associative, runs speed processor core. 82433BX Host Bridge System Controller Intel' 82433BX Host Bridge system controller highly integrated device that combines controller, DRAM controller, controller into component. 82433BX Host Bridge multiple power management features designed specifically notebook systems such CLKRUN#, feature that enables controlling clock off. 82433BX Host Bridge suspend modes, which include Suspend-to-RAM (STR), Suspend-to-Disk (STD), Power-On-Suspend (POS). System Management (SMRAM) power management modes, which include Compatible SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM). C_SMRAM traditional SMRAM feature implemented Intel chipsets.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Advanced Platform Recommended Design Debug Practices. Refer Intel® 440BX AGPset Datasheet details memory device support, organization, size, addressing. 4.3.2 Reset Strap Options
Several strap options memory address define behavior Pentium processor with on-die cache mobile module MMC-2 after reset. Other straps allowed override default settings. Table shows various straps their implementation.
Table Configuration Straps 82433BX Host Bridge System Controller
Signal
MAB[12]# MAB[11]# MAB[10] MAB[9]# MAB[7]# MAB[6]#
Function
Host Frequency Select Order Queue Depth Quick Start Select disable Config Host Buffer Mode Select
Module Default Setting
strap- default. strap- maximum queue depth set, i.e. Strapped high module Quick Start mode. strap- enabled. strap- standard MMC-2 mode. Strapped high module mobile buffers.
Optional Override System Electronics
None None None Pull this signal disable interface. None None
4.3.3
Interface
4.3.4
Interface
interface 82433BX Host Bridge available connector. 82433BX Host Bridge supports Clockrun protocol power management. this protocol, devices assert CLKRUN# open-drain signal when they require interface. Refer Mobile Design Guide complete details Clockrun protocol. 82433BX Host Bridge responsible arbitrating bus. With MMC-2 connector, 82433BX Host Bridge support five masters. There five Request/Grant pairs, REQ[4:0]# GNT[4:0]#, available connector manufacturer' system electronics. interface MMC-2 connector volts only. Five-volt devices supported such devices that drive outputs nominal level. 82433BX Host Bridge system controller compliant with specification, which improves worst case access latency from earlier specifications. 82433BX Host Bridge supports only Mechanism accessing configuration space, detailed specification. This implies that signals AD[31:11] available IDSEL signals. However, since 82433BX Host Bridge always device AD11 will never asserted during configuration cycles IDSEL. 82433BX reserves AD12 AGPbus. Thus, AD13 first available address line usable IDSEL. Intel recommends that AD18 used PIIX4E/M.
82433BX Host Bridge system controller compliant with Interface Specification 1.0, which supports asynchronous interface coupling 82433BX core frequency. interface achieve real data throughput excess megabytes second using graphics device. Actual bandwidth vary depending specific hardware software implementations. Power Management
4.4.1
Clock Control Architecture
clock control architecture optimal notebook designs. clock control architecture consists seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant Snoop, Sleep, Deep Sleep states. Auto Halt state provides low-power clock state that controlled through software execution instruction. Quick Start state provides very low-power, low-exit latency clock state that used hardware controlled idle"states. Deep Sleep State provides extremely low-power state that used Power-onSuspend states, which alternative shutting processor' power. exit latency Deep Sleep State been reduced microseconds. Stop Grant state Sleep states available Pentium processor with on-die cache mobile module these states intended desktop server systems. Stop Grant state Quick Start clock state mutually exclusive.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
example, strapping option signal A15# chooses which state entered when STPCLK# signal asserted. Strapping A15# signal enables Quick Start state ground Reset. Otherwise, asserting STPCLK# signal puts processor into Stop Grant state. Stop Grant state useful platforms supported Pentium processor with on-die cache mobile module. Quick Start state available module provides significantly lower power level. Figure provides illustration clock control architecture. State transitions shown Figure neither recommended supported
Normal State
HS=false
STPCLK#
(!STPCLK# !HS) RESET# halt cycle halt break STPCLK# !STPCLK#
Quick Start
BCLK stopped BCLK
STPCLK# !QSE (!STPCLK# !HS) stop break !STPCLK# STPCLK# !QSE
Auto Halt
HS=true
Snoop serviced
Snoop occurs
Deep Sleep
Snoop occurs Snoop serviced Snoop occurs
Stop Grant
Snoop serviced
HALT/Grant Snoop
SLP# !SLP# RESET# BCLK stopped
BCLK !QSE
Sleep
Halt break A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI# instruction executed Processor Halt State Quick Start State Enabled Stop Grant Acknowledge cycle issued Stop break BINIT#, FLUSH#, RESET# Intel Mobile Modules support shaded clock states
Figure Clock Control States
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
4.4.2
Normal State While Stop Grant state, assertions SMI#, INIT#, INTR, LINT[1:0]) will latched processor. These latched events will serviced until processor returns Normal state. Only each event will recognized upon return Normal state. 4.4.5 Quick Start State
This normal operating mode where processor' core clock running processor actively executing instructions. 4.4.3 Auto Halt State
This low-power mode entered processor through execution instruction. power level this mode similar Stop Grant state. transition Normal state made halt break event (one following signals going active: NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, SMI#). Asserting STPCLK# signal while Auto Halt state will cause processor transition Stop Grant state Quick Start state, where Stop Grant Acknowledge cycle will issued. Deasserting STPCLK# will cause processor return Auto Halt state without issuing Halt cycle. SMI# (System Management Interrupt) recognized Auto Halt state. return from handler either Normal state Auto Halt state. Intel Architecture Software Developer' Manual, Volume III: System Programmer' Guide more information. Halt cycle issued when returning Auto Halt state from System Management Mode (SMM). FLUSH# signal serviced Auto Halt state. After flushing on-chip, processor will return Auto Halt state without issuing Halt cycle. Transitions A20M# PREQ# signals recognized while Auto Halt state. 4.4.4 Stop Grant State
This mode entered processor with assertion STPCLK# signal when configured Quick Start state (via A15# strapping option). Quick Start state processor only capable acting snoop transactions generated priority device. Because snooping behavior, Quick Start only used single processor configurations. transition Deep Sleep state made stopping clock input processor. transition back Normal state (from Quick Start state) made only STPCLK# signal deasserted. While this state processor limited ability respond input. incapable latching interrupts, servicing snoop transactions from symmetric masters, responding FLUSH# BINIT# assertions. Quick Start state, processor will respond properly input signal other than STPCLK#, RESET#, BPRI#. other input signal changes, then behavior processor will unpredictable. serial interrupt messages begin progress while processor Quick Start state. RESET# assertion will cause processor immediately initialize itself, processor will stay Quick Start state after initialization until STPCLK# deasserted. 4.4.6 HALT/Grant Snoop State
This state available Intel mobile modules. processor enters this mode with assertion STPCLK# signal when configured Stop Grant state (via A15# strapping option). processor still able respond snoop requests latch interrupts. Latched interrupts will serviced when processor returns Normal state. Only occurrence each interrupt event will latched. transition back Normal state made deassertion STPCLK# signal, occurrence stop break event BINIT#, FLUSH#, RESET# assertion). processor will return Stop Grant state after completion BINIT# initialization unless STPCLK# been deasserted. RESET# assertion will cause processor immediately initialize itself. However, processor will stay Stop Grant state after initialization until STPCLK# deasserted. FLUSH# signal asserted, processor will flush on-chip caches return Stop Grant state. transition Sleep state made assertion SLP# signal.
processor will respond snoop transactions while Auto Halt, Stop Grant, Quick Start state. When snoop transaction presented system bus, processor will enter HALT/Grant Snoop state. processor will remain this state until snoop been serviced quiet. After snoop been serviced, processor will return previous state. HALT/Grant Snoop state entered from Quick Start state, then input signal restrictions Quick Start state still apply HALT/Grant Snoop state (except those signal transitions that required perform snoop). 4.4.7 Sleep State
This state available Intel mobile modules. Sleep state very low-power state which processor maintains context phase locked loop (PLL) maintains phase lock. Sleep state only entered from Stop Grant state. After entering Stop
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Grant state SLP# signal asserted, causing processor enter Sleep state. SLP# signal recognized Normal state Auto Halt state. processor reset RESET# signal while Sleep state. RESET# driven active while processor Sleep state, then SLP# STPCLK# must immediately driven inactive ensure that processor correctly initializes itself. Input signals (other than RESET#) change while processor Sleep state transitioning into Sleep state. Input signal changes these times will cause unpredictable behavior. Thus, processor incapable snooping latching events Sleep state. While Sleep state processor enter lowest power state, Deep Sleep state. Removing processor' input clock puts processor Deep Sleep state. PICCLK removed Sleep state. 4.4.8 Deep Sleep State
Deep Sleep state lowest power mode processor enter while maintaining context. Stopping BCLK input processor enters Deep Sleep state, while Sleep state Quick Start state. proper operation, BCLK input should stopped state. processor will return Sleep state Quick Start state from Deep Sleep state when BCLK input restarted. lock latency, there 30millisecond delay after clocks have started before this state transition happens. PICCLK removed Deep Sleep state. PICCLK should designed turn when BCLK turns when transitioning Deep Sleep state. input signal restrictions Deep Sleep state same Sleep state, except that RESET# assertion will result unpredictable behavior.
Table Clock State Characteristics Clock State Normal Auto Halt Stop Grant
Exit Latency Approximately clocks clocks Through snoop, HALT/Grant Snoop state: immediate Through STPCLK#, Normal state: clocks clocks after snoop activity. Stop Grant state clocks
Processor Power Varies 1.2W 1.2W
Snooping
System Uses Normal program execution. controlled entry idle mode. controlled entry/exit mobile throttling.
Quick Start
0.5W
controlled entry/exit mobile throttling.
HALT/Grant Snoop Sleep
specified 0.5W
Supports snooping power states. controlled entry/exit desktop idle mode support. controlled entry/exit mobile powered-on suspend support.
Deep Sleep
NOTES: Intel mobile modules support shaded clock control states. 100% tested. Specified design characterization.
Typical Power
Table shows typical power values. Table Power State Typical MMC-2 Power 0.475W 0.018W
NOTE: These average values measurement guidelines only.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
4.6.1 Electrical Requirements Requirements
Table provides power supply design criteria.
following section provides information electrical requirements Pentium processor with on-die cache mobile module MMC-2. Table Power Supply Design Specifications Symbol
Parameter Input Voltage Input Current Maximum Surge Current
12.0
21.0 17.3
Unit
Notes
DC-Surge DC-Leakage 5-Surge 5-Leakage 3-Surge 3-Leakage VCPUPU CPUPU VCLK
Typical Leakage Current Power Managed Voltage Supply Power Managed Current Maximum Surge Current Typical Leakage Current Power Managed 3.3V Voltage Supply 3.135 Power Managed 3.3V Current Maximum Surge Current Typical Leakage Current Processor Ring Voltage Processor Ring Current Processor Clock Rail Voltage Processor Clock Rail Current 2.375 2.375 24.0 4.75
5.25 3.465 35.0 2.625 2.625
0.125 0.125
NOTES: Unless otherwise noted, specifications this table apply Intel mobile processor frequencies. V_DC order determine typical V_DC current. V_DC order determine maximum V_DC current. Leakage current that expected when VR_ON deactivated V_DC still applied. These values system dependent.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
4.6.2
Requirements
Table shows BCLK requirements. Table Specifications Processor Core Pins Parameter
1,2,3
66.67
Unit
Figure
Notes processor core frequencies
Frequency
BCLK Period
15.0 ±250
BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time
>1.8V <0.7V (0.9V-1.6V) (1.6V-0.9V)
0.175 0.175
0.875 0.875
NOTES: Unless otherwise noted, specifications this table apply Intel mobile modules. timings GTL+ signals referenced BCLK rising edge 1.25V processor core pin. GTL+ signal timings (address bus, data bus, etc.) referenced 1.00V processor core pins. timings CMOS signals referenced BCLK rising edge 1.25V processor core pin. CMOS signal timings (compatibility signals, etc.) referenced 1.25V processor core pins. internal core clock frequency derived from clock. clock core clock ratio determined during initialization described predetermined Pentium processor with on-die cache mobile module MMC-2. BCLK period allows +0.5 tolerance clock driver variation. CK97 Clock Synthesizer/Driver Specification further information. Measured rising edge adjacent BCLKs 1.25V. jitter present must accounted component BCLK skew between devices. clock driver' closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into 10-pF 20-pF load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. CK97 Clock Synthesizer/Driver Specification further details. 100% tested. Specified design characterization clock driver requirement.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
4.6.2.1
Clock Signal Quality Specifications Measurement Guidelines Figure describes signal quality waveform clock processor core pins.
Table describes signal quality specifications processor core clock (BCLK) signal.
Table BCLK Signal Quality Specifications Processor Core Parameter Unit BCLK BCLK
-0.8
V/ns
Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback
BCLK rising/falling slew rate
NOTES: Unless otherwise noted, specifications this table apply Intel mobile modules. BCLK must rise/fall monotonically between VIL,BCLK VIH, BCLK. This processor clock overshoot undershoot specification 66-MHz operation. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing (rising) (falling) voltage limits. proper signal termination, refer Clocking Guidelines Mobile Pentium® Processor 440BX AGPset Advanced Platform Recommend Design Debug Practices.
Figure BCLK, TCK, PICCLK Generic Clock Waveform Processor Core Pins Voltage Regulator 4.7.1 voltage regulator (DC/DC converter) provides appropriate core voltage, ring voltage, sideband signal pullup voltage Pentium processor with on-die cache mobile module MMC-2. voltage range volts volts. Voltage Regulator Efficiency Table lists voltage regulator efficiencies.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Table Typical Voltage Regulator Efficiency
Icore,
V_DC,
12.0 12.0 12.0 12.0 12.0 12.0 12.0 21.0 21.0 21.0 21.0 21.0 21.0 21.0
I_DC,
0.370 0.702 1.044 1.404 1.762 2.144 2.528 0.159 0.295 0.438 0.584 0.736 0.890 1.043 0.091 0.170 0.253 0.340 0.429 0.519 0.617
Efficiency
82.8% 88.8% 89.8% 89.7% 88.1% 86.4% 85.0% 79.7% 87.0% 87.8% 87.3% 86.1% 84.9% 83.8% 79.3% 86.0% 87.3% 85.3% 84.1% 82.9% 80.7%
NOTES: These efficiencies will change with future voltage regulators that accommodate wider ranges input voltages. With V_DC applied voltage regulator off, typical leakage with maximum Icore indicates core current being drawn during test measurement.
4.7.2
Control Voltage Regulator VR_PWRGD signal indicates that voltage regulator power operating stable voltage level. VR_PWRGD system electronics control power inputs gate PWROK PIIX4E/M. Table lists voltage signal definitions sequences, Figure shows signal sequencing voltage planes sequencing required normal operation Pentium processor with on-die cache mobile module MMC-2.
VR_ON turns voltage regulator off. VR_ON should controlled function SUSB#, which controls system' power planes. VR_ON should switch high only when following conditions met: V_5(s) 4.5V V_DC 4.75V. Caution- Turning VR_ON prior meeting these conditions will severely damage Pentium processor with on-die cache mobile module MMC-2.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
4.7.2.1
Voltage Signal Definition Sequencing
Table Voltage Signal Definitions Sequences
Signal
V_DC
Source
System Electronics
Definitions Sequences
V_DC required between driven system electronics'power supply. V_DC powers module' DC-to-DC converter processor core voltages. module cannot inserted removed while V_DC powered supplied system electronics 82433BX. supplied system electronics 82433BX' 5.0-V reference voltage module' voltage regulator. VR_ON 3.3-V (5.0-V tolerant) signal that enables module' voltage regulator circuit. When driven active high voltage regulator circuit activated. signal driving VR_ON should digital signal with rise fall time less than equal (VIL (max)=0.4V, (min)=3.0V). result VR_ON being asserted, V_CORE output DC-DC regulator module driven core voltage processor. also used host GTL+ termination voltage, known VTT. Upon sampling voltage level V_CORE (minus tolerances ripple), VR_PWRGD driven active high. VR_PWRGD sampled active within second assertion VR_ON, then system electronics should deassert VR_ON. After V_CORE stabilized, VR_PWRGD will assert logic high (3.3V). This signal must pulled system electronics. VR_PWRGD should ANDed" with V_3s generate PIIX4E/M input signal, PWROK. system electronics should monitor VR_PWRGD verify asserted high prior active high assertion PIIX4E/M PWROK. V_CPUPU 2.5V. system electronics uses this voltage power PIIX4E/M-to-processor interface circuitry. V_CLK 2.5V. system electronics uses this voltage power HCLK[0:1] drivers processor clock.
VR_ON
System Electronics System Electronics System Electronics
V_CORE (also Module host GTL+ termination voltage VTT) VR_PWRGD Module
V_CPUPU V_CLK
Module Module
following list provides additional specifications clarifications power sequence timing Figure provides illustration. VR_ON signal only asserted logical high digital signal after V_DC volts, volts, volts. Rise Time Fall Time VR_ON must less than equal microsecond when goes through Vih. VR_ON (max) +0.4 volts (min) +3.0 volts. VR_PWRGD will asserted logic high (3.3 volts) after V_CORE stabilized V_DC reaches volts. This signal should pulled system electronics. power-on process, Intel recommends raise higher voltage power plane first (V_DC), followed lower power planes (V_5, V_3), finally assert VR_ON after above voltage levels rails. power-off process should reverse process, i.e. VR_ON gets deasserted, followed lower power planes, finally higher power planes. VR_ON must monotonically rise through fall through points. sign slope change between rising falling. VR_ON must provide instantaneous in-rush current module with following values listed Table
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Table VR_ON In-rush Current Instantaneous Operating 41.0
NOTE: These values based 3.3V VR_ON signal.
VR_ON Valid-Low Time: This specifies long VR_ON needs valid before VR_ON turned back again. going from valid then back following conditions must prevent damage system Intel mobile module: VR_ON must millisecond. original voltage level requirements turn-on must before assertion VR_ON (i.e. V_DC volts, volts, volts).
V_DC V_3S VR_ON VR_PWRGD V_CPUPU/ V_CLK
POWER SEQUENCE TIMING
PWROK board should active when VR_PWRGD active V_3S good. CPU_RST from board should active minimum after PWROK active PLL_STP# CPU_STP# inactive. Note that PLL_STP# condition RSMRST# SUSB# PIIX4E/M. V_DC 4.7V, V_5>=4.5V, V_3S>=3.0V. V_CPUPU V_CLK generated Intel Mobile Module. This power supplied processor module connector. This should first plane power VR_PWRGD specified associated high/active module regulator within less than equal max. after assertion VR_ON.
Figure Power-on Sequence Timing
4.7.3
Power Planes: Bulk Capacitance Requirements
module. However, order achieve proper filtering, additional capacitance should placed system electronics.
order provide adequate filtering in-rush current protection system design, bulk capacitance required. small amount bulk capacitance supplied
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Table details bulk capacitance requirements system electronics.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Table Capacitance Requirement Power Plane Power Plane V_DC V_3S VCC_AGP V_CPUPU V_CLK2 Capacitance Requirements 0.01 0.01 0.01 0.01 0.01 8200 8200
Ripple Current 1A-3.5A
Rating tolerance tolerance tolerance tolerance tolerance tolerance tolerance
NOTES: Placement above capacitance requirements should located near connector. V_CLK filtering should located next system clock synthesizer. Ripple current specification depends V_DC input. 5.0-V V_DC, 3.5A device required. V_DC higher, sufficient.
4.7.4
Surge Current Guidelines
approximately amperes. This information also used develop bulk capacitance requirements. Table more information. Note: Depending system electronics design, different impedances yield different results. thorough analysis should performed understand implications surge current their system. Figure shows electrical model used when analyzing instantaneous in-rush conditions, Figure illustrates results with SPICE simulation.
This section provides results worst case, surge current analysis. analysis determines maximum amount surge current that Pentium processor with on-die cache mobile module MMC-2 manage. analysis, module microfarads with 0.15 ohms each. MMC-2 approximately 30.0 milliohms series resistance, total series resistance 0.18 ohms. powering system with adapter volts), amount surge current module would
Figure Instantaneous In-rush Current Model
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Figure Instantaneous In-rush Current component height requirements millimeters) Pentium processor with on-die cache mobile module MMC-2, Polymerized Organic Semiconductor capacitors must used input bulk capacitance voltage regulator circuit. Because capacitor' susceptibility high in-rush current, special care must taken. soften in-rush current provide overvoltage overcurrent protection ramp V_DC slowly using circuit similar shown Figure
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
NOTE: Values shown reference only.
Figure Overcurrent Protection Circuit 4.7.4.1 Slew-rate Control: Circuit Description Figure voltage generated applying Adaptor Battery. (on) P-Channel MOSFET such Siliconix* SI4435DY. When voltage applied increased over 4.75 volts, UNDER_VOLTAGE_LOCKOUT circuit allows pull
gate start turn-on sequence. pulls drain toward ground forcing current flow through will start source current until after t_delay with t_delay defined
t_delay
Vpwr Vgs_max
Vgs_max
system manufacturer' Vgs_max specification volts must never exceeded. However, Vgs_max must high enough keep (on) device
Vpwr
possible. After initial t_delay, will begin source current V_DC will start ramp ramp time, t_ramp, defined
t_ramp
Maximum current during voltage ramping
Vsat Vgs_max
t_delay
Vpwr Ctotal t_ramp
With circuit shown Figure t_delay 5.53 t_tran 14.0 I_max
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Figure shows SPICE simulation circuit Figure increase reliability tantalum capacitors, slewrate control circuit described Figure voltage derate capacitor about percent. That maximum input voltage 18.0 volts, 35.0-volt, capacitor with high ripple current capability. Place five, 22-microfarad/35volt capacitors baseboard, directly V_DC pins processor module connector. Finally, slew-rate control circuit should applied every input power source system V_DC provide most protection. potential problem still exists power sources logically together node. example, system will immediately source current node V_DC Li-Ion battery pack powering system (12.0 volts PWR) Adaptor (18.0 volts) plugged into system. This because slew-rate control already Therefore, slew-rate control must applied every input power source provide most protection.
Figure Spice Simulation Using In-rush Protection (Example ONLY)) 4.7.4.2 Undervoltage Lockout: Circuit Description (V_uv_lockout) circuit shown Figure provides undervoltage protection locks applied voltage Pentium processor with on-die cache mobile module MMC-2 prevent accidental turn-on voltage. output this circuit, LM339 comparator, open
collector output. when applied voltage less than 4.75 volts. This voltage calculated with following equation with voltage across volts 2.5-volt reference generator).
V_uv_lockout
Vref.
R18.
V_uv_lockout 4.757 volt
4.7.4.3 Overvoltage Lockout: Circuit Description (V_ov_lockout)
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Pentium processor with on-die cache mobile module MMC-2 operates with maximum input voltage volts. This circuit locks input voltage exceeds maximum volts. output this circuit, LM339 comparator, open-collector output. when applied voltage more than volts. This voltage calculated with following equation:
V_ov_lockout
Vref.
V_ov_lockout 20.998 volt
4.7.4.4 Overcurrent Protection: Circuit Description Figure shows that circuit detects overcurrent condition cuts input voltage applied Pentium processor with on-die cache mobile module MMC-2. This circuit different current limit trip points, which accounts
Different maximum current drain Pentium processor with on-die cache mobile module MMC-2 different input voltages. Assuming Adaptor 18.0 volts battery Li-Ion configuration with minimum voltage volts, maximum current above circuit calculated using following expression:
With Adaptor (I_wAdaptor):
I_wAdaptor
Vref Vbe_Q1.
I_wAdaptor 0.989 Without Adaptor (I_woAdaptor):
I_woAdaptor
Vref Vbe_Q1. R14.
I_woAdaptor 2.375
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Active Thermal Feedback
Table identifies address allocated SMBus thermal sensor used Pentium processor with on-die cache mobile module MMC-2. Table Thermal Sensor SMBus Address Table
Function
Thermal Sensor
SMBus Address
1001
NOTE: thermal sensor used compliant with SMBus addressing. Please refer Pentium® processor Thermal Sensor Interface Specification.
Thermal Sensor Configuration Register temperature conversions Standby mode when receives one-shot command. However, result one-shot command during Auto Convert mode guaranteed. Intel does recommend using one-shot command monitor temperature when processor active, only Auto Convert mode should used. Refer Mobile Pentium Processor Pentium Processor Mobile Module Thermal Sensor Interface Specifications, Rev.1.0.
configuration register thermal sensor controls operating mode (Auto Convert Standby) device. Since processor temperature varies dynamically during normal operation, Auto Convert mode should used exclusively monitor processor temperature. Table shows format configuration register. RUN/STOP low, then thermal sensor enters Auto Convert mode. RUN/STOP high, then thermal sensor immediately stops converting enters Standby mode. thermal sensor will still perform
Name MASK RUN/STOP
Table Thermal Sensor Configuration Register Reset State Function Masks SMBALERT# when high. Standby mode control bit. low, device enters autoconvert mode. high, device immediately stops converting, enters standby mode where one-shot command performed. Reserved future use.
NOTE: bits should written read don' care" programming purposes.
MECHANICAL SPECIFICATION
Module Dimensions
This section provides physical dimensions Pentium processor with on-die cache mobile module MMC-2.
Figure shows board dimensions connector orientation.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Figure Board Dimensions with 400-Pin Connector Orientation
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
5.1.2
Location MMC-2 Connector
Figure shows location 400-pin connector referenced adjacent mounting hole.
Figure Board Dimensions with 400-Pin Connector- Orientation 5.1.3 Printed Circuit Board Thickness Note: system manufacturer must ensure that mechanical restraining method and/or system-level contacts able support this range compatibility with future Intel mobile modules.
Figure shows minimum maximum thickness printed circuit board (PCB). range thickness allows different technologies used with current future Intel mobile modules.
min: 0.90 max: 1.10
Printed circuit board
Figure Printed Circuit Board Thickness
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
5.1.4
Height Restrictions millimeters, millimeters, millimeters. three sizes provide flexibility choosing system electronics components between boards. Information these connectors obtained from your local Intel representative.
Figure shows mechanical stack-up associated component clearance requirements. This module keep-out zone should entered. Thesystem manufacturer establishes board-to-board clearance between module system electronics selecting three mating connectors. connector sizes available
NOTE: topside component clearance independent thickness.
Figure Keep-out Zone Thermal Transfer Plate When attaching mating block TTP, thermal elastimer thermal grease should used. This material reduces thermal resistance. thermal interface block should secured with 2.0-millimeter screws using maximum torque Kg*cm Kg*cm (equivalent 0.147 to.197 N*m). thread length 2.00-
82433BX provides heat dissipation thermal attach point where system manufacturer attach heat pipe, heat spreader plate, thermal solution transfer heat through notebook system. Figure Figure attachment dimensions from thermal interface block TTP.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
millimeter screws should 2.25-millimeter gageable thread (2.25-millimeters minimum 2.80-millimeters maximum). system manufacturer should exact dimensions maximum contact area ensure that warpage occurs. warpage occurs, thermal resistance module could adversely affected.
thermal resistance between processor core system interface (top TTP) less than Celsius watt.
Figure Thermal Transfer Plate
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Figure Thermal Transfer Plate Module Physical Support vary should calculated into final dimensions standoffs used. calculations made with Intel® MMC-2 Standoff/Receptacle Height Spreadsheet. Information this spreadsheet obtained from your local Intel representative. Figure shows standoff support hole patterns, board edge clearance, dimensions containment ring. components placed board keep-out area.
5.3.1
Module Mounting Requirements
Three mounting holes available securing module system base. Figure mounting hole locations. These hole locations board edge clearances will remain fixed Intel mobile modules. three mounting holes should used ensure long term mechanical reliability integrity system. board edge clearance includes 0.762-millimeter (0.030 inches) wide containment ring around perimeter module. This ring each layer module grounded. surface module, metal exposed shielding purposes. hole patterns also have plated surrounding ring metal standoff shielding purposes. Standoffs should used provide support installed module. distance from bottom module system electronics board with connectors mated millimeters 0.16 millimeters -0.13 millimeters. However, warpage baseboard
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
Hole detail, places
3.81+/-0.19
2.413
0.050 0.025 hole diameter
4.45 diameter grounded ring
1.27+/- 0.19 board edge ring
0.762 width containment ring
2.54+/-0.19 keep-out area
3.81+/-0.19 board edge hole centerline
Figure Standoff Holes, Board Edge Clearance, Containment Ring 5.3.2 Module Weight executing worst case power instruction mix. This includes power dissipated byall relevant components. During operating environments, processor junction temperature, must within specified range Celsius Celsius.
Pentium processor with on-die cache mobile module MMC-2 weighs approximately grams.
THERMAL SPECIFICATION Thermal Sensor Setpoint
Thermal Design Power
power handling capability system thermal solution reduced less than recommended typical thermal design power (TDP) with implementation firmware/software control throttling" which reduces power consumption dissipation. typical typical power dissipation under normal operating conditions nominal V_CORE (CPU power supply) while
thermal sensor implements SMBALERT# signal described SMBus specification. SMBALERT# always asserted when temperature processor core thermal diode thermal sensor internal temperature exceeds either upper lower temperature thresholds. SMBALERT# also asserted measured temperature equals either upper lower threshold.
Table Thermal Design Power Specification Symbol module
NOTE: During operating environments, processor temperature, must within specified range Celsius Celsius. module thermal solution design reference point thermal solution readiness total module power.
Parameter Module Thermal Design Power
Typical 11.5
Notes Module core, 82433BX, voltage regulator.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
LABELING INFORMATION label determine assembly level module. contains characters provides following information.
Intel mobile modules tracked ways. first Product Tracking Code (PTC). Intel uses
Example: PMG40002001AA Definition: Processor Module Pentium processor with on-die cache mobile module (MMC-2) Speed Identity 400, 366, 333, 300, Cache Size (256K) Notifiable Design Revision (Start 001) Notifiable Processor Revision (Start
Note: other Intel mobile modules, second field defined Pentium processor with on-die cache mobile module (MMC-1)
Figure Product Tracking Information
second tracking method generated software utility. Four strapping resistors located module determine production level. connected terminated properly, 16-module revision levels determined. generated software utility then read these bits with stepping provide complete
module manufacturing revision level. current module information, please refer latest Intel mobile module Product Change Notification letter which obtained from your local Intel sales representative.
Intel® Pentium® Processor With On-Die Cache Mobile Module MMC-2
ENVIRONMENTAL STANDARDS
environmental standards defined Table Table Environmental Standards
Parameter
Temperature Cycle Humidity Voltage
Condition
Non-operating Operating Unbiased
Specification
-40° relative humidity 3.3V Half Sine, msec Trapezoidal, 50G, msec Inclined Impact ft/s Half Sine, msec Simulated Free Fall gRMS random gRMS 11,800 impacts (low frequency) Non-powered test module only non-catastrophic failure. module tested then inserted system functional test.
Shock
Non-operating Unpackaged Packaged Packaged
Vibration
Unpackaged Packaged Packaged
Damage
Human Body Model
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