with Volt SRAM (W30) 28F6408W30, 28F3204W30, 28F320W30, 28F640W30
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Volt Intel® Wireless Flash Memory
with Volt SRAM (W30)
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Product Features
Flash Performance Initial Access Speed Page-Mode Read Speed Burst-Mode Read Speed Burst Page Mode Blocks across Partition Boundaries Enhanced Factory Programming: Word Program Time Programmable WAIT Signal Polarity Flash Power 1.70 1.90 VCCQ 2.20 3.30 Standby Current (typ.) Read Current word burst, typ.) Flash Software (typ.) Program/Erase Suspend Latency Time Intel® Flash Data Integrator (FDI) Common Flash Interface (CFI) Compatible Quality Reliability Operating Temperature: 100K Minimum Erase Cycles 0.18 ETOXVII Process
Flash Architecture Multiple 4-Mbit Partitions Dual Operation: Parameter Block Size 4-Kword Main block size 32-Kword Bottom Parameter Devices Flash Security 128-bit Protection Register: Unique Device Identifier Bits; User Protection Register Bits Absolute Write Protection with Ground Program Erase Lockout during Power Transitions Individual Instantaneous Block Locking/ Unlocking with Lock-Down SRAM Access Speed 16-bit Data Voltage Data Retention S-VCC 2.20 3.30 Density Packaging 32-Mbit Discrete Package 64-Mbit Discrete µBGA* Package Active Ball Matrix, 0.75 Ball-Pitch µBGA* Packages 32/4-, 64/8- 128/TBD- Mbit (Flash SRAM) 80-Ball Stacked-CSP Package 16-bit Data
Volt Intel®Wireless Flash Memory with Volt combines state-of-the-art Intel® Flash technology with power SRAM provide most versatile compact memory solution high performance, power, board constraint memory applications. Volt Intel Wireless Flash Memory with Volt offers multi-partition, dual-operation flash architecture that enables device read from partition while programming erasing another partition. This Read-While-Write Read-While-Erase capability makes possible achieve higher data throughput rates compared single partition devices allows processors interleave code execution because program erase operations occur background processes. Volt Intel Wireless Flash Memory with Volt incorporates Enhanced Factory Programming (EFP) mode improve factory programming performance. This feature helps eliminate manufacturing bottlenecks associated with programming high density flash devices. Compare program time word standard factory program time word save significant factory programming time improved factory efficiency. Additionally, Volt Intel Wireless Flash Memory with Volt includes block lock-down, programmable WAIT signal polarity supported array software tools. these features make this product perfect solution demanding memory application.
Notice: This document contains preliminary information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
290702-002 March 2001
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Volt Intel® Wireless Flash Memory (with Volt SRAM) contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2000 2001. *Other names brands claimed property others.
Preliminary
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Contents
Product Introduction
Document Purpose. Nomenclature Product Overview Package Diagram. Package Dimensions. Signal Descriptions. Block Diagram Flash Memory Map. Operations. Flash Command Definitions Read Array 4.1.1 Asynchronous Mode.12 4.1.2 Synchronous Mode Configuration Register (CR).13 4.2.1 Read Mode (RM).14 4.2.2 First Latency Count (LC2-0) 4.2.3 WAIT Signal Polarity (WT) 4.2.4 WAIT Signal Function.17 4.2.5 Data Output Configuration (DOC) 4.2.6 WAIT Configuration (WC).18 4.2.7 Burst Sequence (BS).19 4.2.8 Clock Configuration (CC) 4.2.9 Burst Wrap (BW) 4.2.10 Burst Length (BL2-0) Read Query Register.21 Read Register.21 Read Status Register 4.5.1 Clear Status Register Read-While-Write/Erase.24 Factory Program Mode.24 Programming Voltage Protection (VPP).25 Enhanced Factory Programming (EFP) 5.3.1 Requirements Considerations 5.3.2 Setup Phase.26 5.3.3 Program Phase 5.3.4 Verify Phase 5.3.5 Exit Phase Write Protection (VPP VPPLK)
Product Description
Product Operations
Flash Read Modes
Program Erase Voltages.24
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Flash Erase Mode
Block Erase Erase Protection (VPP VPPLK) Program/Erase Suspend. Program/Erase Resume. Block Lock. Block Unlock Lock-Down Block Block Lock Operations during Erase Suspend. Lock-Down Control. Protection Register Read Program Protection Register Protection Register Lock Power-Up/Down Characteristics Power Supply Decoupling Flash Reset Characteristics Absolute Maximum Ratings Extended Temperature Operation. Characteristics Discrete Capacitance (32-Mbit Package) Stacked Capacitance (32/4 64/8 Stacked-CSP Package) Flash Read Operations Flash Write Operations Flash Program Erase Operations. Reset Operations SRAM Read Operation SRAM Write Operation. SRAM Data Retention Operation
Flash Suspend/Resume Modes.
Flash Security Modes
Flash Protection Register
10.0
Power Reset Considerations
10.1 10.2 10.3
11.0
Electrical Specifications.
11.1 11.2 11.3 11.4 11.5
12.0
Flash Characteristics
12.1 12.2 12.3 12.4
13.0
SRAM Characteristics
13.1 13.2 13.3
14.0
Ordering Information Flash Write State Machine (WSM) Flowcharts Common Flash Interface
Appendix Appendix Appendix
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Revision History
Date Revision 09/19/00 03/14/01 Version -001 -002 Original Version 28F3208W30 product references removed (product discontinued) 28F640W30 product added Revised Table Signal Descriptions (DQ15-0, ADV#, WAIT, S-UB#, S-LB#, VCCQ) Revised Section 3.1, Operations Revised Table Command Definitions, Notes Revised Section 4.2.2, First Latency Count (LC2-0); revised Figure Data Output with Setting Code added Figure First Access Latency Configuration Revised Section 4.2.3, WAIT Signal Polarity (WT) Added Section 4.2.4, WAIT Signal Function Revised Section 4.2.5, Data Output Configuration (DOC) Added Figure Data Output Configuration with WAIT Signal Delay Revised Table Status Register Description Revised entire Section 5.0, Program Erase Voltages Revised entire Section 5.3, Enhanced Factory Programming (EFP) Revised entire Section 8.0, Flash Security Modes Revised entire Section 9.0, Flash Protection Register; added Table Simultaneous Operations Allowed with Protection Register Revised Section 10.1, Power-Up/Down Characteristics Revised Section 11.3, Characteristics. Changed ICCS,ICCWS, ICCES Specs from 21µA; changed ICCR Spec from (burst length Added Figure WAIT Signal Synchronous Non-Read Array Operation Waveform Added Figure WAIT Signal Asynchronous Page-Mode Read Operation Waveform Added Figure WAIT Signal Asynchronous Single-Word Read Operation Waveform Revised Figure Write Waveform Revised Section 12.4, Reset Operations Clarified Section 13.2, SRAM Write Operation, Note Revised Section 14.0, Ordering Information Minor text edits Description
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Product Introduction
Document Purpose
This document contains information pertaining Volt Intel® Wireless Flash Memory with Volt SRAM. Section provides product introduction. Section provides product description. Section describes general device operations. Sections through describe flash functionality. Section describes device power reset considerations. Section 11.0 describes device electrical specifications. Section 12.0 describes flash characteristics. Section 13.0 describes SRAM characteristics. Section 14.0 describes ordering information.
Nomenclature
Block: group flash bits that share common erase circuitry erase simultaneously. Partition: Partition group blocks that share erase program circuitry common
status register. block erasing word programming, only status register, rather than array data, available when address within partition read.
Main Block: flash block 32-Kwords. Parameter Block: flash block 4-Kwords. Main Partition: partition that only contains main blocks. Parameter Partition: partition that contains both main parameter blocks. Top/Bottom Parameter Device: parameter blocks located top/bottom flash memory map. top/bottom parameter partition contains blocks; main blocks parameter blocks.
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Product Description
Product Overview
Intel® Volt Wireless Flash Memory with Volt SRAM combines flash SRAM into package. Volt Intel Wireless Flash Memory with Volt divides flash memory into many separate 4-Mbit partitions. doing this, device perform simultaneous readwhile-write read-while-erase operations. With this architecture, Volt Intel Wireless Flash Memory with Volt read from partition while programming erasing another partition. This read-while-write read-while-erase capability greatly increases data throughput performance. Each partition contains eight 32-Kword blocks, called "main blocks." However, bottom parameter device, upper lower 32-Kword block segmented into eight, separate 4-Kword blocks, called "parameter blocks." Parameter blocks ideally suited frequently updated variables boot code storage. Both main parameter blocks support page burst mode reads. Volt Intel Wireless Flash Memory with Volt also incorporates Enhanced Factory Programming (EFP) mode. mode, this device provides fastest flash factory programming time possible data word. This feature greatly reduce factory flash programming time thereby increase manufacturing efficiency. Volt Intel Wireless Flash Memory with Volt offers both hardware software forms data protection. Software individually lock unlock block "on-the-fly" run-time data protection. absolute data protection, blocks locked when voltage falls below lockout threshold. Upon initial power return from reset, Volt Intel Wireless Flash Memory with Volt defaults page mode. enable burst mode, write configure configuration register. While burst mode, Volt Intel Wireless Flash Memory with Volt synchronized with host CPU. Additionally, configurable WAIT signal used provide easy flash-toCPU synchronization. Volt Intel Wireless Flash Memory with Volt maintains compatibility with Intel® Command User Interface (CUI), Common Flash Interface (CFI), Intel® Flash Data Integrator (FDI) software tools. used control flash device, used obtain specific product information, used data management. Volt Intel Wireless Flash Memory with Volt SRAM offers low-power savings features: Automatic Power Savings (APS) standby mode. flash device automatically enters following completion read cycle. Flash SRAM standby modes enabled when appropriate chip select signals de-asserted. Finally, Volt Intel Wireless Flash Memory with Volt provides program erase suspend/resume operations allow system software service higher priority tasks. offers 128-bit protection register that used unique device identification and/or system security purposes. Combined, these features make Volt Intel Wireless Flash Memory with Volt SRAM ideal solution high-performance, low-power, board-constrained memory application.
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Package Diagram
Figure 80-Ball Matrix, 0.80 Ball Pitch, Stacked-CSP 32/4-, 64/8- 128/TBD-Mbit Devices (Flash SRAM)
F-WP# F-ADV# F-ADV# F-WP F-VPP F-VCC F-VSS F-VSS F-VCC F-VPP S-LB# S-VSS S-CS2 S-VCC S-VCC S-CS2 S-VSS S-LB# S-VSS SWE# F-CLK SF-CLK S-VSS
S-UB# F-RST# F-WE# F-WE# F-RST# S-UB# DQ10 DQ13 F-WAIT F-WAIT DQ13 DQ10 S-OE# DQ12 DQ14 DQ14 DQ12 S-OE# S-CS1# F-OE# DQ11 DQ15 DQ15 DQ11 F-OE S-CS1# F-CE# S-VCC S-VCC F-VCCQ S-Vss S-VSS F-VCCQ S-VCC S-VCC F-CE# S-VSS F-VSSQ F-VCCQ F-VCC S-VSS F-VSSQ F-VSS S-VSS S-VSS F-VSS F-VSSQ S-VSS F-VCC F-VCCQ F-VSSQ S-VSS
View Ball Side Down Complete Mark Shown
Bottom View Ball Side
NOTES: lower density devices, upper address balls treated connects. example, 32-Mbit device, A23-21 will connects.
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Figure 56-Ball Matrix, 0.75 Ball Pitch, Package µBGA* Package 32Mbit 64-Mbit Discrete Devices
VCCQ VSSQ VCCQ VCCQ VSSQ VCCQ WAIT WAIT ADV# ADV# RST# RST#
View Ball Side Down Complete Mark Shown
Bottom View Ball Side
NOTE: balls will populated; however, addresses will
Table
Package Dimensions
Package Outline Dimensions
Package Type µBGA* Stacked-CSP Device Density Mbit Mbit 32/4, 64/8 Dimension-D 14.0 Dimension-E Height (max.) (mm)
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Table
Symbol A25-0 Type
Signal Descriptions
Signal Descriptions (Sheet
Name Function ADDRESS: Device address. Addresses internally latched during read write cycles. 32-Mbit flash: A20-0; 64-Mbit flash: A21-0; 128-Mbit flash: A22-0; 4-Mbit SRAM: A17-0; 8-Mbit SRAM: A18-0 DATA INPUT/OUTPUTS: Inputs data commands during write cycles, outputs data during query, reads, memory, status register, protection register, configuration code reads. Data signals float when chip outputs deselected. Data internally latched during writes. Query accesses status register accesses DQ0-DQ7. other accesses DQ0-DQ15. FLASH ADDRESS VALID: Internally latches addresses. page mode, addresses internally latched rising edge ADV#. burst mode, address internally latched rising edge ADV# rising/ falling edge CLK, whichever occurs first. Connect ADV# when flash device operating asynchronous mode only. FLASH CHIP ENABLE: Enables/disables flash device. CE#-low enables device. CE#-high disables device places device into standby mode. high places data WAIT signals High-Z level. SRAM CHIP SELECT1: Activates SRAM internal control logic, input buffers, decoders sense amplifiers. S-CS1# active low. S-CS1# high deselects SRAM memory device reduces power consumption standby levels. SRAM CHIP SELECT2: Activates SRAM internal control logic, input buffers, decoders sense amplifiers. S-CS2 active high. S-CS2 deselects SRAM memory device reduces power consumption standby levels. FLASH CLOCK: Synchronizes device system frequency. (Used only burst mode.) FLASH OUTPUT ENABLE: Enables/disables device output buffers. enables device output buffers. high disables device output buffers places outputs High-Z level. SRAM OUTPUT ENABLE: Activates SRAM outputs through data buffers during read operation. S-OE# active low. FLASH RESET: Enables/disables device operation. RST# initializes internal circuitry disables device operation. RST# high enables device operation. FLASH WAIT: Indicates valid data burst read mode. WAIT High-Z until configuration register CR.10 set, which also determines polarity when asserted. FLASH WRITE ENABLE: Enables/disables device write buffers. enables device write buffers. Data latched rising edge WE#. high disables device write buffers. SRAM WRITE ENABLE: Controls writes SRAM memory array. S-WE# active low. SRAM UPPER BYTE ENABLE: Enables upper bytes SRAM (DQ15-8). S-UB# active low. S-UB# S-LB# must tied together restrict mode. SRAM LOWER BYTE ENABLE: Enables lower bytes SRAM (DQ7-0). S-LB# active low. S-UB# S-LB# must tied together restrict mode. FLASH WRITE PROTECT: Enables/disables device lock-down function. enables lockdown mechanism blocks marked lock-down cannot unlocked system software. high disables lock-down mechanism blocks marked lock-down unlocked system software. FLASH PROGRAM/ERASE POWER: Hardware erase program protection. valid voltage this ball allows erase programming. Memory contents cannot altered when VPPLK. Block erase program invalid voltages should attempted. in-system read, program, erase operations. must remain above VPP1Min perform in-system operations. VPP2 applied main blocks 1000 cycles maximum parameter blocks 2500 cycles. VPP2 cumulative total, exceed hours maximum. Extended this ball VPP2 reduce block cycling capability. FLASH POWER SUPPLY: Flash operations invalid voltages should attempted. FLASH OUTPUT POWER SUPPLY: Enables input output signals driven VCCQ.
DQ15-0
ADV#
S-CS1#
S-CS2 S-OE# RST# WAIT S-WE# S-UB# S-LB#
VCCQ
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Table
Symbol VSSQ S-VCC S-VSS Type
Signal Descriptions (Sheet
Name Function FLASH POWER SUPPLY GROUND: Balls internal device circuitry must connected system ground. FLASH OUTPUT POWER SUPPLY GROUND: Balls internal device circuitry must connected system ground. SRAM POWER SUPPLY: Device operations invalid S-VCC voltages should attempted. SRAM GROUND: Balls internal device circuitry must connected system ground. DON'T USE: this ball. This ball should connected power supplies, control signals and/or other ball must floated. CONNECT: internal connection. driven floated. NOTE: non-discrete devices, flash signals prefixed with before signal's name.
Block Diagram
Figure Volt Intel® Wireless Flash Memory with Volt SLRAM Block Diagram
VCCQ
VSSQ
ADV# RST# 18-20 19-21 19-22 DQ15-0 Mbit Flash Memory WAIT
A0-17 0-18 S-SC S-SC S-OE# S-WE# S-LB# S-UB# SRAM Mbit
Flash Memory
Volt Intel® Wireless Flash Memory with Volt memory divided into separate partitions support read-while-write/erase function. Each partition 4-Mbits size operate independently from other partitions.
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32-Mbit device will have eight partitions; 64-Mbit device will have partitions; 128-Mbit device will have partitions. Each main block 32-Kword size. Volt Intel Wireless Flash Memory with Volt supports CPUs that boot from either bottom flash memory map. parameter flash device highest addressable 32-Kword block divided into eight smaller blocks. Conversely, bottom parameter flash device lowest addressable 32-Kword block divided into eight smaller blocks. Each these eight 4Kword blocks called parameter blocks. Parameter blocks useful frequently stored data variables. Their smaller block size allows them erase faster than main blocks. Page- burstmode reads also permitted blocks across partition boundaries. should mentioned that SRAM does adhere this multi-partition architecture. SRAM memory organized single memory array.
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Figure Flash Memory
Mbit
Parameter Device divides highest 32-Kword main block into eight 4-Kword parameter blocks xxF000 xxFFFF xxE000 xxEFFF xxD000 xxDFFF xxC000 xxCFFF xxB000 xxBFFF xA000 xxAFFF xx9000 xx9FFF xx8000 xx8FFF Partition Blocks Start Stop Addr 1F8000 1FFFFF 1F0000 1F7FFF 1E8000 1EFFFF 1E0000 1E7FFF 1D8000 1DFFFF 1D0000 1D7FFF 1C8000 1CFFFF 1C0000 1C7FFF Partition Blocks Start Stop Addr 3F8000 3FFFFF 3F0000 3F7FFF 3E8000 3E7FFF 3E0000 3E7FFF 3D8000 3D7FFF 3D0000 3D7FFF 3C8000 3CFFFF 3C0000 3C7FFF
Mbit
Partition Blocks Start Stop Addr 7F8000 7FFFFF 7F0000 7F7FFF 7E8000 7E7FFF 7E0000 7E7FFF 7D8000 7D7FFF 7D0000 7D7FFF 7C8000 7CFFFF 7C0000 7C7FFF
Mbit
Partition Main Blocks 180000 1BFFFF
Mbit
Partition Main Blocks 380000 3BFFFF
Mbit
Partition Main Blocks 780000 7BFFFF
Mbit
Partition Main Blocks 140000 17FFFF
Mbit
Main Blocks Start Stop Addr F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF
Partition Main Blocks 100000 13FFFF
Mbit
Partition Main Blocks C0000 FFFFF
Mbit
Partition Main Blocks 80000 BFFFF
Mbit
Mbit
Mbit
Partition Main Blocks 40000 7FFFF
Mbit
Partition Main Blocks 40000 7FFFF
Partition Main Blocks 40000 7FFFF
Mbit
Partition Blocks Start Stop Addr 38000 3FFFF 30000 37FFF 28000 2FFFF 20000 27FFF 18000 1FFFF 10000 17FFF 08000 0FFFF 00000 07FFF Partition Blocks Start Stop Addr 38000 3FFFF 30000 37FFF 28000 2FFFF 20000 27FFF 18000 1FFFF 10000 17FFF 08000 0FFFF 00000 07FFF
Mbit
Partition Blocks Start Stop Addr 38000 3FFFF 30000 37FFF 28000 2FFFF 20000 27FFF 18000 1FFFF 10000 17FFF 08000 0FFFF 00000 07FFF
Mbit
Bottom Parameter Device divides lowest 32-Kword main block into eight 4-Kword parameter blocks 7000 7FFF 6000 6FFF 5000 5FFF 4000 4FFF 3000 3FFF 2000 2FFF 1000 1FFF 0000 0FFF
NOTES: Partition size: Mbit/256 Kword/512 Kbytes. Main block size: Kword/64 Kbytes. Parameter block size: Kword/8 Kbytes. partitions have main blocks, except top/bottom parameter partitions. Top/bottom parameter partitions have blocks, main parameter.
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Product Operations
Operations
Volt Intel® Wireless Flash Memory's on-chip Write State Machine (WSM) manages erase program algorithms. local controls in-system read, program, erase operations flash device. cycles from flash device conform standard microprocessor operations. RST#, CE#, OE#, WE#, ADV# signals control flash. WAIT informs valid data during burst reads. S-OE#, S-WE#, S-CS1#, S-CS2, S-LB# S-UB# control SRAM. S-UB# S-LB# must tied together restrict mode. Table summarizes operations.
Table
Operations
S-CS1# S-UB# S-LB#7 S-WE# S-OE# S-CS2 ADV# Mode RST# WAIT Note
[15:0]
Read Output Disable FLASH Standby Reset Write Read Output Disable SRAM Standby Data Retention Write
1,2,
Valid High-Z High-Z High-Z High-Z High-Z
SRAM must High-Z
DOUT High-Z
Valid SRAM Mode
High-Z High-Z
SRAM must High
Flash must High-Z
DOUT High-Z High-Z High-Z
Valid FLASH Mode Flash must High-Z High-Z
NOTES: Manufacturer device codes accessed Read Register command. Query status register accesses only DQ7-0. other accesses DQ15-0. must control signals addresses. Refer Table "Command Definitions" page valid during write operation. devices drive memory same time. SRAM placed into data retention mode lowering S-VCC limit when standby mode. Always S-UB# S-LB# together.
Flash Command Definitions
Device operations selected writing specific commands Command User Interface (CUI). Table "Command Code Descriptions" page lists possible command codes descriptions. Table "Command Definitions" page further defines command cycle operations. Since commands partition-specific, important write commands within target partition range. Multi-cycle command writes flash memory partition must issued sequentially without intervening command writes. example, Erase Setup command partition must immediately followed Erase Confirm command order executed properly. address given during Erase Confirm command determines location erase. Erase
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Confirm command given partition then command will executed, block partition will erased. Alternatively, Erase Confirm command given partition command will still executed, block partition will erased. other command given partition prior Erase Confirm command will result command sequence error, which posted status register. After erase successfully started partition read cycles occur other partition. Table
Mode Instruction Code Read
Command Code Descriptions (Sheet
Command Read Array Read Status Register Read Register, Read Configuration Register Read Query Register Clear Status Register Word Program Setup Alternate Word Program Setup Enhanced Factory Programming Setup Enhanced Factory Programming Confirm Description Places addressed partition read array mode. Places addressed partition read status register mode. partition automatically enters read status register mode after valid Program/Erase command executed. Puts addressed partition read device identifier mode. device outputs manufacturer device codes, configuration register settings, block lock status protection register data. Data output DQ15-0. Puts addressed partition read query mode. device outputs Common Flash Interface (CFI) information DQ7-0. Clears status register bits reset bits preferred first cycle program command that prepares program operation. second cycle command latches address data. Read Array command required read array data after programming. Equivalent Word Program Setup command (40h). Activates Enhanced Factory Programming mode (EFP). first cycle sets command. second cycle Confirm command (D0h), subsequent writes provide program data. other commands ignored once mode begins. first command Enhanced Factory Programming Setup (30h), latches address, confirms command data, prepares device mode. Prepares block erase operation. device erases block addressed Erase Confirm command. next command Erase Confirm,
Program
Erase
Block Erase Setup
Erase Confirm
Suspend
Program Erase Suspend
Block Locking
Suspend Resume Lock Setup Lock Block Unlock Block Lock-Down
sets status register bits SR.4 SR.5 "1," places partition read status register mode waits another command. first command Erase Setup (20h), latches address data erases block indicated erase confirm cycle address. During program/erase, partition responds only Read Status Register, Program Suspend, Erase Suspend commands. toggle updates status register data. This command issued device address initiates suspension currently executing program/erase operation. status register, invoked Read Status Register command, indicates successful operation suspension setting status bits SR.2 (program suspend) SR.6 (erase suspend) SR.7. remains suspend mode regardless control signal states, except RST# VIL. This command issued device address resumes suspended program erase operation. Prepares lock configuration. next command Block-Lock, Unlock, Lock-Down sets SR.4 SR.5 indicate command sequence error. previous command Lock Setup (60h), locks addressed block. After Lock Setup (60h) command latches address unlocks addressed block. previously Locked-down, operation effect. After Lock Setup (60h) command, latches address locks-down addressed block.
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Table
Configuration Protection Mode Instruction Code
Command Code Descriptions (Sheet
Command Description
Prepares protection register program operation. second cycle Protection Program latches address data. read array data after programming, issue Read Array Setup command. Configuration Setup Configuration Register Prepares device configuration. Configuration Register next command, sets SR.4 SR.5 indicate command sequence error. previous command Configuration Setup (60h), writes data into configuration register A15-0. Following Configuration Register command, subsequent read operations access array data.
NOTE: Unassigned instruction codes should used. Intel reserves right redefine these codes future functions.
Table
Mode
Command Definitions
Command Cycles First Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr(1) Data(2,3) 40h/10h Write Write Write Write Write FFFDh Write Write Write Read Read Read XnA+IA PnA+QA Oper Second Cycle Addr(1) Data(2,3)
Read Array Read Register READ PROGRAM ERASE LOCK CONFIG- PROTECURATION TION Read Query Register Read Status Register Clear Status Register Block Erase Word Program Enhanced Factory Program Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection Program Lock Protection Program
Configuration Register
Write
Write
NOTES: First cycle command addresses should same operation's target address. Examples: firstcycle address Read Register command should same Identification Code address (IA); first cycle address Program command should same word address (WA) programmed; first cycle address Erase/Program Suspend command should same address within block suspended; etc. valid address within device. Identification code address. Address within block. Lock Protection Address obtained from (via Read Query command). Intel®1.8 Volt
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Wireless Flash Memory Flash Memory family's 0080h. User programmable 4-word protection address device identification plane. Address within partition. Base Address where partition, main block parameter block. Figure "Device Identification Codes" page details. Query code address. Word address memory location written. Data read from status register DQ7-0. Data written location Identifier code data. =User programmable 4-word protection data. Query code data DQ7-0. Configuration register code data presented device addresses A15-0. AMAX-16 address bits select partition. Table "Configuration Register Bits" page configuration register bits descriptions. Commands other than those shown above reserved Intel future device implementations should used.
4.1.1
Flash Read Modes
Read Array
Asynchronous Mode
Volt Intel® Wireless Flash Memory with Volt supports asynchronous reads. asynchronous read executed implementing read operation without signal. During asynchronous read operation, signal ignored. asynchronous reads will only read mode operation, recommended that signal held valid level. Page mode default read mode after power-up reset. page-mode read outputs words asynchronous data; however, manipulating certain control signals, device made output less than words. After power-up reset, necessary execute Read Array command before accessing flash memory. However, perform flash read other time, necessary execute Read Array command before accessing flash memory. Page mode permitted blocks, across partition boundaries operates independent VPP. single-word read used access register information. During asynchronous reads, address latched rising edge ADV#. Upon completion reading array, device automatically enters Automatic Power Savings (APS) mode. mode consumes power comparable standby mode.
4.1.2
Synchronous Mode
Volt Intel® Wireless Flash Memory supports synchronous reads. synchronous read executed implementing read operation with signal. During synchronous read operation, signal edge (rising falling) controls flash array access. burst-mode read synchronized signal outputs continuous-word data stream based configuration register settings. However, manipulating certain control signals, device made output less then continuous-words.
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Burst mode default mode after power-up device reset. perform burst-mode read, configuration register must set. configuration register, refer Section 4.2, "Set Configuration Register (CR)" page After setting configuration register, first device operation burst-mode read, necessary execute Read Array command before accessing flash memory. However, perform flash read other time, necessary execute Read Array command before accessing flash memory array. Burst mode permitted blocks, across partition boundaries operates independently VPP. single-word burst-mode read cannot used access register information. burst mode, address latched either rising edge ADV# rising edge with ADV# low, whichever occurs first. Upon completion reading array, device automatically enters Automatic Power Savings (APS) mode. mode consumes power comparable standby mode.
Configuration Register (CR)
configuration register bits wide. This register used configure burst mode parameters. Therefore, using page mode, necessary this register. configuration register, execute Configuration Register command. bits data used this command must placed address lines A15-0. other address lines must held (VIL). After setting configuration register, first device operation flash burst-mode read, necessary execute Read Array command before accessing flash memory. However, perform burst-mode read other time, necessary execute Read Array command before accessing flash memory.
Table
Configuration Register Bits
Configuration Register Bits2
LC2-0
BL2-0
NOTES: bits reserved bits. These bits other address lines must low. power-up return from reset, bits "1."
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Table
Configuration Register Settings
Name Read Mode (RM) CR.15 Setting Burst synchronous mode. Page asynchronous mode.
First Latency Count (LC2-0) CR.13 CR.11
Code 000. Reserved. Code 001. Reserved. Code 010. Code 011. Code 100. Code 101. Code 110. Reserved. Code 111. Reserved. active signal. active high signal hold data clock cycle. hold data clock cycles. WAIT signal asserted during 16-word boundary transition. WAIT signal assert data cycle before 16-word boundary transition. Intel burst sequence. linear burst sequence. falling edge clock. rising edge clock. Wrap enabled. Wrap disabled. Word burst mode. Word burst mode. Reserved. Continuous burst mode.
WAIT Polarity (WT) CR.10 Data Output Configuration (DOC) CR.9 WAIT Configuration (WC) CR.8 Burst Sequence (BS) CR.7 Clock Configuration (CC) CR.6 Burst Wrap (BW) CR.3
Burst Length (BL2-0) CR.2 CR.0
4.2.1
Read Mode (RM)
CR.15 sets flash read mode. read modes page mode (default mode) burst mode. flash device only configured these modes time.
4.2.2
First Latency Count (LC2-0)
First Access Latency Count configuration tells device many clocks must elapse from ADV#-high (VIH) before first data word should driven onto data pins. input clock frequency determines this value. Table "Configuration Register Bits" page latency values. Figure "First Access Latency Configuration" page shows data output latency from ADV#-active different latencies. these equations calculate First Access Latency Count: Frequency} Period
(CLK Period) tAVQV (ns) tADD-DELAY (ns) tDATA (ns) First Access Latency Count (LC)
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Clock periods (rounded next integer)
*Must when starting address aligned four-word boundary CR.3 Wrap).
Table First Latency Count (LC)
Setting Mode continuous Wrap disabled disabled enabled enabled Aligned 4-word Boundary Wait Asserted 16-Word Boundary Crossing yes, occurs every occurrence yes, occurs once
Figure Word Boundary
Word
Word
Word
Word
Word Boundary Word Boundary
NOTE: 16-word boundary device word-line.
Parameters defined CPU: tADD-DELAY Clock CE#, ADV#, Address Valid whichever occurs last. tDATA Data Clock. Parameters defined flash: tAVQV Address Output Delay. Example: Clock Speed tADD-DELAY (typical speed from CPU) (max) tDATA (typical speed from CPU) (min) tAVQV (from Characteristic Read Only Operations Table) From (1): 1/52 (MHz) 19.2 From n(19.2 n(19.2 80/19.2 4.17 (Integer) From n-2=5-2=3 First Access Latency Count Setting Code (Figure "Data Output with Setting Code page displays example data)
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
formula tAVQV (ns) tADD-DELAY (ns) tDATA (ns) also known initial access time. Figure shows data output available valid after four clocks from ADV# going first clock period with setting Figure Data Output with Setting Code
tADD ADV#
tDATA
AMAX-0 Code DQ15-0 (D/Q)
Valid Address
High
Valid Output
Valid Output
R103
Figure First Access Latency Configuration
Valid Address
Address
ADV# Code (Reserved) 15-0 [D/Q] 15-0 [D/Q] 15-0 [D/Q] 15-0 [D/Q] 15-0 [D/Q] 15-0 [D/Q] 15-0 [D/Q] 15-0 [D/Q] Code
Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output
Code (Reserved)
Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code
Valid Output
Valid Output
Valid Output
Valid Output
Code
Valid Output
Valid Output
Valid Output
Code (Reserved)
Valid Output
Valid Output
Code (Reserved)
Valid Output
FREQCONF.WMF
4.2.3
WAIT Signal Polarity (WT)
WAIT signal polarity register CR.10 (WT).
When CR.10 WAIT active low. WAIT signal indicates "asserted" state.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
When CR.10 WAIT active high. WAIT signal indicates "asserted" state. WAIT signal "asserted" means that WAIT signal indicating "wait" condition. WAIT signal "deasserted" means that WAIT signal indicating "wait" condition
(i.e., valid). WAIT High-Z until device active (CE# VIL). synchronous read array mode, when device active (CE# VIL) data valid, CR.10 (WT) determines WAIT goes VOL. WAIT signal only "deasserted" when data valid bus. Invalid data drives WAIT signal "asserted" state. asynchronous page mode, WAIT always "asserted" state (CR.10
4.2.4
WAIT Signal Function
WAIT signal indicates data valid when device operating synchronous burst mode (CR.15 "0"), when addressing partition that currently read array mode. WAIT signal only "deasserted" when data valid bus. WAIT signal polarity CR.10. When device operating synchronous non-read-array mode, such read status, read read query, WAIT "asserted" state determined CR.10. Figure page displays WAIT Signal Synchronous Non-Read Array Operation Waveform. When device operating asynchronous page mode asynchronous single word read mode, WAIT "asserted" state determined CR.10. Figure "WAIT Signal Asynchronous Page-Mode Read Operation Waveform" page Figure "WAIT Signal Asynchronous Single-Word Read Operation Waveform" page From system perspective, WAIT signal will asserted state (based CR.10) when device operating synchronous non-read array mode (such Read Read Query, Read Status), device operating asynchronous mode (CR.15 "1"). these cases, system software should ignore (mask) WAIT signal, does convey useful information about validity what appearing data bus. Systems several components' WAIT signals together.
4.2.5
Data Output Configuration (DOC)
Data Output Configuration (CR.9) determines whether data word remains valid data clock cycles. processor's minimum data set-up time flash memory's clock-to-data output delay determine whether clocks needed. Data Output Configuration one-clock data hold, this corresponds one-clock data cycle; Data Output Configuration two-clock data hold, this corresponds twoclock data cycle. This configuration bit's setting depends system characteristics. Refer Figure "Data Output Configuration with WAIT Signal Delay" page clarification. method determining what this configuration should shown below: device clock data hold subsequent reads, following condition must satisfied: tCHQV (ns) tDATA (ns) Period (ns)
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
example, clock frequency will used. clock period 19.2 This data applied formula above subsequent reads assuming data output hold time clock: 19.2 This equation satisfied data output will available valid every clock period. tDATA long, hold cycles. assume clock frequency MHz. This corresponds period. initial access time calculated This condition satisfies tAVQV (ns) tADD-DELAY (ns) tDATA (ns) shown above First Access Latency Count equations. However, data output hold time clock violates one-clock data hold condition: tCHQV (ns) tDATA (ns) Period less than clock period satisfy formula above, data output hold time must clocks correctly allow data output setup time. This formula also satisfied tDATA (ns) which yields: page mode reads, initial access time determined formula: tADD-DELAY (ns) tDATA (ns) tAVQV (ns) subsequent reads page mode defined tAPA (ns) tDATA (ns) (minimum time) Figure Data Output Configuration with WAIT Signal Delay
WAIT (CR.8 tCHQV WAIT (CR.8 Note
Valid Output Valid Output Valid Output
Note
Data Hold
DQ15-0
tCHTL/H tCHQV
WAIT (CR.8 WAIT (CR.8
Note Note
Valid Output Valid Output
Data Hold DQ15-0
Note1: WAIT shown active high (CR.10
4.2.6
WAIT Configuration (WC)
CR.8 sets WAIT signal delay. WAIT signal delay determines when WAIT signal asserted. WAIT signal asserted either clock before time misaligned 16-word boundary crossing. asserted WAIT signal indicates invalid data data bus.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
synchronous mode, WAIT active when asserted. WAIT signal asserted burst-mode read misaligned 4-word boundary. misaligned, imply that address must mod-4 boundary; such xx00h, xx04h, xx08h xx0Ch. address aligned 4-word boundary, "delay" will never seen. Also, "delay" will only occur once burstmode read sequence. When misaligned burst-mode read crosses 16-word boundary, device must deselect order select next row. this selecting/de-selecting energizing/ de-energizing) memory rows that causes device "delay" output data. assertion WAIT signal that informs interfacing processor this pending flash "delay." During "delay," subsequent data reads prohibited. WAIT signal asserted depending burst starting address latency count. starting address aligned 4-word boundary, delay will occur. starting address aligned 4-word boundary, delay equal clock cycle less than latency count will occur (worst case scenario). Table "WAIT Delay" page starting address falls between, delay will dependent upon latency count value starting address indicated Table 8-word burst modes with burst wrap enabled, device will assert WAIT signal. However, with burst wrap disabled, flash device will assert WAIT signal burst-mode read misaligned crosses 16-word boundary. With wrap disabled, burst mode will read consecutive words based initial address. initial address aligned mod-4 boundary, WAIT signal will asserted. However, initial address misaligned mod-4 boundary crosses 16-word boundary limit, WAIT signal will asserted. continuous-word burst mode, burst wrap feature does apply WAIT signal only asserted first 16-word boundary crossing. WAIT signal inactive High-Z state when accessing register information. Table WAIT Delay
Starting Burst Address xx0h, xx4h, xx8h, xxCh xx1h, xx5h, xx9h, xxDh xx2h, xx6h, xxAh, xxEh xx3h, xx7h, xxBh, xxFh WAIT Delay Clock Cycles After Crossing 16-Word Boundary Delay Boundary 4-Word Boundary Start Boundary
4.2.7
Burst Sequence (BS)
CR.7 sets burst sequence. burst sequence determines 8-word output order. 8-word burst modes, burst sequence defined either linear Intel. continuous burst mode, burst sequence always linear. burst sequence depends interfacing processor's characteristics.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Table Sequence Burst Length
Burst Addressing Sequence (Decimal) Start Addr (Decimal) Wrap (CR.3) 4-Word Burst Length (CR2-0 001) Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Intel 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8-Word Burst Length (CR2-0 010) Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Intel 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Continuous Burst (CR2-0 111) Linear 0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10-. 5-6-7-8-9-10-11-. 6-7-8-9-10-11-12-. 7-8-9-10-11-12-13-. 14-15-16-17-18-19-20. 15-16-17-18-19-20-21. 0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10-. 5-6-7-8-9-10-11-. 6-7-8-9-10-11-12-. 7-8-9-10-11-12-13-. 14-15-16-17-18-19-20. 15-16-17-18-19-20-21.
0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-1314
4.2.8
Clock Configuration (CC)
CR.6 sets clock configuration. clock configuration determines which edge clock flash device will respond while burst mode. device configured either track rising falling edge clock.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
4.2.9
Burst Wrap (BW)
CR.3 sets burst wrap. burst wrap determines device will handle burst-mode read that crosses 16-word boundary. Wrap have either burst mode wrap around same have burst read consecutive addresses. Wrap applies 8-word burst modes only. Wrap effect continuous burst mode. 8-word burst mode with wrap enabled, WAIT signal will asserted. 8word burst mode with wrap disabled, WAIT signal will asserted only 16-word boundary crossed.
4.2.10
Burst Length (BL2-0)
CR.2-CR.0 sets burst length. burst length determines maximum number consecutive words device will output during burst-mode read. Volt Intel® Wireless Flash Memory with Volt supports continuous-word burst lengths.
Read Query Register
query plane comes foreground occupies 4-Mbit address range partition supplied Read Query command address. mode outputs Common Flash Interface (CFI) data when partition addresses read. Appendix "Common Flash Interface" page shows query mode information addresses. Issuing Read Query command partition that programming erasing places that partition's outputs read query mode while partition continues program erase background. Read Query command subject read restrictions dependent parameter partition availability. Refer Table "Simultaneous Operations Allowed with Protection Register" page details.
Read Register
Identification (ID) Register contains various product information, such manufacturer device block lock status, protection register information, configuration register settings. obtain information from register, execute Read Register command. Information contained this register only accessed executing single-word asynchronous read.
Table Device Identification Codes
Item Manufacturer Code Mbit Device Code: Mbit Mbit Block Lock Configuration Block Unlocked Block Locked Block Locked-Down Block Locked-Down
Address(1,2,3) 000000h 000001h 000001h 000001h
Data 0089h 8852h 8853h 8854h 8855h 8856h 8857h
MBBA 000002h PBBA 000002h, depends block
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Table Device Identification Codes
Item Configuration Register Settings Protection Register Lock Status Protection Register Data Address(1,2,3) 000005h 000080h +000081h 000088h Data CD(5) PR-LK(6) PR(7)
NOTES: Partition Base Address. AMAX MBBA Main Block Base Address. MBBA AMAX PBBA Parameter Block Base Address. PBBA AMAX Block Lock Status section valid lock status. Configuration Register Settings. PR-LK Protection Register Lock status. Protection Register data.
Read Status Register
status register bits wide. status register contains information pertaining current condition flash device partitions. determine partition's status, execute Read Status Register command. read status register data, execute signal-word asynchronous read. status register considered value cleared value zero (0). Status register data output DQ7-0; DQ15-8 outputs 00h. Each partition status register data. Information contained this register only accessed executing singleword asynchronous read.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Table Status Register Definitions
SR.7 SR.7 SR.6 SR.5 SR.6 Name Device Status (DWS) Erase Suspend Status (ESS) Erase Suspend (ES) SR.5 SR.4 VPPS SR.3 SR.2 NOTES Device busy with program erase operation. Device ready. EFP, Table erase operation, any, being suspended. erase operation being suspended. Block erase successful. Block erase error. three bits indicate command sequence error. Word program successful. Word program error. three bits indicate command sequence error. voltage level VPPLK. voltage level VPPLK. Hardware program/erase lockout. SR.1 SR.0
SR.4
Program Status (PS)
SR.3
Status (VPPS) Note: This does provide continuous feedback. Signal functionality guaranteed when VPP1 VPP2. program operation, any, being suspended. Program Suspend Status (PSS) program operation being suspended. Block unlocked. Device Protect Status (DPS) erase program operation attempted locked block. VIL. other partition busy. Partition Write/Erase Status (PWS) Another partition busy performing erase program operation. EFP, Table
SR.2 SR.1 SR.0
Table Status Register Description
(SR.7) (SR.0) Description addressed partition performing program/erase operation. other partition active. Enhanced Factory Programming: device finished programming verifying data ready data. partition other than currently addressed performing program/erase operation. Enhanced Factory Programming: device either programming verifying data. program/erase operation progress partition. Erase Program suspend bits (SR.6 SR.2) indicate whether other partitions suspended. Enhanced Factory Programming: device exited mode. Won't occur standard program erase modes. Enhanced Factory Programming: this combination will occur.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
4.5.1
Clear Status Register
clear status register, execute Clear Status Register command. When status register cleared, only bits cleared. status register considered value cleared value zero (0). Since bits indicated different error conditions and/or device states, these bits only cleared cleared when Clear Status Register command given. status register should cleared before implementing program erase operations. After executing Clear Status Register command, device returns read array mode. device reset also clears status register.
Read-While-Write/Erase
Volt Intel® Wireless Flash Memory supports flash multi-partition architecture. dividing flash memory into many separate partitions, device capable reading from partition while programing erasing another partition; hence terms, Read-While-Write (RWW) Read-While-Erase (RWE). These features greatly enhance flash data storage performance. perform operation, execute Word Program command partition. While this operation being performed flash WSM, execute Read Array command another partition. perform operation, execute Block Erase command partition. While this operation being performed flash WSM, execute Read Array command another partition. Volt Intel Wireless Flash Memory does support simultaneous program erase operations. Attempting perform operations such these will result command sequence error. Only partition programming erasing while another reading.
Program Erase Voltages
Volt Intel® Wireless Flash Memory with Volt SRAM memory provides insystem program erase VPP1. factory programming, also includes low-cost, backward-compatible programming feature. also includes Enhanced Factory Programming (EFP) feature.
Factory Program Mode
standard factory programming mode uses same commands algorithm Word Program mode (40h/10h). When VPP1, program erase currents drawn through pin. Note that driven logic signal, VPP1 must remain above VPP1Min value perform in-system flash modifications. When connected power supply, device draws program erase current directly from pin. This eliminates need external switching transistor control voltage. Figure "Example Power Supply Configurations shows examples flash power supply usage various configurations.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
mode enhances programming performance during short time period typically found manufacturing processes; however, intended extended use. applied during program erase operations specified Section 11.2, "Extended Temperature Operation" page connected total tPPH hours maximum. Stressing device beyond these limits cause permanent damage.
Programming Voltage Protection (VPP)
addition flexible block locking, holding programming voltage provide absolute hardware write protection flash-device blocks. below VPPLK, program erase operations will result error displayed status register SR.3 (set
Figure Example Power Supply Configurations
System supply supply
System supply Prot# (logic signal)
fast programming Absolute write protection with VPPLK System supply (Note supply
Low-voltage programming Absolute write protection logic signal
System supply
voltage fast programming
Low-voltage programming
NOTE: supply sink adequate current, appropriately valued resistor used.
Enhanced Factory Programming (EFP)
substantially improves device programming performance number enhancements conventional 12-volt word program algorithm. EFP's more efficient algorithm eliminates traditional overhead delays conventional word program mode both host programming system flash device. Changes flowchart internal routine were developed because today's beat-rate-sensitive manufacturing environments; balance between programming speed cycling performance struck. After single command sequence, host programmer cycles write data words followed status checks determine when next data word ready accepted. This modification essentially cuts write cycles half. Following each internal program pulse, automatically increments device's address next physical location. Now, programming equipment sequentially stream program data throughout entire block without having setup present each address. combination, these enhancements reduce much host programmer overhead, enabling more data streaming approach device programming. Additionally, speeds programming performing internal code verification. With this, PROM programmers rely device verify that it's been programmed properly. From device side, streamlines internal overhead eliminating delays previously associated switch voltages between programming verify levels each memory-word location.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
consists four phases: setup, program, verify exit. Refer Figure "Enhanced Factory Program Flowchart" page detailed graphical representation implement EFP.
5.3.1
Requirements Considerations
requirements:
Ambient temperature: within specified operating range within specified VPP2 range Target block unlocked
considerations: Block cycling below erase cycles(1) supported(2) programs block time cannot suspended
Recommended optimum performance. Some degradation performance occur this limit exceeded, internal algorithm will continue work properly. Code data cannot read from another partition during EFP.
5.3.2
Setup Phase
After receiving Setup (30h) Confirm (D0h) command sequence, device SR.7 transitions from indicating that busy with algorithm startup. delay before checking SR.7 required allow time perform setups checks (VPP level block lock status). error detected, status register bits SR.4, SR.3 and/or SR.1 operation terminates.
5.3.3
Program Phase
After setup completion, host programming system must check SR.0 determine "data-stream ready" status (SR.0=0). Each subsequent write after this program-data write flash array. Each cell within memory word programmed will receive pulse; additional pulses, required, occur verify phase. SR.0=1 indicates that busy applying program pulse. host programmer must poll device's status register "program done" state after each data-stream write. SR.0=0 indicates that appropriate cell(s) within accessed memory location have received their single program pulse, that device ready next word. Although host check full status errors time, only necessary block basis, after exit. Addresses must remain within target block. Supplying address outside target block immediately terminates program phase; then enters verify phase.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
address either hold constant increment. device compares incoming address that stored from setup phase (WA0); they match, programs data word next sequential memory location. they differ, jumps address location. program phase concludes when host programming system writes different block address; data supplied must FFFFh. Upon program phase completion, device enters verify phase.
5.3.4
Verify Phase
high percentage flash bits program first pulse. However, those cells that completely program their first attempt, internal verification identifies them applies additional pulses required. verify phase identical flow that program phase, except that instead programming incoming data, compares verify-stream data that which previously programmed into block. data compares correctly, host programmer proceeds next word. not, host waits while applies additional pulse(s). host programmer must reset initial verify-word address same starting location supplied during program phase. then reissues each data word same order during program phase. Like programming, host write each subsequent data word increment through block addresses. verification phase concludes when interfacing programmer writes different block address; data supplied must FFFFh. Upon verify phase completion, device enters exit phase.
5.3.5
Exit Phase
SR.7=1 indicates that device returned normal operating conditions. full status check should performed this time ensure entire block programmed successfully. After exit, valid command issued.
Write Protection (VPP VPPLK)
voltage below lockout threshold, word programming prohibited. ensure proper word program operation, must valid ranges. determine program status, poll status register analyze bits. When VPP1, program currents drawn through supply. driven logic signal, VPP1 must remain above VPP1 minimum value order program erase mode.
Flash Erase Mode
Block Erase
Flash erasing performed block-by-block basis; therefore, only block erased given time. Once block erased, bits within that block will read logic level (1).
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
erase block, execute Block Erase command. determine status block erase, poll status register analyze bits. device standby mode during erase operation, device will continue erase until operation complete; then will enter standby mode. Refer Figure "Block Erase Flowchart" page detailed flow implement block erase operation.
Erase Protection (VPP VPPLK)
voltage below lockout threshold voltage, block erasure prohibited. ensure proper block erase operation, must valid levels. determine block erase status, poll status register analyze bits. When VPP1, erase currents drawn through supply. driven logic signal, VPP1 must remain above VPP1 minimum value order erase block.
Flash Suspend/Resume Modes
Program/Erase Suspend
suspend program erase, execute suspend command. Suspend halts in-progress word programming block erase operation. Suspend command written device address, partition being addressed remains previous command state. Suspend command allows data accessed from memory location other than those suspended. program operation suspended allow read. erase operation suspended allow word programming device reads within except suspended block. program operation nested within erase suspend suspended read flash device. Once program/erase process starts, suspend only occur certain points program/erase algorithm. Erase cannot resume until program operations initiated during erase suspend complete. device read functions permitted during suspend. During suspend, must remain valid program level must change. Also, minimum time required between issuing Program Erase command then issuing Suspend command.
Program/Erase Resume
Resume command (D0H) instructs continue programming/erasing automatically clears status register bits SR.2 SR.6) SR.7. Resume command written partition. status register error bits set, status register cleared before issuing next instruction. RST# must remain VIH. Figure "Program Suspend/Resume Flowchart" page Figure "Erase Suspend/Resume Flowchart" page suspended partition placed read array, read status register, read identifier (ID), read query mode during suspend, device will remain that mode output data corresponding that mode after program erase operation resumed. After resuming suspend operation,
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
always issue Read Mode command appropriate read operation. read status after resuming suspended operation, issue Read Status Register command (70H) return suspended partition status mode.
Flash Security Modes
Volt Intel® Wireless Flash Memory with Volt offers both hardware software security features protect flash data. software security feature used executing Lock Block command. hardware security feature used executing Lock-Down Block command asserting signals. details data security, refer Section 5.4, "Write Protection (VPP VPPLK)" page Section 6.2, "Erase Protection (VPP VPPLK)" page Refer Figure "Block Locking State Diagram state diagram flash security features. Also Figure "Locking Operations Flowchart" page
Figure Block Locking State Diagram
Power-up Reset
Block Status unlocked locked; default invalid locked down unlocked locked unlocked locked
(001) (101) (101)
Initial Lock-Down Assert (011)
Block Locked
Notes: write protect signal. Lock-down status. Lock status. Unlock (000) Unlock (110)
Block LockedDown
Unassert (111)
Lock (101) Lock (001)
Block Unlocked
(100)
Initial Lock-Down Assert (011)
NOTES: notation (X,Y,Z) denotes locking state block, current locking state block defined state bits block-lock status DQ1-0. Solid line indicates asserted (low). Dashed line indicates unasserted (high).
Block Lock
blocks default locked (states [001] [101]) upon power-up reset. Locked blocks fully protected from alteration. Attempted program erase operations locked block will return error status register SR.1. locked block's status changed unlocked lock-down using appropriate software commands. Writing Lock Block command sequence lock unlocked block.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Block Unlock
Unlocked blocks (states [000], [100], [110]) programmed erased. unlocked blocks return locked when device reset powered down. unlocked block locked locked-down using appropriate software commands. it's locked-down, locked block unlocked writing Unlock Block command sequence.
Lock-Down Block
Locked-down blocks (state [011]) protected from program erase operations, unlike locked blocks, software commands alone cannot change their protection status. locked-down block only unlocked when high. When low, locked-down blocks revert locked. locked unlocked block locked-down writing Lock-Down Block command sequence. Locked-down blocks revert locked state device reset power-down.
Block Lock Operations during Erase Suspend
Block lock configurations performed during erase suspend using standard locking command sequences unlock, lock, lock-down block. Useful when another block requires immediate updating. change block locking during erase operation, first write Erase Suspend command. After checking SR.6 determine that erase operation suspended, write desired lock command sequence block; lock status will changed. After completing lock, unlock, read, program operations, resume erase operation with Erase Resume command (D0h). block locked locked-down during suspended erase same block, locking status bits will change immediately. when resumed, erase operation will complete. Locking operations cannot occur during program suspend. Appendix "Flash Write State Machine (WSM)" shows valid commands during erase suspend.
Lock-Down Control
allows block lock-down overridden. Table defines device write protection methodology. controls lock-down function. VIL(0) protects locked-down blocks [011] from program, erase, lock status changes. When VIH(1), locked-down blocks revert locked [111]. software command then individually unlock block [110] erase program. These blocks then re-locked [111] while remains high. When returns low, previously locked-down blocks revert lock-down state [011] regardless changes made while high. Device reset power-down resets blocks locked state [101] [001].
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Table Write Protection Truth Table
VPPLK >VPPLK RST# Write Protection Reset mode, device Inaccessible Program Erase Prohibited Lock-down Blocks Locked Lock-down Blocks Unlockable
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Flash Protection Register
Volt Intel® Wireless Flash Memory includes 128-bit protection register. This protection register used increase system security and/or identification purposes. protection register value match flash component system's ASIC prevent device substitution. lower 64-bit segments within protection register programmed Intel with unique number each flash device. upper 64-bit segments within protection register left customer program. Once programmed, customer segment locked prevent further reprogramming. protection register shares some same internal flash resources parameter partition. Therefore, read-while-write only allowed between protection register main partitions. Table describes operation allowed using read-while-write/erase with protection register.
Table Simultaneous Operations Allowed with Protection Register
Protection Register Parameter Partition Array Data Conditional- Notes Main Partition Notes While programming erasing main partition, protection register read from other partition. Reading parameter partition data allowed protection register being read from addresses within parameter partition. While programming erasing main partition, read operations allowed parameter partition. Accessing protection registers from parameter partition addresses allowed. While programming erasing main partition, read operations allowed parameter partition. Accessing protection registers partition that different from being programed/erased, also different from parameter partition, allowed. While programming protection register, reads only allowed other main partitions. Access parameter partition allowed. This because programming protection register only occur parameter partition, will exist status mode. While programming erasing parameter partition, reads protection registers allowed partition. Reads other main partitions supported.
Read
Write/Erase
Conditional- Notes
Read
Write/Erase
Read
Read
Write/Erase
Write
Access Allowed
Read
Access Allowed
Write/Erase
Read
Protection Register Read
Writing Read Identifier command allows protection register data read bits time from addresses shown Table "Device Identification Codes" page plane, containing protection registers, appears over partition addresses corresponding partition address supplied with command. Writing Read Array command returns device read array mode.
Program Protection Register
Protection Program command should issued only bottom partition followed data programed specified location. programs 64-bit user protection register bits time. Table "Device Identification Codes" page Table "Protection Register
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Addressing" page show allowable addresses. also Figure "Protection Register Programming Flowchart" page Issuing Protection Program command outside register's address space results status register error (SR.4 Table Protection Register Addressing
Word LOCK Both Intel Intel Intel Intel Customer Customer Customer Customer Offset PBA+000080h PBA+000081h PBA+000082h PBA+000083h PBA+000084h PBA+000085h PBA+000086h PBA+000087h PBA+000088h Word LOCK
NOTE: Addresses A17-A8 should zero. AMAX-A18 partition base address (PBA).
Protection Register Lock
protection register's user-programmable segment lockable programming PR-LOCK register bits using Protection Program command (Figure 11). PR-LOCK register programmed Intel factory protect unique device number. PR-LOCK register programmed user lock 64-bit user register. This using Protection Program command program "FFFDh" into PR-LOCK register After PR-LOCK register bits have been programmed, further changes made protection register's stored values. Protection Program commands written locked section result status register error (program error SR.4 lock error SR.1 Once locked, protection register states reversible.
Figure Protection Register Locking
0088h 0085h 0084h 0081h 0080h
Words bits) User Programmed Words bits) Intel Factory Programmed Word (16bits) Lock Register
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
10.0
10.1
Power Reset Considerations
Power-Up/Down Characteristics
order prevent condition that result spurious write erase operation, recommended power-up VCC, VCCQ S-VCC together. Conversely, VCC, VCCQ S-VCC must power-down together. also recommended power-up with slightly after VCC. Conversely, must powerdown with slightly before VCC. VCCQ and/or connected supply, then should attain VCCMin before applying VCCQ VPP. Device inputs should driven before supply voltage VCCMin. Power supply transitions should only occur when RST# low.
10.2
Power Supply Decoupling
When device accessed, many internal conditions change. Circuits enabled charge pumps voltages switched. this internal activity produces transient signals. magnitude these transient signals depends device system capacitive inductive loading. minimize effect these transient signals, ceramic decoupling capacitor required across each VCC, VCCQ, VPP, S-VCC system ground. Capacitors should also placed close possible package balls.
10.3
Flash Reset Characteristics
holding flash device reset during power-up/down transitions, invalid conditions masked. flash device enters reset mode when RST# driven low. reset mode, internal flash circuitry turned outputs placed high-impedance state. After return from reset, certain amount time required before flash device capable performing normal operations. Upon return from reset, flash device defaults page mode. RST# driven during program erase operation, operation will aborted memory contents aborted block address longer valid. Figure "Reset Operations Waveforms" page detailed information regarding reset timings.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
11.0
11.1
Electrical Specifications
Absolute Maximum Ratings
Parameter Temperature under Bias Storage Temperature Voltage Signals (except VCC, VCCQ, S-VCC) Voltage Voltage VCCQ S-VCC Voltage Output Short Circuit Current 1,2,3 Note Maximum Rating +125 -0.5 +3.80 -0.2 -0.2 +2.40 -0.2 +3.36
NOTES: specified voltages with respect VSS. Minimum voltage -0.5 input/output signals -0.2 supplies. During transitions, this level undershoot -2.0 periods which, during transitions, overshoot +2.0 periods Maximum voltage overshoot +14.0 periods program voltage normally VPP1. VPP2 1000 cycles main blocks 2500 cycles parameter blocks during program/erase. Output shorted more than second. more than output shorted time.
NOTICE: This datasheet contains preliminary information products production. Specifications subject change without notice. Verify with your local Intel Sales office that have latest datasheet before finalizing design.
Warning:
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
11.2
Extended Temperature Operation
Symbol VCCQ, S-VCC VPP1 VPP2 tPPH Block Erase Cycles Parameter Operating Temperature Supply Voltage Flash SRAM Supply Voltages Voltage Supply (Logic Level) Factory Programming Maximum Hours Main Parameter Blocks Main Blocks Parameter Blocks VPP2 VPP2 VPP2 100,000 1000 2500 Cycles Note 1.70 2.20 0.90 11.4 1.90 3.30 1.90 12.6 Hours Unit
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
NOTES: normal operation, program voltage VPP1. connected 11.4 V-12.6 1000 cycles main blocks extended temperatures 2500 cycles extended temperature parameter blocks. VCCQ S-VCC must tied together, except when Data Retention Mode.
11.3
Characteristics
Devic Flash/ SRAM Flash/ SRAM
Parameter Input Load Current Output Leakage Current
Note
Unit
Test Condition VCCMax VCCQ VCCQMax S-VCC S-VCCMax Inputs VCCQ VCCMax
DQ15-0, WAIT
Flash ICCS Standby Current 4-Mbit SRAM 8-Mbit SRAM 4-Mbit SRAM 8-Mbit SRAM 4-Mbit SRAM 8-Mbit SRAM Flash
VCCQ VCCQMax RST# =VCC S-VCC S-VCCMax S-CS1# S-VCC S-CS2 S-VCC S-VSS Inputs S-VCC S-VSS S-CS1# S-SC2 S-WE# Inputs Cycle time 100% duty S-CS1# S-SC2 Inputs 4-Word Read VCCMax -Word Burst
Operating Power Supply Current (cycle time
ICC2
Operating Power Supply Current (min cycle time)
Asynchronous Page Mode Read ICCR Average Read Current Synchronous
Flash
8-Word Burst Inputs
Continuous Burst VPP1 VPP2 VPP1 VPP2 VCCQ
ICCW
Program Current
Flash
ICCE ICCWS ICCES
Block Erase Current Program Suspend Current Erase Suspend Current
Flash Flash Flash
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Parameter Standby Current Program Suspend Current Erase Suspend Current Read Current Program Current
Devic
Note
Unit
Test Condition
IPPS (IPPWS, IPPES) IPPR IPPW
Flash
VPP1
Flash Flash
0.05 0.05
0.10
VPP1 VPP2
0.10 VCCQ
IPPE
Erase Current Input Voltage Input High Voltage
Flash Flash SRAM Flash SRAM Flash SRAM
VCCQ
VPP1 VPP2
VCCMin VCCQ VCCQMin VCCMin 0.90 VCCQ VCCQMin -100
Output Voltage
VPPLK VLKO VLKOQ
Output High Voltage Lock-Out Voltage Lock Voltage VCCQ Lock-Out Voltage
Flash SRAM Flash Flash Flash
VCCQ
NOTES: currents unless noted. Typical values typical VCC, Automatic Power Savings (APS) reduces ICCR approximately standby levels static operation. burst wrap (CR.3) determines whether 8-word burst accesses wrap within burst-length boundary, whether they cross word-length boundaries perform linear accesses. no-wrap mode (CR.3 device operates similar continuous linear burst mode, consumes less power. Sampled, 100% tested. read program current summation read program currents. read erase current summation read block erase currents. ICCES specified with device deselected. device read while erase suspend, current draw ICCES ICCR. Erase program operations inhibited when VPPLK guaranteed outside valid VPP1 VPP2 ranges. undershoot -0.4 overshoot VCCQ durations less. Test Conditions
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Input/Output Reference Waveform
VCCQ Input
NOTES: test inputs driven VCCQ Logic Logic "0." Input timing begins, output timing ends, VCCQ/2. Input rise fall times (10% 90%) Worst case speed conditions when VCCMin. Timing conditions apply both flash SRAM.
VCCQ/2
Test Points
VCCQ/2
Output
Figure Transient Equivalent Testing Load Circuit
VCCQ
Device Under Test
NOTES: table component values. Test configuration component value worst case speed conditions. includes capacitance. Test Configuration VCCQMin Standard Test (pF)
11.4
Discrete Capacitance (32-Mbit Package)
+25°C,
COUT Parameter(1) Input Capacitance Output Capacitance Input Capacitance Unit Condition VOUT
NOTE: Sampled, 100% tested.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
11.5
Stacked Capacitance (32/4 64/8 Stacked-CSP Package)
+25°C,
COUT Parameter(1) Input Capacitance Output Capacitance Input Capacitance Unit Condition VOUT
NOTE: Sampled, 100% tested.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
12.0
12.1
Flash Characteristics
Flash Read Operations
Speed Unit Note
R101 R102 R103 R104 R105 R106 R108 R200 R201 R202 R203 R301 R302 R303 R304 R305 R306 R307 R308 R309 R310
tAVAV tAVQV tELQV tGLQV tPHQV tGLQX tEHQZ tGHQZ tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA fCLK tCLK tCH/L tCHCL tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTL/
Parameter (1,2) Read Cycle Time Address Output Delay Output Delay Output Delay RST# High Output Delay Output Low-Z High Output High-Z High Output High-Z CE#, (OE#) High Output Low-Z Address Setup ADV# High ADV# High ADV# Output Delay ADV# Pulse Width ADV# Pulse Width High Address Hold from ADV# High Page Address Access Time Frequency Period High Time Fall Rise Time Address Valid Setup ADV# Setup Setup Output Delay Output Hold from Address Hold from WAIT Asserted WAIT Active (OE#) High WAIT High-Z Pulse Width High
tELTL tEHTZ tEHEL
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
NOTES: Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. specifications assume data voltage less than equal VCCQ when read operation initiated. tAVAV 128-Mbit device. Address hold synchronous burst-mode defined tCHAX tVHAX, whichever timing specification satisfied first. delayed tELQV- tGLQV after falling edge without impact tELQV. Sampled, 100% tested. Applies only subsequent synchronous reads.
Figure Single Word Asynchronous Read Waveform
Address
Valid Address
Data [D/Q]
High
Valid Output
RST#
Generic_Async_Rd
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Single Word Latched Asynchronous Read Waveform
AMAX-2
Valid Address
Valid Address
A1-0
R101 R105 R106
Valid Address
Valid Address
ADV#
R104 R103
R102
Data [D/Q]
High
Valid Output
RST#
Generic_Latch_Async_Rd
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Page Mode Read Waveform
AMAX-2
Valid Address
A1-0
R101 R105 R106
Valid Address
Valid Address
Valid Address
Valid Address
ADV#
R104 R103
R102
R108
Data [D/Q]
High
Valid Output
Valid Output
Valid Output
Valid Output
RST#
Generic_Pg_Rd
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Single Word Burst Read Waveform
Note R301 R306
Address
Valid Address
R101 R105 R106 R302
ADV#
R104 R103
R102
R303
R308 R309 Note R304 R305
Valid Output High
WAIT
High
Data [D/Q]
High
RST#
Generic_1W_Sync_Rd
NOTES: Section 4.2.2, "First Latency Count (LC2-0)" page describes insert clock cycles during initial access. WAIT (shown active low) configured assert either during data cycle before valid data.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Word Burst Read Waveform
R301 R306 Note
Address
Valid Address
R101 R105 R106 R302
ADV#
R104 R103 R310
R102
R303
R308 R307 R309 Note R304 R305
Valid Output Valid Output Valid Output Valid Output High High
WAIT
High
Data [D/Q]
High
RST#
NOTES: Section 4.2.2, "First Latency Count (LC2-0)" page describes insert clock cycles during initial access. WAIT (shown active low) configured assert either during data cycle before valid data.
Figure Clock Input Waveform
R201
R202 R203
CLKINPUT.WMF
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure WAIT Signal Synchronous Non-Read-Array Operation Waveform
Note R301 R306
Address
Valid Address
R101 R105 R106 R302
ADV#
R104 R103
R102
R303
R308 R309
Note
High
WAIT
High
R304
R305
Valid Output
Data [D/Q]
High
RST#
NOTES: WAIT signal "asserted" state. WAIT shown active low.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure WAIT Signal Asynchronous Page-Mode Read Operation Waveform
AMAX-2
Valid Address
A1-0
R101 R105 R106
Valid Address
Valid Address
Valid Address
Valid Address
ADV#
R104 R103 R107
R102
WAIT
High Valid Output Valid Output Valid Output Valid Output High
Note
R108
High
Data [D/Q]
RST#
NOTES: WAIT signal "asserted" state. WAIT shown active low.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure WAIT Signal Asynchronous Single-Word Read Operation Waveform
Address
Valid Address
High High
WAIT
Note
Data [D/Q]
High
Valid Output
RST#
NOTES: WAIT signal "asserted" state. WAIT shown active low.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
12.2
Flash Write Operations
Speed tAVQV tAVQV Unit Note Parameter (1,2)
tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWHWL (tEHEL) tVPWH (tVPEH) tQVVL tQVBL tBHWH (tBHEH) tWHGL (tEHGL) tWHQV
RST# High Recovery (CE#) (WE#) Setup (CE#) (CE#) Write Pulse Width Data Setup (CE#) High Address Setup (CE#) High (WE#) Hold from (CE#) High Data Hold from (CE#) High Address Hold from (CE#) High (CE#) Pulse Width High Setup (CE#) High Hold from Valid Status Register Data Hold from Valid Status Register Data Setup (CE#) High Write Recovery before Read High Valid Data
NOTES: Write timing characteristics during erase suspend same during write-only operations. write operation terminated with either WE#. Sampled, 100% tested. Write pulse width (tWLWH tELEH) defined from (whichever occurs last) high (whichever occurs first); hence, tWLWH tELEH tWLEH tELWH. Write pulse width high (tWHWL tEHEL) defined from high (whichever first) (whichever last). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. System designers should take this into account insert software No-Op instruction delay first read after issuing command. commands other than resume commands. should held VPP1 VPP2 until block erase program success determined.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Write Waveform
Note Note
Valid Address
Note
Valid Address
Note
Note
Valid Address
Address
ADV#
(WE#) [E(W)]
Note
(CE#) [W(E)]
Note
Data [D/Q]
Data Data
Valid Data
RST#
VPP1/2
VPPLK
NOTE: power-up standby. Write Program Erase Setup command. Write valid address data (for program) Erase Confirm command. Automated program/erase delay. Read status register data (SRD) determine program/erase operation completion. must driven active (low) must de-asserted (high) read operations.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
12.3
Flash Program Erase Operations
F-VPP1 Symbol tWHQV1/ tEHQV1 tBWPB Program Time tBWMB tBWPB Mode tBWMB 32-KW Main 4-KW Parameter Block 32-KW Main Program Suspend Erase Suspend Setup Program Verify Transition Verify 1,2,3,4 1,2,3,4 1,2,3,4 1,3,4 1,3,4 1,3,4 1,2,3,4, 1,2,3,4 0.12 0.25 Parameter 1-Word Word Enhanced Factory Programming Mode 4-KW Parameter Block 32-KW Main 4-KW Parameter 1,2,3,4 1,2,3,4, 0.24 0.015 Notes 1,2,3,4 1,3,4 1,2,3,4 0.05 0.23 F-VPP2 Unit 0.03 0.07
Extended Temperatures Operation
Erase Time tWHQV2/ tEHQV2 tWHRH1/ tEHRH1 tWHRH2/ tEHRH2 tEFP-SETUP Latency tEFP-TRAN tEFP-VERIFY
Suspend Latency
NOTES: Typical values measured nominal voltages. Excludes external system-level overhead. These performance numbers valid speed versions. Sampled, 100% tested. Exact results vary based system overhead.
12.4
Reset Operations
Symbol tPLPH tPLRH tVCCPH Parameter RST# Reset during Read RST# Reset during Block Erase RST# Reset during Program Power Valid RST# High Note Unit
NOTES: These specifications valid product versions (packages speeds). device reset tPLPH <tPLPHMin, this guaranteed. applicable RST# tied VCC. Sampled, 100% tested. RST# tied supply, device ready until "P3"µs after >=VCCMin.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
RST# tied supply/signal with VCCQ voltage levels, RST# input voltage must exceed until after >=VCCMin.
Figure Reset Operations Waveforms
Reset during read mode
RST#
Reset during program block erase
Abort Complete
RST#
Reset during program block erase
Abort Complete
RST#
Power-up RST# high
RESET.WMF
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
13.0 13.1
SRAM Characteristics
SRAM Read Operation
Density Parameter1 S-VCC Speed Note tCO1, tCO2 tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tBLZ tBHZ Read Cycle Time Address Output Delay S-CS1#, S-CS2 Output Delay S-OE# Output Delay S-UB#, S-LB# Output Delay S-CS1#, S-CS2 Output Low-Z S-OE# Output Low-Z S-CS1#, S-CS2 Output High-Z S-OE# Output High-Z Output Hold from Address, S-CS1#, S-CS2, S-OE# Change, Whichever Occurs First S-UB#, S-LB# Output Low-Z S-UB#, S-LB# Output High-Z Mbit Unit
NOTE: Figure Waveform: SRAM Read Operation" page Sampled, 100% tested. given temperature voltage condition, (Max) less than (Max) given device from device-to-device interconnection. Timings tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Waveform: SRAM Read Operation
Standby Device Address Selection Address Stable Data Valid
ADDRESSES
CS1# (E1) (E2)
High Valid Output High
DATA (D/Q)
UB#,
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
13.2
SRAM Write Operation
Density Parameter1 S-VCC Speed Note Mbit Unit
Write Cycle Time Address Setup S-WE# (S-CS1#) S-UB#, S-LB# Going S-WE# (S-CS1#) Pulse Width Data Write Time Overlap Address Setup S-WE# (S-CS1#) Going High S-SC1# (S-WE#) Setup S-WE# (S-CS1#) Going High S-SC2 Going Data Hold Time from S-WE# (S-CS1#) High Write Recovery S-UB#, S-LB# Setup S-WE# (S-CS1#) Going High
NOTES: Figure Waveform: SRAM Write Operation" page write occurs during overlap (tWP) S-CS1# S-WE#. write begins when S-CS1# goes S-WE# goes with asserting S-UB# S-LB# operation. S-UB# S-LB# must tied together restrict mode. write ends earliest transition when S-CS1# goes high S-WE# goes high. measured from beginning write write. measured from S-CS1# going write. measured from address valid beginning write. measured from write address change; applied case write ends S-CS1# S-WE# going high.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Waveform: SRAM Write Operation
Device Address Selection Address Stable
Standby
ADDRESSES
CS1# (E1) (E2)
High High
DATA (D/Q)
Data
UB#,
13.3
tSDR tRDR
SRAM Data Retention Operation
Parameter S-VCC Data Retention Data Retention Current 8-Mbit Data Retention Setup Time Recovery Time 4/8Mbit 4/8Mbit Device 4/8Mbit 4-Mbit Note Unit Test Conditions S-CS1# S-VCC S-VCC S-CS1# S-VCC Data Retention Waveform
NOTES: Typical values nominal S-VCC, S-CS1# S-VCC S-CS2 S-VCC (S-CS1# controlled) S-CS2 (S-CS2 controlled).
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure SRAM Data Retention Waveform
tSDR
S-CS1# controlled
S-VCC VIHMAX S-CS1# (E1) VIHMIN S-VSS
S-CS1#
Data Retention Mode
tRDR
S-CS2 controlled
S-VCC VIHMIN S-CS2 (E2) VILMAX S-VSS
S-CS2
tSDR
Data Retention Mode
tRDR
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
14.0
Ordering Information
Figure Component Ordering Breakdown
Package Designator, Extended Temperature (-25 0.75 Stacked 0.75 µBGA* Access Speed Parameter Partition Parameter Device Bottom Parameter Device
Product line designator Intel® Flash products
Flash Density (32-Mbit) (64-Mbit) (128-Mbit)
Product Family Volt Intel® Wireless Flash Memory with Volt SRAM 1.70 1.90 VCCQ 2.20 3.30
SRAM Density Stacked-CSP Products Only (4-Mbit) (8-Mbit)
Table Valid Component Combinations
Stacked-CSP RD28F3204W30T70 RD28F3204W30B70 RD28F3204W30T85 RD28F3204W30B85 RD28F6408W30T70 RD28F6408W30B70 RD28F6408W30T85 RD28F6408W30B85 GE28F320W30T70 GE28F320W30B70 GE28F320W30T85 GE28F320W30B85 GT28F640W30T70 GT28F640W30B70 GT28F640W30T85 GT28F640W30B85 µBGA*
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Appendix Flash Write State Machine (WSM)
This table shows command state transitions based incoming commands. Only partition actively programming erasing time. Each partition stays last output state (Array, ID/CFI Status) until command changes next state does depend partition's output state. Figure Write State Machine Next State Table (Sheet
Chip Next State after Command Input Current Chip
Read Array
Program Setup
(4,5)
Erase Setup
(4,5)
Write State Machine (WSM) Next State Table
State
Enhanced Confirm, Factory Resume, Setup
Confirm (D0H)
Program/ Erase Suspend (B0H)
Read Status
Clear Status Register (50H)
Read ID/Query
(FFH) Ready Lock/CR Setup Setup Busy Setup Program Busy Suspend Setup Busy Erase Suspend Setup Program Erase Suspend Busy Suspend Lock/CR Setup Erase Suspend Enhanced Factory Program Setup Busy Verify Erase Suspend Ready
(10H/40H) Program Setup
(20H) Erase Setup
(30H) Setup
(70H) Ready
(90H, 98H)
Ready (Lock Error)
Ready Busy
Ready (Lock Error)
Program Busy Program Busy Program Suspend Ready (Error) Erase Busy Erase Susp Setup Erase Suspend Erase Busy Busy Erase Busy Erase Susp Susp Program Busy Program Suspend Ready (Error) Erase Busy Erase Suspend
Program Erase Suspend Busy Program Erase Suspend Busy Program Suspend Erase Suspend Erase Suspend (Lock Error) Ready (Error) Erase Susp Busy Erase Susp Busy Busy
Susp Erase Susp
Program Erase Suspend Busy
Program Suspend Erase Suspend Erase Suspend (Lock Error) Ready (Error)
Verify Busy
Output Next State after Command Input
Output Next State Table
Setup, Erase Setup, Setup, Erase Susp Setup, Setup, Busy, Verify Busy Lock/CR Setup, Lock/CR Setup Erase Susp Busy Ready, Busy, Suspend, Erase Busy, Erase Suspend, Erase Susp Busy, Susp Erase Susp
Status
Status Status
Array
Status
Output does change
Status
Output does change
ID/Query
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Write State Machine Next State Table (Sheet
ock, eady uspe uspe uspe Suspend nhan rify Busy
firm
Write State Machine (WSM) Next State Table
firm
rite firm
nhanced Fact
Ille
eady
eady
eady
eady
eady uspend eady eady
rify eady
rify
rify
eady
Output Next State Table
Busy, rify eady, usy, uspend,
chang
NOTES: output state shows type data that appears outputs partition address same command address. partition placed Read Array, Read Status Read ID/CFI, depending command issued. Each partition stays last output state (Array, ID/CFI Status) until command changes next state does depend partition's output state. example, partition #1's output state Read Array partition #4's output state Read Status, every read from partition (without issuing command) outputs Status register. Illegal commands those defined command set. partitions default Read Array mode power-up. Read Array command issued busy partition results undermined data when partition address read. Both cycles 2-cycle commands should issued same partition address. they issued different partitions, second write determines active partition. Both partitions will output status information when read. active, both cycles 2-cycle command ignored. This differs from previous Intel devices. Clear Status command clears status register error bits except when running (Pgm Busy, Erase Busy, Busy Erase Suspend, Busy, modes) suspended (Erase Suspend, Suspend, Suspend Erase Suspend). writes allowed only when status register SR.0 busy Block Address address Confirm command. other commands treated data. "current state" that WSM, partition. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform operation then move Ready State.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Appendix Flowcharts
Figure Programming Flowchart
WORD PROGRAM PROCEDURE
Start
Program Word
Command Operation Write Program Setup Data
Comments Data Addr Location program (WA) Data Data program (WD) Addr Location program (WA) Status register data. Toggle update Status register Check SR.7 ready busy
Write 40h, Word Address
Data/ Confirm
Write
Write Data Word Address Read Read Status Register
Suspend Program Loop Suspend Program
Standby
SR.7
Repeat subsequent programming operations. Full Status register check done after each program after sequence program operations. Write after last operation enter read array mode.
Full Status Check desired) Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Command Operation Standby SR.3
Comments Check SR.3 error Check SR.4 Data program error Check SR.1 Attempted program locked block Program aborted
Range Error Standby Program Error
SR.4
Standby
SR.1
Device Protect Error
SR.3 MUST cleared before Write State Machine will allow further program attempts Only Clear Staus Register command clears SR.1, error detected, clear status register before attempting program retry other error recovery.
PGM_WRD.WMF
Program Successful
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Program Suspend/Resume Flowchart
PROGRAM SUSPEND RESUME PROCEDURE
Start
Program Suspend
Command Operation Write Program Suspend Read Status
Comments Data Addr Block suspend (BA) Data Addr Same partition Status register data Toggle update Status register Addr Suspended block (BA) Check SR.7 ready busy Check SR.2 Program suspended Program completed
Write Address
Read Status
Write
Write Same Partition Read Status Register Read
SR.7
Standby
SR.2
Read Array
Program Completed
Standby
Write
Write Susp Partition Read Read Array Data
Read Array
Data Addr Block address read (BA) Read array data from block other than being programmed
Write
Program Resume
Data Addr Suspended block (BA)
Done Reading
Program Resume
suspended partition placed Read Array mode: Write
Read Array
Read Status
Return partition Status mode: Data Addr Same partition
Write Address Program Resumed
Read Status
Write Pgm'd Partition Read Array Data
Write Same Partition
PGM_SUS.WMF
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Enhanced Factory Program Flowchart
ENHANCED FACTORY PROGRAMMING PROCEDURE Setup
Start
Program
Read Status Register
Verify
Read Status Register
Exit
Read Status Register
Unlock Block
SR.0=1=N
Data Stream Ready? SR.0 Write Data Address
SR.0=1=N
Verify Stream Ready? SR.0 Write Data Address
SR.7=0=N
Exited? SR.7 Full Status Check Procedure
Write Address
Write Address SR.0=1=N
setup time
SR.7=0=Y
Read Status Register
Program Done? SR.0
SR.0=1=N
Read Status Register
Read Status Register
Operation Complete
Verify Done? SR.0
Setup Done? SR.7 Check Lock errors (SR.3, SR.1)
Last Data? Write FFFFh Address
Last Data? Write FFFFh Address
Exit
Setup
State Write Write Write Standby Read Unlock Block Setup Comments Unlock block Data Address State Read Standby Write (note Read
Program
Comments Status Register Data Check SR.0 Stream Ready data Ready? ready data Data Data program Address Status Register State Read Standby Write (note Read Standby (note Standby
Verify
Comments Status Register Verify Check SR.0 Stream Ready verify Ready? ready verify Data Word verify Address Status Register Verify Done? Last Data? Exit Verify Phase Check SR.0 Verify done Verify done Device automatically increments address. Data FFFFh Address within same Status Register Check SR.7 Exit finished Exited? Exit completed
Data Confirm Address Setup Time Setup Done? Refer Program Erase Operations Table.
Status Register Check SR.7 Standby ready ready SR.7 Error Check SR.3, SR.1 Standby Condition SR.3 error Check SR.1 locked block
Check SR.0 Program Program done Standby Done? Program done Standby Last Data? Device automatically increments address.
Write
Exit Data FFFFh Program Address within same Phase
Write
Exit
first Word Address programmed within target block. (Block Base Address) must remain constant throughout program phase data stream; held constant first address location, written sequence through addresses within block. Writing equal that block currently being written terminates program phase, instructs device enter verify phase. proper verification occur verify data stream must presented device same sequence that program phase data stream. Writing equal terminates verify phase, instructs device exit Bits that fully program with single pulse program phase receive additional program-pulse attempts during verify phase. device will report program failure setting SR.4=1; this check performed during full status check after been exited that block, will indicate error within entire data stream. Read Standby
Repeat subsequent operations. After exit, Full Status Check determine program error occurred. Full Status Check procedure Word Program flowchart.
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Block Erase Flowchart
BLOCK ERASE PROCEDURE
Start
Block Erase
Write Block Address
Erase Confirm
Command Comments Operation Block Data Erase Write Addr Block erased (BA) Setup Write Erase Confirm Data Addr Block erased (BA) Status register data. Toggle update Status register data Check SR.7 ready busy
Write Block Address Read Read Status Register
Suspend Erase Loop Suspend Erase
Standby
SR.7
Repeat subsequent block erasures. Full Status register check done after each block erase after sequence block erasures. Write after last operation enter read array mode.
Full Erase Status Check desired) Block Erase Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status Register Range Error Standby
Command Operation Standby Check SR.3 error
Comments
SR.3
Check SR.4,5 Both Command sequence error Check SR.5 Block erase error
SR.4,5
Command Sequence Error Block Erase Error Erase Locked Block Aborted
Standby
SR.5
SR.1
Check SR.1 Attempted erase locked block Erase aborted MUST cleared before Write State Machine will allow further erase attempts. Standby Only Clear Staus Register command clears SR.1, error detected, clear Status register before attempting erase retry other error recovery.
ERAS_BLK.WMF
Block Erase Successful
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Erase Suspend/Resume Flowchart
ERASE SUSPEND RESUME PROCEDURE
Start
Erase Suspend
Command Operation Write
Comments
Write Address
Read Status
Erase Data Suspend Addr address Read Status Data Addr Same partition Status register data. Toggle update Status register Addr Same partition Check SR.7 ready busy Check SR.6 Erase suspended Erase completed Read Array Data Program Addr Block program read Read array program data from/to block other than being erased Program Resume Data Addr address
Write
Write Same Partition Read Read Status Register Standby SR.7
Standby Erase Completed Write Read Write Write
SR.6
Read
Read Program?
Program
Read Array Data
Program Loop
Done?
Erase Resume Read Array
suspended partition placed Read Array mode Program Loop: Write Read Status Return partition Status mode: Data Addr Same partition
Write Address
Write Erased Partition Read Array Data
Erase Resumed
Read Status
Write Same Partition
ERAS_SUS.WMF
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Locking Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start
Lock Setup
Command Operation Write Lock Setup
Comments Data Addr Block lock/unlock/lock-down (BA) (Lock block) (Unlock block) (Lockdown block) Block lock/unlock/lock-down (BA)
Write Block Address
Lock Confirm
Write 01,D0,2Fh Block Address
Read Plane
Write
Lock, Data Unlock, Lockdown Confirm Addr Read Plane
Write Optional
Write (Optional)
Data Addr Block address offset (BA+2)
Read Block Lock Status
Read Block Lock Block Lock status data (Optional) Status Addr Block address offset (BA+2) Standby (Optional) Read Array Confirm locking change (See Block Locking State Transitions Table valid combinations.) Data Addr Block address (BA)
Locking Change?
Read Array
Write
Write Partition Address Lock Change Complete
LOCK_OP.WMF
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Figure Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Start
Program Setup
Write Addr=Prot addr
Confirm Data
Command Comments Operation Protection Data Write Program Addr First Location Program Setup Write Protection Data Data Program Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write Protect. Register Address Data Read Status Register
Read
Standby
SR.7
Protection Program operations addresses must within protection register address space. Addresses outside this space will return error. Repeat subsequent programming operations.
Full Status Check desired) Program Complete
Full Status register check done after each program after sequence program operations. Write after last operation enter read array mode.
FULL STATUS CHECK PROCEDURE
Read Status Register Data Command Operation Standby SR.3, SR.4
Comments SR.1 SR.3 SR.4 Error Prot. Reg. Prog. Error Register Locked: Aborted
Range Error Standby
SR.1, SR.4
Programming Error
Standby
SR.1, SR.4
Locked-Register Program Aborted
SR.3 MUST cleared before Write State Machine will allow further program attempts. Only Clear Staus Register command clears SR.1, error detected, clear Status register before attempting program retry other error recovery.
PROTFLOW.WMF
Program Successful
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Appendix Common Flash Interface
This appendix defines data structure "database" returned Common Flash Interface (CFI) Query command. System software should parse this structure gain critical information such block size, density, x8/x16, electrical specifications. Once this information been obtained, software will know which command sets enable flash writes, block erases, otherwise control flash component. Query part overall specification multiple command control interface descriptions called Common Flash Interface, CFI.
Query Structure Output
Query database allows system software obtain information controlling flash device. This section describes device's CFI-compliant interface that allows access Query data. Query data presented lowest-order data outputs (DQ0-7) only. numerical offset value address relative maximum width supported device. this family devices, Query table device starting address 10h, which word address devices. word-wide (x16) device, first Query-structure bytes, ASCII "R," appear byte word addresses 11h. This CFI-compliant device outputs data upper bytes. device outputs ASCII byte (DQ0-7) high byte (DQ8-15). Query addresses containing more bytes information, least significant data byte presented lower address, most significant data byte presented higher address. following tables, addresses data represented hexadecimal notation, suffix been dropped. addition, since upper byte word-wide devices always "00h," leading "00" been dropped from table notation only lower byte value shown. device outputs assumed have upper byte this mode.
Table Summary Query Structure Output Function Device Mode
Device Device Addresses Offset 00010: 00011: 00012: Code ASCII Value
Table Example Query Structure Output x16- Devices
Offset 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h Word Addressing: Code 0051 0052 0059 P_ID P_ID A_IDLO A_IDHI Value PrVendor PrVendor TblAdr AltVendor Offset 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h Byte Addressing: Code Value P_ID PrVendor P_ID P_ID
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Query Structure Overview
Query command causes flash component display Common Flash Interface (CFI) Query structure "database." structure subsections address locations summarized below.
Table Query Structure
Offset 00000h 00001h
Sub-Section Name
00004-Fh 00010h 0001Bh 00027h
Block Status register Reserved query identification string System interface information Device geometry definition Primary Intel-specific Extended Query Table
Manufacturer Code Device Code Block-specific information Reserved vendor-specific information Command vendor data offset Device timing voltage information Flash device layout Vendor-defined additional information specific Primary Vendor Algorithm
NOTES: Refer Query Structure Output section offset detailed definition offset address function device width mode. Block Address beginning location (i.e., 08000h block beginning location when block size 32K-word). Offset defines which points Primary Intel-specific Extended Query Table.
Block Status Register
Block Status Register indicates whether erase operation completed successfully whether given block locked accessed flash program/erase operations. Block Erase Status (BSR.1) allows system software determine success last block erase operation. BSR.1 used just after power-up verify that supply accidentally removed during erase operation. Only issuing another operation block resets this bit. Block Status Register accessed from word address within each block.
Table Block Status Register
Offset Length Description (BA+2)h Block Lock Status Register BSR.0 Block lock status Unlocked Locked BSR.1 Block lock-down status locked down Locked down 2-7: Reserved future Add. Value BA+2 BA+2 (bit
BA+2 (bit
BA+2
(bit 2-7):
NOTE: beginning location Block Address (i.e., 008000h block (64KB block) beginning location word mode).
Preliminary
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Query Identification String
Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s).
Table Identification
Offset Length Description Query-unique ASCII string "QRY" Add. Code Value
Primary vendor command control interface code. 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command control interface code. 0000h means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
Table System Interface Information
Offset Length Description Add. Code Value 1.7V
logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out µ-sec such that typical max. buffer write time-out µ-sec
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