DESCRIPTIO 16-Pin Narrow SSOP Package (SO-8 Footprint) Sample Rat

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DESCRIPTIO 16-Pin Narrow SSOP Package (SO-8 Footprint) Sample Rat

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LTC1417 Power 14-Bit, 400ksps Sampling Converter with Serial
DESCRIPTIO
16-Pin Narrow SSOP Package (SO-8 Footprint) Sample Rate: 400ksps ±1.25LSB ±1LSB Power Dissipation: 20mW (Typ) Single Supply Operation Serial Data Output Missing Codes Over Temperature Power Shutdown: Sleep External Internal Reference Differential High Impedance Analog Input Input Range: 4.096V ±2.048V 81dB S/(N 95dB Nyquist
®1417 power, 400ksps, 14-bit converter. This versatile device operate from single supplies. onboard high performance sample-andhold, precision reference internal trimming minimize external circuitry requirements. 20mW power dissipation made even more attractive with userselectable power shutdown modes. LTC1417 converts 4.096V unipolar inputs when using supply ±2.048V bipolar inputs when using supplies. specs include ±1.25LSB INL, ±1LSB missing codes over temperature. Outstanding performance includes 81dB S/(N 95dB Nyquist input frequency 200kHz. internal clock trimmed maximum conversion time. separate convert start input data ready signal (BUSY) ease connections FIFOs, DSPs microprocessors.
registered trademarks Linear Technology Corporation.
APPLICATIO
High Speed Data Acquisition Digital Signal Processing Isolated Data Acquisition Systems Audio Telecom Processing Spectrum Instrumentation
EQUIVALE BLOCK DIAGRA
10µF LTC1417 AIN+ AIN- 14-BIT
400kHz, 14-Bit Sampling Converter Narrow 16-Lead SSOP Package Effective Bits Signal-to-(Noise Distortion) Input Frequency
SERIAL PORT
EFFECTIVE BITS
REFCOMP 10µF
4.096V BUFFER
EXTCLKIN SCLK CLKOUT DOUT
100k INPUT FREQUENCY (Hz)
VREF
2.5V REFERENCE
TIMING LOGIC
BUSY CONVST SHDN
1417 TA01
AGND
DGND
S/(N (dB)
1417 TA02
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LTC1417 ABSOLUTE
(Notes
RATI
PACKAGE/ORDER ATIO
VIEW AIN+ AIN- VREF REFCOMP AGND EXTCLKIN SCLK CLKOUT BUSY CONVST SHDN DGND DOUT
Positive Supply Voltage (VDD) Negative Supply Voltage (VSS) Bipolar Operation Only Total Supply Voltage (VDD VSS) Bipolar Operation Only Analog Input Voltage (Note Unipolar Operation 0.3V (VDD 0.3V) Bipolar Operation. (VSS 0.3) (VDD 0.3V) Digital Input Voltage (Note Unipolar Operation 0.3V Bipolar Operation.(VSS 0.3V) Digital Output Voltage Unipolar Operation (VDD 0.3V) Bipolar Operation. (VSS 0.3V) (VDD 0.3V) Power Dissipation 500mW Operating Temperature Range LTC1417AC/LTC1417C 70°C LTC1417AI/LTC1417I 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1417ACGN LTC1417CGN LTC1417AIGN LTC1417IGN PART MARKING 1417A 1417 1417AI 1417I
PACKAGE 16-LEAD (NARROW) PLASTIC SSOP
TJMAX 110°C, 95°C/W
Consult Marketing parts specified with wider operating temperature ranges.
VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Offset Error Full-Scale Error Full-Scale Tempco (Note External Reference (Note Internal Reference External Reference 2.5V (Note CONDITIONS
indicates specifications which apply over full operating temperature range, otherwise specifications 25°C. Specifications measured while using internal reference unless otherwise noted. (Notes
LTC1417
LTC1417A
UNITS Bits Bits
±0.8 0.33 ±0.7 ±1.5
±0.5 ±1.25 ±0.35 0.33
LSBRMS ppm/°C ppm/°C ppm/°C
IOUT(REF) Internal Reference, 70°C IOUT(REF) Internal Reference, 40°C 85°C IOUT(REF) External Reference
ALOG
SYMBOL PARAMETER
indicates specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS 4.75V 5.25V (Unipolar) 4.75V 5.25V, 5.25V 4.75V (Bipolar) CONVST High
4.096 ±2.048
UNITS
Analog Input Range (Note Analog Input Leakage Current
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LTC1417
ALOG
SYMBOL PARAMETER tACQ tjitter CMRR
indicates specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS Between Conversions (Sample Mode) During Conversions (Hold Mode)
Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Time Sample-and-Hold Aperture Time Jitter Analog Input Common Mode Rejection Ratio
ACCURACY indicates specifications which apply over full operating temperature range,
otherwise specifications 25°C. (Note
SYMBOL S/(N SFDR PARAMETER Signal-to-(Noise Distortion) Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth S/(N 77dB CONDITIONS 100kHz Input Signal 100kHz Input Signal, First Five Harmonics 200kHz Input Signal fIN1 97.3kHz, fIN2 104.6kHz
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance CONDITIONS IOUT IOUT 70°C IOUT 40°C 85°C 4.75V 5.25V 5.25V 4.75V 0.1mA |IOUT| 0.1mA
indicates specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
DIGITAL PUTS DIGITAL OUTPUTS
SYMBOL PARAMETER ISOURCE ISINK High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Level Output Voltage High-Z Output Leakage DOUT, CLKOUT High-Z Output Capacitance DOUT, CLKOUT Output Source Current Output Sink Current CONDITIONS 5.25V 4.75V
indicates specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
-1.5
UNITS
psRMS
(AIN+ AIN-) 4.096V (Unipolar) 2.048V (AIN+ AIN-) 2.048V (Bipolar)
UNITS
2.500 0.05 0.05
2.520
UNITS ppm/°C ppm/°C LSB/V LSB/V
2.480
UNITS
4.75V, 10µA 4.75V, 200µA 4.75V, 160µA 4.75V, 1.6mA VOUT VDD, High High (Note VOUT VOUT 4.74
0.05 0.10
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LTC1417
POWER REQUIRE
SYMBOL PARAMETER Positive Supply Voltage (Notes Negative Supply Voltage (Note Positive Supply Current Mode Sleep Mode Negative Supply Current Mode Sleep Mode Power Dissipation
indicates specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS Bipolar Only (VSS Unipolar) Unipolar, High (Note Bipolar, High (Note SHDN SHDN Bipolar, High (Note SHDN SHDN Unipolar Bipolar
PDIS
indicates specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
SYMBOL fSAMPLE(MAX) tCONV tACQ tACQ tCONV PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Acquisition Plus Conversion Time SHDN CONVST Wake-Up Time from Mode CONVST Time CONVST BUSY Delay Data Ready Before BUSY Delay Between Conversions Wait Time After BUSY Data Access Time After 25pF
CHARACTERISTICS
fSCLK fEXTCLKIN tdEXTCLKIN
Relinquish Time Time CONVST High Time Delay Time, SCLK DOUT Valid Time from Previous Data Remain Valid After SCLK Shift Clock Frequency External Conversion Clock Frequency Delay Time, CONVST External Conversion Clock Input (Note 25pF 25pF (Note
4.75 4.75
5.25 5.25
UNITS
20.0 31.5
27.5
CONDITIONS
2.25
UNITS
(Note (Notes 25pF 25pF (Note
0.05
100pF
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LTC1417
indicates specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
SYMBOL SCLK SCLK EXTCLKIN EXTCLKIN fCLKOUT PARAMETER SCLK High Time SCLK Time EXTCLKIN High Time EXTCLKIN Time Conversion Clock Output Frequency Internal Conversion Clock Mode (EXTCLKIN External Conversion Clock Mode (EXTCLKIN Driven External Conversion Clock Input) Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect ground with DGND AGND wired together (unless otherwise noted). Note When these voltages taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA without latchup driven below (ground unipolar mode) above VDD. Note When these voltages taken below they will clamped internal diodes. This product handle input currents greater than 100mA below without latchup. These pins clamped VDD. Note fSAMPLE 400kHz, unless otherwise specified. Note Linearity, offset full-scale specifications apply singleended AIN+ input with AIN- grounded. CONDITIONS (Note (Note
CHARACTERISTICS
TYPICAL PERFOR CHARACTERISTICS
Typical Curve
SIGNAL/(NOISE DISTORTION) (dB)
ERROR (LSBs) (LSBs)
-0.5
-1.0 4096 8192 OUTPUT CODE
1417
12288
0.04 0.04
UNITS
fEXTCLKIN
Note Integral nonlinearity defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Bipolar offset offset voltage measured from 0.5LSB when output code flickers between 0000 0000 0000 1111 1111 1111 Note Guaranteed design, subject test. Note Recommended operating conditions. Note falling CONVST edge starts conversion. CONVST returns high critical point during conversion create small errors. best results ensure that CONVST returns high either within 625ns after conversion start after BUSY rises. Note Typical noise code transitions. Figure histogram. Note 40ns maximum allows fSCLK 10MHz rising capture with duty cycle. fSCLK 20MHz falling capture with setup time.
25°C, unless otherwise specified) S/(N Input Frequency Amplitude
100k INPUT FREQUENCY (Hz)
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Differential Nonlinearity Output Code
-20dB
-60dB
-1.0
16384
4096
12288 8192 OUTPUT CODE
16384
1417
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LTC1417 TYPICAL PERFOR CHARACTERISTICS 25°C, unless otherwise specified)
Signal-to-Noise Ratio Input Frequency
AMPLITUDE BELOW FUNDAMENTAL)
SIGNAL-TO-NOISE RATIO (dB)
SPURIOUS FREE DYNAMIC RANGE (dB)
100k INPUT FREQUENCY (Hz)
1417
Nonaveraged, 4096 Point FFT, Input Frequency 10kHz
fSAMPLE 400kHz 10.05859375kHz SFDR -97.44dB SINAD 81.71dB
AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
-100 -120
FREQUENCY (kHz)
Power Supply Feedthrough Ripple Frequency
COMMON MODE REJECTION (dB)
CHANGE OFFSET VOTLAGE (LSB)
VRIPPLE 60mV fSAMPLE 400kHz 200kHz FEEDTHROUGH (dB) 100k RIPPLE FREQUENCY (Hz)
1417
DGND
Distortion Input Frequency
-100 -120 INPUT FREQUENCY (kHz) 1000
1417
Spurious-Free Dynamic Range Input Frequency
-100 -120 100k INPUT FREQUENCY (Hz)
1417
Nonaveraged, 4096 Point FFT, Input Frequency 200kHz
fSAMPLE 400kHz 197.949188kHz SFDR -98dB SINAD 81.1dB
Intermodulation Distortion Plot
fSAMPLE 400kHz fIN1 97.303466kHz fIN2 104.632568kHz 4.096VP-P
-100 -120
-100 -120 FREQUENCY (kHz)
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1417
FREQUENCY (kHz)
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Input Common Mode Rejection Input Frequency
INPUT FREQUENCY (kHz) 1000
1417
Input Offset Voltage Shift Source Resistance
100k INPUT SOURCE RESISTANCE
1417
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LTC1417 TYPICAL PERFOR CHARACTERISTICS 25°C, unless otherwise specified)
Supply Current Temperature (Unipolar Mode)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
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TEMPERATURE (°C)
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Supply Current Sampling Frequency (Unipolar Mode)
SUPPLY CURRENT (mA) SUPPLY CURRENT (mA)
SAMPLING FREQUENCY (kHz)
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SAMPLING FREQUENCY (kHz)
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SUPPLY CURRENT (mA)
FUNCTIONS
AIN+ (Pin Positive Analog Input. AIN- (Pin Negative Analog Input. VREF (Pin 2.50V Reference Output. Bypass AGND with 1µF. REFCOMP (Pin 4.096V Reference Output. Bypass AGND using 10µF tantalum parallel with 0.1µF ceramic. AGND (Pin Analog Ground. EXTCLKIN (Pin External Conversion Clock Input. input will enable internal conversion clock. SCLK (Pin Data Clock Input. CLKOUT (Pin Conversion Clock Output. DOUT (Pin Serial Data Output. DGND (Pin 10): Digital Ground. SHDN (Pin 11): Power Shutdown Input. selects shutdown. Shutdown mode selected mode Sleep mode. (Pin 12): Read Input. This enables output drivers. also sets shutdown mode when SHDN goes low. SHDN selects quick wake-up mode, high SHDN selects Sleep mode.
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Supply Current Temperature (Bipolar Mode)
Supply Current Temperature (Bipolar Mode)
TEMPERATURE (°C)
1417
Supply Current Sampling Frequency (Bipolar Mode)
Supply Current Sampling Frequency (Bipolar Mode)
SAMPLING FREQUENCY (kHz)
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LTC1417
FUNCTIONS
CONVST (Pin 13): Conversion Start Signal. This active signal starts conversion falling edge. BUSY (Pin 14): BUSY output shows converter status. when conversion progress. (Pin 15): Negative Supply, Bipolar Operation. Bypass AGND using 10µF tantalum parallel with 0.1µF ceramic. Analog ground unipolar operation. (Pin 16): Positive Supply. Bypass AGND with 10µF tantalum parallel with 0.1µF ceramic.
TEST CIRCUITS
Load Circuits Access Timing
DOUT DGND HI-Z DOUT DGND HI-Z
1417 TC01
FUNCTIONAL BLOCK DIAGRA
AIN+
CSAMPLE CSAMPLE AIN- VREF 2.5V ZEROING SWITCHES
14-BIT CAPACITIVE
REFCOMP (4.096V) AGND DGND
INTERNAL CLOCK SUCCESSIVE APPROXIMATION REGISTER SHIFT REGISTER CONTROL LOGIC DOUT SCLK
EXTCLKIN
SHDN
Load Circuits Output Float Delay
DOUT 30pF DOUT 30pF
HI-Z
HI-Z
1417 TC02
UNIPOLAR MODE BIPOLAR MODE)
COMP
CONVST
1417
CLKOUT BUSY
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LTC1417
APPLICATIONS INFORMATION
CONVERSION DETAILS LTC1417 uses successive approximation algorithm internal sample-and-hold circuit convert analog signal 14-bit serial output. complete with precision reference internal clock. control logic provides easy interface microprocessors DSPs (please refer Digital Interface section data format). Conversion start controlled CONVST input. start conversion, successive approximation register (SAR) reset. Once conversion cycle begun, cannot restarted. During conversion, internal differential 14-bit capacitive output sequenced from most significant (MSB) least significant (LSB). Referring Figure AIN+ AIN- inputs connected sample-and-hold capacitors (CSAMPLE) during acquire phase comparator offset nulled zeroing switches. this acquire phase, minimum delay 500ns will provide enough time sampleand-hold capacitors acquire analog signal. During convert phase, comparator zeroing switches open, placing comparator compare mode. input switches connect CSAMPLE capacitors ground, transferring differential analog input charge onto summing junction. This input charge successively compared with binary weighted charges supplied differential capacitive DAC. decisions made high speed comparator. conversion, differential output balances AIN+ AIN- input charges. contents 14-bit data word) that represent difference AIN+ AIN- output through serial DOUT. Performance measuring transition noise associated with high resolution technique where signal applied input resulting output codes collected over large number conversions. example Figure distribution output code shown input that been digitized 4096 times. distribution Gaussian code transition about 0.33LSB.
4000 3500 3000 2500
COUNTS
AIN+
SAMPLE
CSAMPLE HOLD
ZEROING SWITCHES HOLD
AIN-
SAMPLE
CSAMPLE- HOLD CDAC+
HOLD
VDAC+ CDAC- COMP
VDAC- SHIFT REGISTER
Figure Simplified Block Diagram
2000 1500 1000 CODE
1417
Figure Histogram 4096 Conversions
DYNAMIC PERFORMANCE LTC1417 excellent high speed sampling capability. (Fast Fourier Transform) test techniques used test ADC's frequency response, distortion noise performance rated throughput. applying distortion sine wave analyzing digital output using algorithm, ADC's spectral content examined frequencies beyond fundamental. Figure shows typical LTC1417 plot.
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DOUT
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LTC1417
APPLICATIONS INFORMATION
fSAMPLE 400kHz 10.05859375kHz SFDR -97.44dB SINAD 81.71dB
AMPLITUDE (dB)
-100 -120
FREQUENCY (kHz)
1417
Figure LTC1417 Nonaveraged, 4096 Point FFT, Input Frequency 10kHz
EFFECTIVE BITS
fSAMPLE 400kHz 197.949188kHz SFDR -98dB SINAD 81.1dB
AMPLITUDE (dB)
-100 -120
FREQUENCY (kHz)
1417
Figure LTC1417 Nonaveraged, 4096 Point FFT, Input Frequency 200kHz
Signal-to-Noise Ratio signal-to-noise plus distortion ratio [S/(N ratio between amplitude fundamental input frequency amplitude other frequency components output. output band limited frequencies from above below half sampling frequency. Figure shows typical spectral content with 400kHz sampling rate 200kHz input. dynamic performance excellent input frequencies beyond Nyquist limit 200kHz.
Effective Number Bits effective number bits (ENOBs) measurement resolution directly related S/(N equation: ENOB [S/(N 1.76]/6.02 where effective number bits resolution S/(N expressed maximum sampling rate 400kHz, LTC1417 maintains near ideal ENOBs Nyquist input frequency 200kHz (refer Figure
100k INPUT FREQUENCY (Hz)
1417 TA02
S/(N (dB)
Figure Effective Bits Signal/(Noise Distortion) Input Frequency
Total Harmonic Distortion Total harmonic distortion (THD) ratio harmonics input signal fundamental itself. out-of-band harmonics alias into frequency band between half sampling frequency. expressed
.Vn2 where amplitude fundamental frequency through amplitudes second through harmonics. Input Frequency shown Figure LTC1417 good distortion performance Nyquist frequency beyond. 20Log
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LTC1417
APPLICATIONS INFORMATION
AMPLITUDE BELOW FUNDAMENTAL)
-100 -120 INPUT FREQUENCY (kHz) 1000
1417
Figure Distortion Input Frequency
Intermodulation Distortion input signal consists more than spectral component, transfer function nonlinearity produce intermodulation distortion (IMD) addition THD. change sinusoidal input caused presence another sinusoidal input different frequency. pure sine waves frequencies applied input, nonlinearities transfer function create distortion products difference frequencies ±nfb, where etc. example, order terms include fb). input sine waves equal magnitude, value decibels) 2nd-order products expressed following formula:
fSAMPLE 400kHz fIN1 97.303466kHz fIN2 104.632568kHz 4.096VP-P
AMPLITUDE (dB)
-100 -120
FREQUENCY (kHz)
1417
Figure Intermodulation Distortion Plot
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20Log
Amplitude Amplitude
Peak Harmonic Spurious Noise peak harmonic spurious noise largest spectral component excluding input signal This value expressed decibels relative value full-scale input signal. Full-Power Full-Linear Bandwidth full-power bandwidth input frequency which amplitude reconstructed fundamental reduced from full-scale input signal. full-linear bandwidth input frequency which S/(N dropped 77dB (12.5 effective bits). LTC1417 been designed optimize input bandwidth, allowing undersample input signals with frequencies above converter's Nyquist Frequency. noise floor stays very high frequencies; S/(N becomes dominated distortion frequencies beyond Nyquist. DRIVING ANALOG INPUT differential analog inputs LTC1417 easy drive. inputs driven differentially singleended input (i.e., AIN- input grounded). AIN+ AIN- inputs sampled same instant. unwanted signal that common both inputs will reduced common mode rejection sampleand-hold circuit. inputs draw only small current spike while charging sample-and-hold capacitors conversion. During conversion, analog inputs draw only small leakage current. source impedance driving circuit low, then LTC1417 inputs driven directly. source impedance increases, will acquisition time (see Figure minimum acquisition time, with high source impedance, buffer amplifier must used. only requirement that amplifier driving analog input(s) must settle after small current spike before next conversion starts 500ns full throughput rate.
LTC1417
APPLICATIONS INFORMATION
ACQUISITION TIME (µs)
0.01 SOURCE RESISTANCE 100k
1417
Figure tACQ Source Resistance
Choosing Input Amplifier Choosing input amplifier easy requirements taken into consideration. First, choose amplifier that output impedance (<100) closed-loop bandwidth frequency. example, amplifier used gain closed-loop bandwidth 10MHz, then output impedance 10MHz must less than 100. second requirement that closed-loop bandwidth must greater than 10MHz ensure adequate small-signal settling full throughput rate. slower amps used, more settling time provided increasing time between conversions. best choice drive LTC1417 will depend application. Generally, applications fall into categories: applications where dynamic specifications most critical time domain applications where accuracy settling time most critical. following list summary amps that suitable driving LTC1417. More detailed information available Linear Technology Databooks LinearViewCD-ROM. 1354: 12MHz, 400V/µs Amp. 1.25mA maximum supply current. Good specifications. Suitable dual supply application. LT1357: 25MHz, 600V/µs Amp. 2.5mA maximum supply current. Good specifications. Suitable dual supply application.
LinearView trademark Linear Technology Corporation.
LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current, ±2.5V ±15V supplies. High AVOL, offset 80ns settling step, inverting noninverting configurations) make suitable fast applications. Excellent specifications. Dual quad versions available LT1361 LT1362. LT1468: 90MHz Voltage Feedback Amplifier. ±15V supplies. Lower distortion noise. Settles 0.01% 770ns. Distortion -115dB 20kHz. LT1498/LT1499: 10MHz, 6V/µs, Dual/Quad Rail-to-Rail Input Output Amps. 1.7mA supply current amplifier. 2.2V supplies. Good performance, input noise voltage 12nV/Hz (typ). LT1630/LT1631: 30MHz, 10V/µs, Dual/Quad Rail-to-Rail Input Output Precision Amps. 3.5mA supply current amplifier. 2.7V ±15V supplies. Best performance, input noise voltage 6nV/Hz (typ), 86dB 100kHz. LT1813: Dual 100MHz 750V/µs VFA. supplies. Distortion 86dB 100kHz 77dB 1MHz with supplies (2VP-P into 500). Great part fast applications with supplies. Input Filtering noise distortion input amplifier other circuitry must considered since they will LTC1417 noise distortion. small-signal bandwidth sample-and-hold circuit 10MHz. noise distortion products that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter sufficient many applications. example, Figure shows 1000pF
ANALOG INPUT 1000pF 10µF AIN+ AIN- VREF LTC1417
REFCOMP AGND
1417
Figure Input Filter
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LTC1417
APPLICATIONS INFORMATION
capacitor from ground source resistor limit input bandwidth 1.6MHz. 1000pF capacitor also acts charge reservoir input sample-and-hold isolates input from sampling glitch sensitive circuitry. High quality capacitors resistors should used since these components distortion. silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors also generate distortion from self heating from damage that occur during soldering. Metal film surface mount resistors much less susceptible both problems. Input Range ±2.048V 4.096V input ranges LTC1417 optimized noise distortion. Most amps also perform well over these ranges, allowing direct coupling analog inputs eliminating need special translation circuitry. Some applications require other input ranges. LTC1417 differential inputs reference circuitry accommodate other input ranges often with little additional circuitry. following sections describe reference input circuitry they affect input range. INTERNAL REFERENCE LTC1417 on-chip, temperature compensated, curvature corrected, bandgap reference which factory trimmed 2.500V. internally connected reference amplifier available resistor series with output that easily overdriven applications where external reference required, Figure capacitor must connected between
VOUT LT1460-2.5 10µF ANALOG INPUT 2.5V 0.1µF
OUTPUT CODE
OUTPUT CODE
AIN+ AIN-
LTC1417 VREF REFCOMP AGND
1417
Figure Using LT1460 External Reference
reference amplifier compensation (REFCOMP, ground. reference stable with capacitors greater. best noise performance, 10µF parallel with 0.1µF ceramic recommended. VREF driven with other means provide input span adjustment. reference should kept range 2.25V 2.75V specified linearity. UNIPOLAR BIPOLAR OPERATION ADJUSTMENT Figure shows input/output characteristics LTC1417. code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, 1.5LSB). output code natural binary with 1LSB FS/16384 4.096V/16384 250µV. Figure shows input/output transfer characteristics bipolar mode two's complement format.
111.111 111.110 111.101 111.100 1LSB 4.096V 16384 16384
000.011 000.010 000.001 000.000
UNIPOLAR ZERO
INPUT VOLTAGE
1LSB
1417 F10a
Figure 10a. LTC1417 Unipolar Transfer Characteristics
011.111 011.110 BIPOLAR ZERO
000.001 000.000 111.111 111.110
100.001 100.000 -FS/2
4.096V 1LSB FS/16384 INPUT VOLTAGE FS/2 1LSB
1417 F10b
Figure 10b. LTC1417 Bipolar Transfer Characteristics
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LTC1417
APPLICATIONS INFORMATION
Unipolar Offset Full-Scale Error Adjustment applications where absolute accuracy important, offset full-scale errors adjusted zero. Offset error must adjusted before full-scale error. Figures show extra components required fullscale error adjustment. Zero offset achieved adjusting offset applied AIN- input. zero offset error, apply 125µV (i.e., 0.5LSB) input adjust offset AIN- input until output code flickers between 0000 0000 0000 0000 0000 0000 full-scale adjustment, input voltage 4.095625V 1.5LSBs) applied AIN+ adjusted until output code flickers between 1111 1111 1111 1111 1111 1111 Bipolar Offset Full-Scale Error Adjustment Bipolar offset full-scale errors adjusted similar fashion unipolar case using circuit Figure 11b. Again, bipolar offset error must adjusted before full-scale error. Bipolar offset error adjustment achieved adjusting offset applied AIN- input. zero offset error, apply 125µV (i.e., 0.5LSB) AIN+ adjust offset AIN- input until output code flickers between 0000 0000 0000 1111 1111 1111 full-scale adjustment, input voltage 2.047625V 1.5LSBs) applied AIN+ adjusted until output code flickers between 0111 1111 1111 0111 1111 1111 BOARD LAYOUT GROUNDING obtain best performance from LTC1417, printed circuit board with ground plane required. ground plane under area should free breaks holes possible, such that impedance path between grounds decoupling capacitors provided. critical prevent digital noise from being coupled analog input, reference analog power supply lines. Layout should ensure that digital analog signal lines separated much possible. particular, care should taken digital track alongside analog signal track. analog ground plane separate from logic system ground should established under around ADC. (AGND) (DGND) other analog grounds should connected this single analog ground plane. REFCOMP bypass capacitor bypass capacitor should also connected this analog ground plane. other digital grounds should connected this analog ground plane. impedance analog digital power supply common returns essential noise operation foil width these tracks should wide possible. applications where data outputs control signals connected continuously active microprocessor bus, possible errors conversion results. These errors feedthrough from microprocessor successive approximation comparator. problem eliminated forcing microprocessor into
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ANALOG INPUT OFFSET
AIN+ AIN- VREF
LTC1417
10µF 0.1µF
REFCOMP AGND
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Figure 11a. Offset Full-Scale Adjust Circuit Available
ANALOG INPUT OFFSET 10µF 0.1µF AIN+ AIN- VREF
LTC1417
REFCOMP AGND
1417 F11b
Figure 11b. Offset Full-Scale Adjust Circuit Available
LTC1417
APPLICATIONS INFORMATION
AIN+ AIN- ANALOG INPUT CIRCUITRY VREF REFCOMP 10µF LTC1417 AGND 10µF 10µF DGND DIGITAL SYSTEM
ANALOG GROUND PLANE
1417
Figure Power Supply Grounding Practice
wait state during conversion using three-state buffers isolate data bus. traces connecting pins bypass capacitors must kept short should made wide possible. LTC1417 differential inputs minimize noise coupling. Common mode noise AIN+ AIN- leads will rejected input CMRR. AIN- input used ground sense AIN+ input; LTC1417 will hold convert difference voltage between AIN+ AIN-. leads AIN+ (Pin AIN- (Pin should kept short possible. applications where this possible, AIN+ AIN- traces should side side equalize coupling. SUPPLY BYPASSING High quality, series resistance ceramic, 10µF bypass capacitors should used REFCOMP pins. Surface mount ceramic capacitors such Taiyo Yuden LMK325BJ106MN provide excellent bypassing small board space. Alternatively 10µF tantalum capacitors parallel with 0.1µF ceramic capacitors used. Bypass capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible.
SHDN CONVST
Figure SHDN CONVST Wake-Up Timing
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Example Layout Figures 13a, 13b, show schematic layout suggested evaluation board. layout demonstrates proper decoupling capacitors ground plane with 2-layer printed circuit board. POWER SHUTDOWN LTC1417 provides power shutdown modes, Sleep, save power during inactive periods. mode reduces power dissipation leaves only digital logic reference powered wake-up time from active 500ns (see Figure 14). Sleep mode, bias currents shut down only leakage current remains- about 2µA. Wake-up time from Sleep mode much slower since reference circuit must power settle 0.005% full 14-bit accuracy. Sleep mode wake-up time dependent value capacitor connected REFCOMP (Pin wake-up time 30ms with recommended 10µF capacitor. Shutdown controlled (SHDN); shutdown when low. shutdown mode selected with (RD); selects mode, high selects Sleep mode.
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LTC1417
APPLICATIONS INFORMATION
0.1µF 0.1µF
OPTIONAL
LT1363CN8
0.1µF
1000pF
LTC1417CGN +AIN -AIN VREF REFCOMP AGND EXTCLKIN CLKOUT BUSY CONVST SHDN DGND DOUT
10µF
JP5A JP5B JP5C
Figure 13a. Suggested Evaluation Circuit Schematic
Figure 13b. Suggested Evaluation Circuit Board-Component Side Silkscreen
Figure 13c. Suggested Evaluation Circuit Board-Component Side
LT1363CS8
10µF
AGND DGND TC74HCT244AF
0.1µF
10µF
10µF
100k
0.1µF BYPASS CAPACITOR
10µF
100k
100k BUSY DOUT SCLK
CON7
1417 F13a
100k
CLKOUT EXTCLKIN
Figure 13d. Suggested Evaluation Circuit Board-Solder Side
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LTC1417
APPLICATIONS INFORMATION
DIGITAL INTERFACE LTC1417 operates serial mode. control input common peripheral memory interfacing. Only four digital interface lines required, SCLK, CONVST, EXTCLKIN DOUT. SCLK, serial data shift clock external input supplied LTC1417's internal clock. Internal Clock internal clock. Either internal clock external clock used conversion clock (see Figure 15). internal clock factory trimmed achieve typical conversion time 1.8µs, maximum conversion time over full operating temperature range 2.5µs. external adjustments required, with guaranteed maximum acquisition time 0.5µs, throughput performance 400ksps assured. Conversion Control Conversion start controlled signal applied CONVST input. falling edge signal applied CONVST starts conversion. Once initiated, cannot restarted until conversion complete. Converter status indicated BUSY output. BUSY during conversion. Data Output Output will active when low. high will threestate ouput. unipolar mode (VSS 0V), data will straight binary format (corresponding unipolar input range). bipolar mode (VSS 5V), data will two's complement format (corresponding bipolar input range). Serial Output Mode Conversions started falling CONVST edge. After conversion completed output shift register been updated, BUSY will high valid data will available DOUT (Pin This data clocked either before next conversion starts clocked during next conversion. enable serial data output buffer shift clock, must low. Figure shows function block diagram LTC1417. There pieces this circuitry: conversion clock selection circuit (EXTCLKIN CLKOUT) serial port (SCLK, DOUT RD).
DATA CLOCK INPUT SHIFT REGISTER SCLK
CONVERSION CLOCK CYCLES THREE STATE BUFFER
CLOCK DETECTOR INTERNAL CLOCK
Figure Functional Block Diagram
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DATA THREE STATE BUFFER
DOUT
CLKOUT
EXTCLKIN
BUSY
1417
LTC1417
APPLICATIONS INFORMATION
Conversion Clock Selection Figure conversion clock controls internal operation. conversion clock either internal external. connecting EXTCLKIN high, internal clock selected. This clock generates clock cycles which feed into each conversion. select external conversion clock, apply external conversion clock EXTCLKIN (Pin (When external shift clock (SCLK) used during conversion, SCLK should used external conversion clock avoid noise generated asynchronous clocks. maintain accuracy, external conversion clock frequency must between 50kHz 9MHz.) sends conversion signal, EOC, that gates external conversion clock that only clock cycles into SAR, even external clock, EXTCLKIN, contains more than cycles. When low, these cycles conversion clock (whether internally externally generated) will appear CLKOUT during each conversion then CLKOUT will remain until next conversion. desired, CLKOUT used master clock drive serial port. Because CLKOUT running during conversion, important avoid excessive loading that cause large supply transients create noise. best performance, limit CLKOUT loading 20pF. Serial Port serial port Figure made 16-bit shift register three-state output buffer that controlled inputs: SCLK serial port output, DOUT, that provides serial output data. SCLK used clock shift register. Data clocked with internal conversion clock operating master connecting CLKOUT (Pin SCLK (Pin with external data clock applied SCLK. minimum number SCLK cycles required transfer data word Normally, SCLK contains clock cycles word length bits; bits with first, followed trailing zeros. logic high disables SCLK three-states DOUT. case using continuous SCLK, controlled limit number shift clocks desired number (i.e., cycles) three-state DOUT after data transfer. power shutdown mode (SHDN low), high selects Sleep mode while selects mode. DOUT outputs serial data; bits, first, falling edge each SCLK (see Figures 17). SCLKs provided, data bits will followed zeros. (D13) will valid first rising first falling edge SCLK. will valid second rising second falling edge will remaining bits. data captured using either edge. largest hold time margin achieved data captured rising edge SCLK. BUSY gives end-of-conversion indication. When LTC1417 configured serial master, BUSY used framing pulse. three-state serial port after transferring serial output data, BUSY should connected together (see Figure 17). Figures show several serial modes operation, demonstrating flexibility LTC1417 serial interface.
SCLK
DOUT
1417
Figure SCLK DOUT Delay
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LTC1417
APPLICATIONS INFORMATION
Serial Data Output During Conversion Using Internal Clock Conversion Data Transfer. Figure shows data from previous conversion being clocked during conversion with LTC1417 internal clock providing both conversion clock SCLK. internal clock been optimized fastest conversion time; consequently, this mode provide best overall speed performance. select internal conversion clock, EXTCLKIN (Pin high. internal clock appears CLKOUT (Pin which tied SCLK (Pin supply SCLK.
CONVST
CONVST
(SAMPLE EXTCLKIN CONVST BUSY CLKOUT SCLK) DOUT Hi-Z FILL ZEROS Hi-Z DATA CLKOUT SCLK)
1417
DOUT
Figure Internal Conversion Clock Selected. Data Transferred During Conversion Using Clock Output Master Shift Clock (SCLK Driven from CLKOUT)
BUSY
BUSY (CONFIGURED SLAVE) SHIFT REGISTER
LTC1417 SCLK CLKOUT DOUT
CLKOUT SCLK) DOUT
(SAMPLE
HOLD SAMPLE HOLD
DATA tCONV
CAPTURE RISING CLOCK CAPTURE FALLING CLOCK
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LTC1417
APPLICATIONS INFORMATION
Using External Clock Conversion Data Transfer. Figure data from previous conversion output during conversion with external clock providing both conversion clock shift clock. select external conversion clock, apply clock EXTCLKIN. same clock also applied SCLK provide data shift clock. maintain conversion accuracy, external clock frequency must between 50kHz 9MHz. Using external clock transfer data while internal clock controls conversion process recommended. both signals asynchronous, clock noise corrupt conversion result.
CONVST
CONVST
(SAMPLE CONVST BUSY tdEXTCLKIN EXTCLKIN SCLK) DOUT Hi-Z FILL ZEROS Hi-Z DATA EXTCLKIN SCLK) tLEXTCLKIN DOUT CAPTURE RISING CLOCK CAPTURE FALLING CLOCK tHEXTCLKIN
1417
Figure External Conversion Clock Selected. Data Transferred During Conversion Using External Clock (External Clock Drives Both EXTCLKIN SCLK)
BUSY
BUSY
LTC1417 EXTCLKIN SCLK DOUT
EXTCLKIN SCLK)
DOUT
(SAMPLE
HOLD SAMPLE HOLD
DATA tCONV
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LTC1417
APPLICATIONS INFORMATION
Serial Data Output After Conversion Using Internal Conversion Clock External Data Clock. this mode, data output after each conversion before next conversion started (Figure 19). internal clock used conversion clock external clock used SCLK. This mode useful applications where processor acts serial master device. This mode MICROWIREcompatible. also allows operation when SCLK frequency very (less than 30kHz). select internal conversion clock, EXTCLKIN high. external SCLK applied SCLK. used gate external SCLK, such that data will clock only after goes three-state DOUT after data transfer. more than SCLKs provided, more zeros will filled after data word indefinitely.
MICROWIRE trademark National Semiconductor Corporation.
CONVST
CONVST
BUSY
LTC1417 SCLK DOUT
EXTCLKIN CONVST
BUSY HOLD SCLK DOUT (SAMPLE tCONV DATA Hi-Z
Figure Internal Conversion Clock Selected. Data Transferred After Conversion Using External SCLK. BUSY Indicates Conversion
MISO
SAMPLE
FILL ZEROS Hi-Z
1417
SCLK
LSCLK HSCLK
DOUT
CAPTURE RISING CLOCK CAPTURE FALLING CLOCK
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LTC1417
APPLICATIONS INFORMATION
Using External Conversion Clock External Data Clock. Figure data also output after each conversion completed before next conversion started. external clock used conversion clock either another same external clock used SCLK. This mode identical Figure except that external clock used conversion. This mode allows user synchronize conversion external clock either have precise control internal test timing provide precise conversion time. Figure this mode works when SCLK frequency very (less than 30kHz). However, external conversion clock must between 30kHz 9MHz maintain accuracy. more than SCLKs provided, more zeros will filled after data word indefinitely. select external conversion clock, apply external conversion clock EXTCLKIN. external SCLK applied SCLK. used gate external SCLK such that data will clocked only after goes low.
CONVST
CONVST EXTCLKIN BUSY LTC1417 SCLK DOUT
tdEXTCLKIN EXTCLKIN CONVST
BUSY HOLD SCLK DOUT (SAMPLE tCONV DATA Hi-Z
Figure External Conversion Clock Selected. Data Transferred After Conversion Using External SCLK. BUSY Indicates Conversion
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CLKOUT
MISO
SAMPLE
FILL ZEROS Hi-Z
SCLK
LSCLK HSCLK
DOUT
CAPTURE RISING CLOCK CAPTURE FALLING CLOCK
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LTC1417
TYPICAL APPLICATIONS
Figure shows connections necessary interfacing LTC1417 LTC1391 8-channel signal acquisition system port. With sample software routine shown Listing uses MOSI send serial data LTC1391 8-channel multiplexer, selecting eight channels. While data sent LTC1391, uses MISO retrieve conversion data from LTC1417. After data transfer complete, conversion start signal sent LTC1417. conversion signaled logic high BUSY output. When this occurs, data exchanged between LTC1417/LTC1391 controller. timing diagram Figure shows relation between channel selection data conversion data that simultaneously exchanged. There conversion delay between data selects given channel when that channel's data retrieved.
LTC1391
DOUT DGND
Figure 4.096V, 8-Channel Data Acquisition System Configured Control Data Retrieval 68HC11 Code Shown Listing
0.1µF 10µF AIN+ AIN- VREF REFCOMP AGND EXTCLKIN SCLK CLKOUT BUSY CONVST SHDN DGND DOUT
10µF
LTC1417
PORT PORT
MC68HC11 MISO MOSI
1417
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LTC1417
TYPICAL APPLICATIONS
Listing
This example program retrieves data from previous LTC1417 conversion loads next LTC1391 channel. stores 14-bit, right justified data consecutive memory locations. finishes initiating next conversion. 68HC11 register definitions PIOC $1002 Parallel control register "STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB" PORTC $1003 Port data register DDRC $1007 Port data direction register output, input PORTD $1008 Port data register ,CSK ;MOSI,MISO,TxD ,RxD DDRD $1009 Port data direction register SPCR $1028 control register "SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0" SPSR $1029 status register "SPIF,WCOL, ,MODF; SPDR $102A data register; Read-Buffer; Write-Shifter variables hold LTC1417's conversion result DIN1 This memory location holds LTC1417's bits DIN2 This memory location holds LTC1417's bits This memory location holds address data Start GETDATA Routine $C000 Program start location INIT1 LDAA #$03 0,0,0,0,0,0,1,1 "STAF=0,STAI=0,CWOM=0,HNDS=0, OIN=0, PLS=0, EGA=1,INVB=1" STAA PIOC Ensures that PIOC register's status same after reset, necessary simple Port manipulation LDAA #$01 0,0,0,0,0,0,0,1 "Bit7=input,- ,Bit0=output" Bit7 used BUSY signal input, Bit0 used CONVST signal output STAA DDRC direction PortD's bits LDAA PORTC contents Port ORAA #%00000001 Bit0 high STAA PORTC Initialize CONVST logic high LDAA #$2F -,-,1,0;1,1,1,1 SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, STAA PORTD Keeps logic high when DDRD, LDAA #$38 -,-,1,1;1,0,0,0 STAA DDRD SCK, MOSI configured Outputs MISO, TxD, configured Inputs DDRD's that port general output LDAA #$50 STAA SPCR configured Master, CPHA CPOL clock rate
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LTC1417
TYPICAL APPLICATIONS
(This assumes E-Clock frequency 4MHz. higher E-Clock frequencies, change above value value that ensures frequency 2MHz less.) GETDATAPSHX PSHY PSHA Setup indecies register used pointer memory locations that hold conversion data #$1000 next short loop ensures that LTC1417's conversion finished before starting data transfer CONVENDLDAA PORTC Retrieve contents port ANDA #%10000000 Look Bit7 Bit7 LTC1417's conversion complete Bit7 LTC1417's conversion complete CONVEND Branch loop's beginning while Bit7 remains This routine sends data LTC1417 sets channel. very first time this routine entered produces invalid data. Each time thereafter, data will correspond previous active CONVST signal sent LTC1417. LDAA #$00 Dummy value upper byte 16-bit transfer BCLR PORTD,Y %00100000 This sets output logic low, selecting LTC1417 STAA SPDR Transfer Accum. contents register initiate serial transfer WAITMX1 LDAA SPSR transfer status WAITMX1If transfer finished, read status LDAA SPDR Load accumulator with current byte LTC1417 data that just received STAA DIN1 Transfer LTC1417's high byte (Bit13 Bit6) memory LDAA Retrieve address ORAA #$08 MUX's ENABLE STAA SPDR Transfer Accum. contents register initiate serial transfer WAITMX2 LDAA SPSR transfer status WAITMX2If transfer finished, read status BSET PORTD,Y %00100000 This sets output logic high, de-selecting LTC1417 LDAA SPDR Load accumulator with current byte LTC1417 data that just received STAA DIN2 Transfer LTC1417's byte (Bit5 Bit0) memory DIN1 Load contents DIN1 DIN2 into double accumulator LSRD LSRD logical shifts right right justify 14-bit conversion results DIN1 Place right justified result back memory
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LTC1417
TYPICAL APPLICATIONS
Initiate LTC1417 conversion BCLR PORTC,Y %00000001 This sets PORTC, Bit0 output logic low, initiating conversion BSET PORTC,Y %00000001 This resets PORTC, Bit0 output logic high, returning CONVST logic high PULA Restore register PULY Restore register PULX Restore register
CONVST
BUSY
DATA
DATA
1417
Figure This Diagram Shows Relationship Between Selected LTC1391 Channel Conversion Data Retrieved from LTC1417 When Using Sample Program Listing Point Time, Conversion Delay Exists Between Selected Channel When Data Retrieved
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LTC1417
TYPICAL APPLICATIONS
Figure uses DG408 select eight ±2.048V bipolar signals apply LTC1417's analog input. circuit designed connect 68HC11 MUX's parallel input connected controller's port LTC1417's serial interface accessed through controller's interface. sequence generate conversion shown sample program Listing first step selects channel. This followed initiating conversion waiting BUSY high, signifying conversion. Once BUSY goes low, used retrieve 14-bit conversion data. timing relationships between various control signals data transmission shown Figure
DG408
0.1µF 10µF
Figure With Input Range ±2.048V Each Eight Inputs, This Data Acquisition System Configured Communication with 68HC11
0.1µF AIN+ AIN- VREF REFCOMP AGND EXTCLKIN SCLK CLKOUT BUSY CONVST SHDN DGND DOUT MISO MC68HC11 PORT PORT PORT
1417
LTC1417
PORT PORT
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LTC1417
TYPICAL APPLICATIONS
Listing
This example program selects DG408 channel using parallel port initiates conversion, retrieves data from LTC1417. stores 14-bit, right justified data consecutive memory locations. 68HC11 register definitions PIOC $1002 Parallel control register "STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB" PORTC $1003 Port data register DDRC $1007 Port data direction register output, input PORTD $1008 Port data register ,CSK ;MOSI,MISO,TxD ,RxD DDRD $1009 Port data direction register SPCR $1028 control register "SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0" SPSR $1029 status register "SPIF,WCOL, ,MODF; SPDR $102A data register; Read-Buffer; Write-Shifter variables hold LTC1417's conversion result DIN1 This memory location holds LTC1417's bits DIN2 This memory location holds LTC1417's bits This memory location holds address data Start GETDATA Routine $C000 Program start location INIT1 LDAA #$03 0,0,0,0,0,0,1,1 "STAF=0,STAI=0,CWOM=0,HNDS=0, OIN=0, PLS=0, EGA=1,INVB=1" STAA PIOC Ensures that PIOC register's status same after reset, necessary simple Port manipulation LDAA #$47 0,1,0,0,0,1,1,1 "Bit7=input,Bit6=output,- ,Bit2=output,Bit1=output, Bit0=output" Bit7 used BUSY input Bit6 used CONVST signal output Bits used address STAA DDRC Direction PortD's LDAA #$2F -,-,1,0;1,1,1,1 SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, STAA PORTD Keeps logic high when DDRD, Bit5 LDAA #$38 -,-,1,1;1,0,0,0 STAA DDRD SCK, MOSI configured Outputs MISO, TxD, configured Inputs DDRD's Bit5 that port general output LDAA #$50 STAA SPCR configured Master, CPHA CPOL clock rate (This assumes E-Clock frequency 4MHz. higher
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LTC1417
TYPICAL APPLICATIONS
E-Clock frequencies, change above value value that ensures frequency 2MHz less.) GETDATAPSHX PSHY PSHA Setup indecies register used pointer memory locations that hold conversion data #$1000 Initialize LTC1417's CONVST input logic high before conversion start BSET PORTC,Y %01000000 This sets PORTC, Bit6 output logic high, forcing CONVST logic high Retrieve address from memory send DG408 LDAA PORTC Capture contents PortC ORAA "Add" address STAA PORTC Select channel Initiate LTC1417 conversion BCLR PORTC,Y %01000000 This sets PORTC, Bit6 output logic low, initiating conversion BSET PORTC,Y %01000000 This resets PORTC, Bit6 output logic high, returning CONVST logic high next short loop ensures that LTC1417's conversion finished before starting data transfer CONVENDLDAA PORTC Retrieve contents port ANDA #%10000000 Look Bit7 Bit7 LTC1417's conversion complete Bit7 LTC1417's conversion complete CONVEND Branch loop's beginning while Bit7 remains high This routine sends data LTC1417 sets channel. very first time this routine entered produces invalid data. Each time thereafter, data will correspond previous active CONVST signal sent LTC1417.
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LTC1417
TYPICAL APPLICATIONS
BCLR TRFLP1 LDAA STAA WAIT1 LDAA LDAA STAA BSET LSRD LSRD PULA PULY PULX This sets output logic low, selecting LTC1417 Load accumulator with null byte transfer SPDR This writes byte into data register starts transfer SPSR This loop waits complete serial transfer/exchange reading Status Register WAIT1 SPIF (SPI transfer complete flag) SPSR's transfer. branch will occur while SPIF zero. SPDR Load accumulator with current byte LTC1417 data that just received Transfer LTC1417's data memory Increment pointer #DIN2+1Has last byte been transferred/exchanged? TRFLP1 last byte been reached, then proceed next byte transfer/exchage PORTD,Y %00100000 This sets output logic high, de-selecting LTC1417 DIN1 Load contents DIN1 DIN2 into double accumulator logical shifts right justify 14-bit conversion results Return right justified data memory Restore register Restore register Restore register PORTD,Y %00100000
DIN1
CONVST
BUSY
SCLK
DOUT
DATA
DATA
Figure Using Sample Program Listing LTC1417, Combined with DG408 8-Channel MUX, Latency Between Selected Input Voltage Conversion Data Shown Timing Relationship Above
DATA
DATA
DATA
1417
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LTC1417
PACKAGE DESCRIPTIO
Package 16-Lead Plastic SSOP (Narrow 0.150)
(LTC 05-08-1641)
0.189 0.196* (4.801 4.978) 0.009 (0.229) 0.229 0.244 (5.817 6.198) 0.150 0.157** (3.810 3.988) 0.015 0.004 (0.38 0.10) 0.007 0.0098 (0.178 0.249) 0.016 0.050 (0.406 1.270) DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE 0.053 0.068 (1.351 1.727) 0.004 0.0098 (0.102 0.249) 0.008 0.012 (0.203 0.305) 0.025 (0.635)
GN16 (SSOP) 0398
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Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LTC1417
RELATED PARTS
PART NUMBER ADCs LTC1274/LTC1277 LTC1401 LTC1404 LTC1412 LTC1415 LTC1416 LTC1418 LTC1419 LTC1604 LTC1605 DACs LTC1595 LTC1596 LTC1650 LTC1655 LTC1658 Reference LT1019-2.5 LT1460-2.5 LT1461-2.5 Precision Bandgap Reference Micropower 3-Termainal Bandgap Reference Ultraprecise Micropower Dropout Reference 0.05% Max, 5ppm/°C 0.075% Max, 10ppm/°C 0.04%, 3ppm/°C Serial 16-Bit CMOS Mulitplying SO-8 Serial 16-Bit CMOS Mulitplying Serial 16-Bit Voltage Output Serial 16-Bit Voltage Output Serial 14-Bit Voltage Output ±1LSB INL/DNL, Glitch, DAC8043 Upgrade ±1LSB INL/DNL, DAC8143/AD7543 Upgrade Noise Glitch Rail-to-Rail VOUT Power, SO-8 with Internal Reference Power, 8-Lead MSOP Rail-to-Rail VOUT Power, 12-Bit, 100ksps ADCs with Parallel Output Serial 12-Bit, 200ksps SO-8 Serial 12-Bit, 600ksps SO-8 12-Bit, 3Msps Sampling with Parallel Output Single 12-Bit, 1.25Msps with Parallel Output Power, 14-Bit, 400ksps with Parallel Output Power, 14-Bit, 200ksps with Parallel Serial Power, 14-Bit, 800ksps with Parallel Output 16-Bit, 333ksps Sampling with Parallel Output Single 16-Bit, 100ksps with Parallel Output 10mW Power Dissipation, Parallel/Byte Interface 15mW, Internal Reference Power Shutdown Mode ±5V, Internal Reference Shutdown Best Dynamic Performance, SINAD 72dB Nyquist 55mW Power Dissipation, 72dB SINAD 70mW Power Dissipation, 80.5dB SINAD True 14-Bit Linearity, 81.5dB, SINAD, 15mW Dissipation True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipaton ±2.5V Input, 90dB SINAD, 100dB Power, ±10V Inputs, Parallel/Byte Interface DESCRIPTION COMMENTS
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT/TP 0102 1.5K PRINTED
www.linear.com
LINEAR TECHNOLOGY CORPORATION 1999

DESCRIPTIO 16-Pin Narrow SSOP Package (SO-8 Footprint) Sample Rat

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