SYNCHRONOUS DRAM PC100 functionality Fully synchronous; signals r

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SYNCHRONOUS DRAM PC100 functionality Fully synchronous; signals r

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64Mb: SDRAM
SYNCHRONOUS DRAM
PC100 functionality Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal banks hiding access/precharge Programmable burst lengths: full page Auto Precharge, includes CONCURRENT AUTO PRECHARGE, Auto Refresh Modes Self Refresh Mode 64ms, 4,096-cycle refresh (15.6µs/row) LVTTL-compatible inputs outputs Single +3.3V ±0.3V power supply Supports latency
MT48LC2M32B2 512K banks
latest data sheet, please refer Micron site:
ASSIGNMENT (TOP VIEW) 86-PIN TSOP
VDDQ VSSQ VDDQ VSSQ DQM0 CAS# RAS# DQM2 DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23
OPTIONS
Configuration (512K banks) Plastic Package OCPL1 86-pin TSOP (400 mil) Timing (Cycle Time) (200 MHz) 5.5ns (183 MHz) (166 MHz) (143 MHz) Operating Temperature Range Commercial +70°C) Extended (-40°C +85°C)
NOTE: Off-center parting line Available Part Number Example:
MARKING
2M32B2 None
MT48LC2M32B2TG-7
DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ DQM1 DQM3 DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24
TIMING PARAMETERS
SPEED GRADE CLOCK ACCESS TIME FREQUENCY 4.5ns 5.5ns 5.5ns SETUP TIME 1.5ns 1.5ns 1.5ns HOLD TIME
Note: symbol indicates signal active LOW.
Configuration Refresh Count Addressing Bank Addressing Column Addressing
512K banks (A0-A10) (BA0, BA1) (A0-A7)
(READ) latency
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
64Mb (x32) SDRAM PART NUMBER
PART NUMBER MT48LC2M32B2TG ARCHITECTURE
GENERAL DESCRIPTION
64Mb SDRAM high-speed CMOS, dynamic random-access memory containing 67,108,864-bits. internally configured quad-bank DRAM with synchronous interface (all signals registered positive edge clock signal, CLK). Each 16,777,216-bit banks organized 2,048 rows columns bits. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select bank accessed (BA0, select bank, A0-A10 select row). address bits registered coincident with READ WRITE command used select starting column location burst access.
SDRAM provides programmable READ WRITE burst lengths locations, full page, with burst terminate option. auto precharge function enabled provide self-timed precharge that initiated burst sequence. 64Mb SDRAM uses internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve high-speed, fully random access. Precharging bank while accessing other three banks will hide precharge cycles provide seamless, high-speed, random-access operation. 64Mb SDRAM designed operate 3.3V, low-power memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs outputs LVTTL-compatible. SDRAMs offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic column-address generation, ability interleave between internal banks hide precharge time capability randomly change column addresses each clock cycle during burst access.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
TABLE CONTENTS
Functional Block Diagram Descriptions Functional Description Initialization Register Definition Mode Register Burst Length Burst Type Latency Operating Mode Write Burst Mode Commands Truth Table (Commands Operation) Command Inhibit Operation (NOP) Load Mode Register Active Read Write Precharge Auto Precharge Burst Terminate Auto Refresh Self Refresh Operation Bank/Row Activation Reads Writes Precharge Power-Down Clock Suspend Burst Read/Single Write Concurrent Auto Precharge Write with Auto Precharge Truth Table (CKE) Truth Table (Current State, Same Bank) Truth Table (Current State, Different Bank) Absolute Maximum Ratings Electrical Characteristics Operating Conditions Specifications Conditions Capacitance
Electrical Characteristics (Timing Table) Electrical Characteristics Timing Waveforms Initialize Load Mode Register Power-Down Mode Clock Suspend Mode Auto Refresh Mode Self Refresh Mode Reads Read Single Read Read Without Auto Precharge Read With Auto Precharge Alternating Bank Read Accesses Read Full-Page Burst Read Operation Writes Write Single Write Write Without Auto Precharge Write With Auto Precharge Alternating Bank Write Accesses Write Full-Page Burst Write Operation
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
FUNCTIONAL BLOCK DIAGRAM SDRAM
CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 BANK0
COMMAND DECODE
MODE REGISTER
REFRESH COUNTER
ROWADDRESS
BANK0 ROWADDRESS LATCH DECODER
2048
BANK0 MEMORY ARRAY (2,048
DQM0DQM3
SENSE AMPLIFIERS 8192
DATA OUTPUT REGISTER
A0-A10, BA0, ADDRESS REGISTER BANK CONTROL LOGIC
GATING MASK LOGIC READ DATA LATCH WRITE DRIVERS (x32) DATA INPUT REGISTER
DQ0DQ31
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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64Mb: SDRAM
DESCRIPTIONS
NUMBERS SYMBOL TYPE Input DESCRIPTION Clock: driven system clock. SDRAM input signals sampled positive edge CLK. also increments internal burst counter controls output registers. Clock Enable: activates (HIGH) deactivates (LOW) signal. Deactivating clock provides PRECHARGE POWER-DOWN SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active bank) CLOCK SUSPEND operation (burst/access progress). synchronous except after device enters power-down self refresh modes, where becomes asynchronous until after exiting same mode. input buffers, including CLK, disabled during power-down self refresh modes, providing standby power. tied HIGH. Chip Select: enables (registered LOW) disables (registered HIGH) command decoder. commands masked when registered HIGH. provides external bank selection systems with multiple banks. considered part command code. Command Inputs: CAS#, RAS# (along with CS#) define command being entered. Input/Output Mask: sampled HIGH input mask signal write accesses output enable signal read accesses. Input data masked during WRITE cycle. output buffers placed High-Z state (two-clock latency) during READ cycle. DQM0 corresponds DQ0DQ7; DQM1 corresponds DQ8-DQ15; DQM2 corresponds DQ16-DQ23; DQM3 corresponds DQ24-DQ31. DQM0-DQM3 considered same state when referenced DQM. Bank Address Input(s): define which bank ACTIVE, READ, WRITE PRECHARGE command being applied. Address Inputs: A0-A10 sampled during ACTIVE command (rowaddress A0-A10) READ/WRITE command (column-address A0-A7 with defining auto precharge) select location memory array respective bank. sampled during PRECHARGE command determine banks precharged (A10 HIGH) bank selected BA0, (LOW). address inputs also provide op-code during LOAD MODE REGISTER command.
Input
Input
WE#, CAS#, RAS# DQM0DQM3
Input Input
25-27, 60-66,
BA0, A0-A10
Input Input
DQ0-DQ31
Input/ Data I/Os: Data bus. Output
VDDQ VSSQ
Supply Supply Supply Supply
Connect: These pins should left unconnected. reserved SSTL reference voltage supply. Power Supply: Isolated improved noise immunity. Ground: Provide isolated ground improved noise immunity. Power Supply: +3.3V ±0.3V. Ground.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
FUNCTIONAL DESCRIPTION
general, this 64Mb SDRAM (512K banks) quad-bank DRAM that operates 3.3V includes synchronous interface (all signals registered positive edge clock signal, CLK). Each 16,777,216-bit banks organized 2,048 rows columns 32-bits. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select bank accessed (BA0 select bank, A0-A10 select row). address bits (A0-A7) registered coincident with READ WRITE command used select starting column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation.
Register Definition
MODE REGISTER Mode Register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode write burst mode, shown Figure Mode Register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power. Mode Register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write burst mode, reserved future use. Mode Register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. Burst Length Read write accesses SDRAM burst oriented, with burst length being programmable, shown Figure burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached. block uniquely selected A1-A7 when burst length two; A2-A7 when burst length four; A3-A7 when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT NOP. Starting some point during this 100µs period continuing least through this period, COMMAND INHIBIT commands should applied. Once 100µs delay been satisfied with least COMMAND INHIBIT command having been applied, PRECHARGE command should applied. banks must then precharged, thereby placing device banks idle state. Once idle state, AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM ready Mode Register programming. Because Mode Register will power unknown state, should loaded prior applying operational command.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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64Mb: SDRAM
BURST TYPE
Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Table
Table Burst Definition
Burst Starting Column Order Accesses Within Burst Length Address Type Sequential Type Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Supported
Address
Mode Register (Mx) Reserved* Mode Latency Burst length
*Should program ensure compatibility with future devices. BA0,
Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Full Page (256)
Burst Type Sequential Interleave
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 A0-A7 (Location -256)
NOTE:
Latency Reserved Reserved Reserved Reserved Reserved
Defined
Operating Mode Standard operation other states reserved
burst length two, A1-A7 select blockof-two burst; selects starting column within block. burst length four, A2-A7 select blockof-four burst; A0-A1 select starting column within block. burst length eight, A3-A7 select blockof-eight burst; A0-A2 select starting column within block. full-page burst, full selected A0-A7 select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-A7 select unique column accessed, mode register ignored.
Write Burst Mode Programmed Burst Length Single Location Access
Figure Mode Register Definition
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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64Mb: SDRAM
Latency latency delay, clock cycles, between registration READ command availability first piece output data. latency one, three clocks. READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, READ command registered latency programmed clocks, will start driving after data will valid shown Figure Table below indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result. Operating Mode normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both READ WRITE bursts. Test modes reserved states should used because unknown operation incompatibility with future versions result. Write Burst Mode When burst length programmed M0-M2 applies both READ WRITE bursts; when programmed burst length applies READ bursts, write accesses single-location (nonburst) accesses.
COMMAND
READ
DOUT
Latency
Table Latency
COMMAND
ALLOWABLE OPERATING FREQUENCY (MHz) SPEED LATENCY LATENCY LATENCY
READ
DOUT
Latency
COMMAND
READ
DOUT
Latency
DON'T CARE UNDEFINED
Figure Latency
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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64Mb: SDRAM
Commands
Truth Table provides quick reference available commands. This followed written description each command. Three additional Truth Tables appear following Operation section; these tables provide current state/next state information.
TRUTH TABLE COMMANDS OPERATION
(Note: NAME (FUNCTION) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z NOTE: RAS# CAS# L/H8 L/H8 ADDR Bank/Row Bank/Col Bank/Col Code Op-Code Valid Active Active High-Z NOTES
HIGH commands shown except SELF REFRESH. A0-A10 define op-code written Mode Register. A0-A10 provide address, determine which bank made active. A0-A7 provide column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; determine which bank being read from written LOW: determine bank being precharged. HIGH: banks precharged "Don't Care." This command AUTO REFRESH HIGH; SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay). DQM0 controls DQ0-DQ7; DQM1 controls DQ8-DQ15; DQM2 controls DQ16-DQ23; DQM3 controls DQ24-DQ31.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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64Mb: SDRAM
COMMAND INHIBIT COMMAND INHIBIT function prevents commands from being executed SDRAM, regardless whether signal enabled. SDRAM effectively deselected. Operations already progress affected. OPERATION (NOP) OPERATION (NOP) command used perform SDRAM which selected (CS# LOW). This prevents unwanted commands from being registered during idle wait states. Operations already progress affected. LOAD MODE REGISTER mode register loaded inputs A0-A10. mode register heading Register Definition section. LOAD MODE REGISTER command only issued when banks idle, subsequent executable command cannot issued until tMRD met. ACTIVE ACTIVE command used open activate) particular bank subsequent access. value inputs selects bank, address provided inputs A0-A10 selects row. This remains active open) accesses until PRECHARGE command issued that bank. PRECHARGE command must issued before opening different same bank. READ READ command used initiate burst read access active row. value (B1) inputs selects bank, address provided inputs A0-A7 selects starting column location. value input determines whether auto precharge used. auto precharge selected, being accessed will precharged READ burst; auto precharge selected, will remain open subsequent accesses. Read data appears subject logic level inputs clocks earlier. given DQMx signal registered HIGH, corresponding will HighZ clocks later; DQMx signal registered LOW, corresponding will provide valid data. DQM0 corresponds DQ0-DQ7, DQM1 corresponds DQ8-DQ15, DQM2 corresponds DQ16-DQ23 DQM3 corresponds DQ24-DQ31. WRITE WRITE command used initiate burst write access active row. value inputs selects bank, address provided inputs A0-A7 selects starting column location. value input determines whether auto precharge used. auto precharge selected, being accessed will precharged WRITE burst; auto precharge selected, will remain open subsequent accesses. Input data appearing written memory array subject input logic level appearing coincident with data. given signal registered LOW, corresponding data will written memory; signal registered HIGH, corresponding data inputs will ignored, WRITE will executed that byte/column location. PRECHARGE PRECHARGE command used deactivate open particular bank open banks. bank(s) will available subsequent access specified time (tRP) after PRECHARGE command issued. Input determines whether banks precharged, case where only bank precharged, inputs select bank. Otherwise treated "Don't Care." Once bank been precharged, idle state must activated prior READ WRITE commands being issued that bank. AUTO PRECHARGE Auto precharge feature which performs same individual-bank PRECHARGE function described above, without requiring explicit command. This accomplished using enable auto precharge conjunction with specific READ WRITE command. PRECHARGE bank/row that addressed with READ WRITE command automatically performed upon completion READ WRITE burst, except full-page burst mode, where auto precharge does apply. Auto precharge nonpersistent that either enabled disabled each individual READ WRITE command. Auto precharge ensures that precharge initiated earliest valid stage within burst. user must issue another command same bank until precharge time (tRP) completed. This determined explicit PRECHARGE command issued earliest possible time, described each burst type Operation section this data sheet.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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64Mb: SDRAM
BURST TERMINATE BURST TERMINATE command used truncate either fixed-length full-page bursts. most recently registered READ WRITE command prior BURST TERMINATE command will truncated, shown Operation section this data sheet. AUTO REFRESH AUTO REFRESH used during normal operation SDRAM analagous CAS#-BEFORE-RAS# (CBR) REFRESH conventional DRAMs. This command nonpersistent, must issued each time refresh required. addressing generated internal refresh controller. This makes address bits "Don't Care" during AUTO REFRESH command. 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (tREF), regardless width option. Providing distributed AUTO REFRESH command every 15.625µs will meet refresh requirement ensure that each refreshed. Alternatively, 4,096 AUTO REFRESH commands issued burst minimum cycle rate (tRC), once every 64ms. SELF REFRESH SELF REFRESH command used retain data SDRAM, even rest system powered down. When self refresh mode, SDRAM retains data without external clocking. SELF REFRESH command initiated like AUTO REFRESH command except disabled (LOW). Once SELF REFRESH command registered, inputs SDRAM become "Don't Care" with exception CKE, which must remain LOW. Once self refresh mode engaged, SDRAM provides internal clocking, causing perform AUTO REFRESH cycles. SDRAM must remain self refresh mode minimum period equal tRAS remain self refresh mode indefinite period beyond that. procedure exiting self refresh requires sequence commands. First, must stable (stable clock defined signal cycling within timing constraints specified clock pin) prior going back HIGH. Once HIGH, SDRAM must have commands issued minimum clocks) tXSR because time required completion internal refresh progress. Upon exiting SELF REFRESH mode, AUTO REFRESH commands must issued every 15.625ms less both SELF REFRESH AUTO REFRESH utililze refresh counter.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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64Mb: SDRAM
Operation
BANK/ROW ACTIVATION Before READ WRITE commands issued bank within SDRAM, that bank must "opened." This accomplished ACTIVE command, which selects both bank activated. Figure After opening (issuing ACTIVE command), READ WRITE command issued that row, subject tRCD specification. tRCD (MIN) should divided clock period rounded next whole number determine earliest clock edge after ACTIVE command which READ WRITE command issued. example, tRCD specification 20ns with clock (8ns period) results clocks, rounded This reflected Figure which covers case where tRCD (MIN)/ (The same procedure used convert other specification limits from time units clock cycles.) subsequent ACTIVE command different same bank only issued after previous active been "closed" (precharged). minimum time interval between successive ACTIVE commands same bank defined tRC. subsequent ACTIVE command another bank issued while first bank being accessed, which results reduction total row-access overhead. minimum time interval between successive ACTIVE commands different banks defined tRRD.
HIGH
RAS#
CAS#
A0-A10
ADDRESS
BA0,BA1
BANK ADDRESS
Figure Activating Specific Specific Bank
COMMAND ACTIVE
tRCD (MIN) tRCD (MIN) +0.5
READ WRITE
tRCD (MIN) 20ns, tRCD (MIN) where number clocks equation true.
DON'T CARE
Example: Meeting
tRCD
Figure (MIN) When tRCD (MIN)/tCK
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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64Mb: SDRAM
READs READ bursts initiated with READ command, shown Figure starting column bank addresses provided with READ command, auto precharge either enabled disabled that burst access. auto precharge enabled, being accessed precharged completion burst. generic READ commands used following illustrations, auto precharge disabled. During READ bursts, valid data-out element from starting column address will available following latency after READ command. Each subsequent data-out element will valid next positive clock edge. Figure shows general timing each possible latency setting. Upon completion burst, assuming other commands have been initiated, will HighZ. full-page burst will continue until terminated. page, will wrap column continue.) Data from READ burst truncated with subsequent READ command, data from fixedlength READ burst immediately followed data from READ command. either case, continuous flow data maintained. first data element from burst follows either last element completed burst last desired data element longer burst that being truncated. READ command should issued cycles before clock edge which last desired data element valid, where equals latency minus one. This
HIGH
COMMAND
READ
DOUT
Latency
RAS#
CAS#
COMMAND
READ
DOUT
A0-A7
COLUMN ADDRESS
Latency
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
COMMAND
READ
DOUT
BA0,1
BANK ADDRESS
Latency
Figure READ Command Figure Latency
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
DON'T CARE UNDEFINED
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64Mb: SDRAM
shown Figure latencies one, three; data element either last burst four last desired longer burst. This 64Mb SDRAM uses pipelined architecture therefore does require rule associated with prefetch architecture. READ command initiated clock cycle following previous READ command. Fullspeed random read accesses performed same bank, shown Figure each subsequent READ performed different bank.
COMMAND
READ
READ cycles
ADDRESS
BANK,
BANK,
DOUT
DOUT
DOUT
DOUT
DOUT
Latency
COMMAND
READ
READ
cycle
ADDRESS
BANK,
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
READ
cycles
ADDRESS
BANK,
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
DOUT
NOTE: Each READ command either bank. LOW. DON'T CARE
Figure Consecutive READ Bursts
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64Mb: SDRAM
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
BANK,
BANK,
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
BANK,
BANK,
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
BANK,
BANK,
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
NOTE: Each READ command either bank. LOW. DON'T CARE
Figure Random READ Accesses
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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64Mb: SDRAM
Data from READ burst truncated with subsequent WRITE command, data from fixedlength READ burst immediately followed data from WRITE command (subject turnaround limitations). WRITE burst initiated clock edge immediately following last last desired) data element from READ burst, provided that contention avoided. given system design, there possibility that device driving input data will Low-Z before SDRAM High-Z. this case, least single-cycle delay should occur between last read data WRITE command.
COMMAND ADDRESS
READ
WRITE
input used avoid contention, shown Figures signal must asserted (HIGH) least clocks prior WRITE command (DQM latency clocks output buffers) suppress data-out from READ. Once WRITE command registered, will High-Z remain High-Z), regardless state signal; provided active clock just prior WRITE command that truncated READ command. not, second WRITE will invalid WRITE. example, during Figure then WRITEs would valid, while WRITE would invalid. signal must de-asserted prior WRITE command (DQM latency zero clocks input buffers) ensure that written data masked. Figure shows case where clock frequency allows contention avoided without adding cycle, Figure shows case where additional needed.
BANK,
BANK,
DOUT
COMMAND
READ WRITE
NOTE:
latency three used illustration. READ command bank, WRITE command bank. burst used, then required.
ADDRESS
BANK,
BANK,
DOUT
Figure READ WRITE
NOTE: latency three used illustration. READ command bank, WRITE command bank. DON'T CARE
Figure READ WRITE with Extra Clock Cycle
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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64Mb: SDRAM
fixed-length READ burst followed truncated with, PRECHARGE command same bank (provided that auto precharge activated), full-page burst truncated with PRECHARGE command same bank. PRECHARGE command should issued cycles before clock edge which last desired data element valid, where equals latency minus one. This shown Figure each possible latency; data element either last burst four last desired longer burst. Following PRECHARGE command, subsequent command same bank cannot issued until met. Note that part precharge time hidden during access last data element(s). case fixed-length burst being executed completion, PRECHARGE command issued optimum time described above) provides same
COMMAND
READ
PRECHARGE cycles
ACTIVE
ADDRESS
BANK
BANK all)
BANK
Latency
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
PRECHARGE cycle
ACTIVE
ADDRESS
BANK
BANK all)
BANK
Latency
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
PRECHARGE
ACTIVE
cycles
ADDRESS
BANK
BANK all)
BANK
Latency
DOUT
DOUT
DOUT
DOUT
NOTE: LOW.
DON'T CARE
Figure READ PRECHARGE
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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64Mb: SDRAM
operation that would result from same fixed-length burst with auto precharge. disadvantage PRECHARGE command that requires that command address buses available appropriate time issue command; advantage PRECHARGE command that used truncate fixed-length full-page bursts. Full-page READ bursts truncated with BURST TERMINATE command, fixed-length READ
bursts truncated with BURST TERMINATE command, provided that auto precharge activated. BURST TERMINATE command should issued cycles before clock edge which last desired data element valid, where equals latency minus one. This shown Figure each possible latency; data element last desired data element longer burst.
COMMAND
READ
BURST TERMINATE cycles
ADDRESS
BANK,
DOUT
DOUT
DOUT
DOUT
Latency
COMMAND
READ
BURST TERMINATE cycle
ADDRESS
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
BURST TERMINATE
cycles
ADDRESS
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
NOTE: LOW.
DON'T CARE
Figure Terminating READ Burst
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64Mb: SDRAM
WRITEs WRITE bursts initiated with WRITE command, shown Figure starting column bank addresses provided with WRITE command, auto precharge either enabled disabled that access. auto precharge enabled, being accessed precharged completion burst. generic WRITE commands used following illustrations,auto precharge disabled. During WRITE bursts, first valid data-in element will registered coincident with WRITE command. Subsequent data elements will registered each successive positive clock edge. Upon completion fixed-length burst, assuming other commands have been initiated, will remain High-Z additional input data will ignored (see Figure 14). full-page burst will continue until terminated. page, will wrap column continue.) Data WRITE burst truncated with subsequent WRITE command, data fixedlength WRITE burst immediately followed data WRITE command. WRITE command issued clock following previous WRITE command, data provided coincident with command applies command. example shown Figure Data either last burst last desired longer burst. This 64Mb SDRAM uses pipelined architecture therefore does require rule associated with prefetch architecture. WRITE command initiated clock cycle following previous WRITE command. Full-speed random write accesses within page performed same bank, shown Figure each subsequent WRITE performed different bank. Data WRITE burst truncated with
COMMAND
WRITE
ADDRESS
BANK,
HIGH
NOTE: Burst length LOW.
Figure WRITE Burst
RAS#
CAS#
COMMAND
WRITE
WRITE
A0-A7
COLUMN ADDRESS
ADDRESS
BANK,
BANK,
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
NOTE:
LOW. Each WRITE command bank. DON'T CARE
BA0,1
BANK ADDRESS
Figure WRITE Command
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Figure WRITE WRITE
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64Mb: SDRAM
subsequent READ command, data fixedlength WRITE burst immediately followed READ command. Once READ command registered, data inputs will ignored, WRITEs will executed. example shown Figure Data either last burst last desired longer burst. Data fixed-length WRITE burst followed truncated with, PRECHARGE command same bank (provided that auto precharge activated), full-page WRITE burst truncated with PRECHARGE command same bank. PRECHARGE command should issued after clock edge which last desired input data element registered. "two-clock" write-back requires least clock plus time, regardless frequency, auto precharge mode. addition, when
truncating WRITE burst, signal must used mask input data clock edge prior clock edge coincident with, PRECHARGE command. example shown Figure Data either last burst last desired longer burst. Following PRECHARGE command, subsequent command same bank cannot issued until met. precharge will actually begin coincident with clock-edge Figure "one-clock" sometime between first second clock "two-clock" (between Figure 18.) case fixed-length burst being executed completion, PRECHARGE command issued optimum time described above) provides same operation that would result from same fixed-length burst with auto precharge. disadvantage PRECHARGE command that requires that command address buses available appropriate time issue command; advantage PRECHARGE command that used truncate fixed-length full-page bursts. Fixed-length full-page WRITE bursts trun-
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
BANK,
BANK,
BANK,
(tCK tWR)
NOTE:
Each WRITE command bank. LOW.
COMMAND
WRITE
PRECHARGE
ACTIVE
ADDRESS
BANK
BANK all)
BANK
Figure Random WRITE Cycles
(when tCK)
COMMAND
WRITE
READ
COMMAND ADDRESS
WRITE
PRECHARGE
ACTIVE
BANK
BANK all)
BANK
ADDRESS
BANK,
BANK,
NOTE:
DOUT
DOUT
NOTE:
WRITE command bank, READ command bank. LOW. latency illustration.
could remain this example WRITE burst fixed length two. DON'T CARE
Figure WRITE READ
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Figure WRITE PRECHARGE
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64Mb: SDRAM
cated with BURST TERMINATE command. When truncating WRITE burst, input data applied coincident with BURST TERMINATE command will ignored. last data written (provided that that time) will input data applied clock previous BURST TERMINATE command. This shown Figure where data last desired data element longer burst. PRECHARGE PRECHARGE command (Figure used deactivate open particular bank open banks. bank(s) will available subsequent access some specified time (tRP) after PRECHARGE command issued. Input determines whether banks precharged, case where only bank precharged, inputs select bank. When banks precharged, inputs treated "Don't Care." Once bank been precharged, idle state must activated prior READ WRITE commands being issued that bank. POWER-DOWN Power-down occurs registered coincident with COMMAND INHIBIT when accesses progress (see Figure 21). power-down occurs when banks idle, this mode referred precharge power-down; power-down occurs when there active either bank, this mode referred active power-down. Entering power-down deactivates input output buffers, excluding CKE, maximum power savings while standby. device remain power-down state longer than refresh period (64ms) since refresh operations performed this mode. power-down state exited registering COMMAND INHIBIT HIGH desired clock edge (meeting tCKS).
COMMAND
WRITE
BURST TERMINATE
NEXT COMMAND
ADDRESS
BANK,
(ADDRESS)
(DATA)
NOTE: DQMs LOW.
Figure Terminating WRITE Burst
HIGH
tCKS
tCKS
RAS#
COMMAND
ACTIVE
banks idle
CAS#
Input buffers gated Enter power-down mode. Exit power-down mode.
tRCD tRAS DON'T CARE
A0-A9
Figure Power-Down
Banks Bank Selected
BA0,1
BANK ADDRESS
Figure PRECHARGE Command
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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CLOCK SUSPEND clock suspend mode occurs when column access/burst progress registered LOW. clock suspend mode, internal clock deactivated, "freezing" synchronous logic. each positive clock edge which sampled LOW, next internal positive clock edge suspended. command data present input pins time suspended internal clock edge ignored; data present pins remains driven; burst counters incremented, long clock suspended. (See examples Figures 23.) Clock suspend mode exited registering HIGH; internal clock related operation will resume subsequent positive clock edge. BURST READ/SINGLE WRITE burst read/single write mode entered programming write burst mode (M9) Mode Register logic this mode, WRITE commands result access single column location (burst one), regardless programmed burst length. READ commands access columns according programmed burst length sequence, just normal mode operation
INTERNAL CLOCK
INTERNAL CLOCK
COMMAND
READ
COMMAND
WRITE
ADDRESS
BANK,
ADDRESS
BANK,
DOUT
DOUT
DOUT
DOUT
NOTE: this example, latency burst length greater, LOW.
DON'T CARE
NOTE: this example, burst length greater, LOW.
Figure CLOCK SUSPEND During WRITE Burst
Figure CLOCK SUSPEND During READ Burst
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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CONCURRENT AUTO PRECHARGE access command (READ WRITE) another bank while access command with auto precharge enabled executing allowed SDRAMs, unless SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs defined below. READ with auto precharge Interrupted READ (with without auto precharge): READ bank will interrupt READ bank latency later. PRECHARGE bank will begin when READ bank registered (Figure 24). Interrupted WRITE (with without auto precharge): WRITE bank will interrupt READ bank when registered. should used clocks prior WRITE command prevent contention. PRECHARGE bank will begin when WRITE bank registered (Figure 25).
COMMAND BANK
READ BANK
READ BANK
Page Active
READ with Burst
Interrupt Burst, Precharge BANK
Idle BANK Precharge
Internal States
BANK
Page Active
READ with Burst
ADDRESS
BANK
BANK DOUT DOUT DOUT DOUT
Latency (BANK Latency (BANK
NOTE: LOW.
Figure READ With Auto Precharge Interrupted READ
READ BANK Page Active WRITE BANK
COMMAND BANK
READ with Burst
Interrupt Burst, Precharge BANK
Idle BANK Write-Back
Internal States
BANK
BANK
Page Active
WRITE with Burst
ADDRESS
BANK
DOUT Latency (BANK
NOTE: HIGH prevent DOUT-a+1 from contending with DIN-d DON'T CARE
Figure READ With Auto Precharge Interrupted WRITE
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WRITE WITH AUTO PRECHARGE Interrupted READ (with without auto precharge): READ bank will interrupt WRITE bank when registered, with dataout appearing latency later. PRECHARGE bank will begin after met, where begins when READ bank registered. last valid WRITE bank will data-in registered clock prior READ bank (Figure 26). Interrupted WRITE (with without auto precharge): WRITE bank will interrupt WRITE bank when registered. PRECHARGE bank will begin after met, where begins when WRITE bank registered. last valid data WRITE bank will data registered clock prior WRITE bank (Figure 27).
COMMAND BANK
WRITE BANK
READ BANK
Page Active
WRITE with Burst
Interrupt Burst, Write-Back BANK
Precharge BANK BANK
Internal States
BANK
Page Active
READ with Burst
ADDRESS
BANK
BANK DOUT Latency (BANK DOUT
NOTE: LOW.
Figure WRITE With Auto Precharge Interrupted READ
WRITE BANK WRITE BANK
COMMAND BANK
Page Active
WRITE with Burst
Interrupt Burst, Write-Back BANK
Precharge BANK BANK Write-Back
Internal States
BANK
Page Active
WRITE with Burst
ADDRESS NOTE: LOW.
BANK
BANK
DON'T CARE
Figure WRITE With Auto Precharge Interrupted WRITE
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TRUTH TABLE
(Notes: 1-4) CKEn-1 CKEn CURRENT STATE Power-Down Self Refresh Clock Suspend Power-Down Self Refresh Clock Suspend Banks Idle Banks Idle Reading Writing NOTE: COMMANDn COMMAND INHIBIT COMMAND INHIBIT COMMAND INHIBIT AUTO REFRESH VALID Truth Table ACTIONn Maintain Power-Down Maintain Self Refresh Maintain Clock Suspend Exit Power-Down Exit Self Refresh Exit Clock Suspend Power-Down Entry Self Refresh Entry Clock Suspend Entry NOTES
CKEn logic state clock edge CKEn-1 state previous clock edge. Current state state SDRAM immediately prior clock edge COMMANDn command registered clock edge ACTIONn result COMMANDn. states sequences shown illegal reserved. Exiting power-down clock edge will device banks idle state time clock edge (provided that tCKS met). Exiting self refresh clock edge will device banks idle state once tXSR met. COMMAND INHIBIT commands should issued clock edges occurring during tXSR period. minimum commands must provided during tXSR period. After exiting clock suspend clock edge device will resume operation recognize next command clock edge
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TRUTH TABLE CURRENT STATE BANK COMMAND BANK
(Notes: 1-6; notes appear below next page) CURRENT STATE RAS# CAS# Idle Active Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) NOTE: COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) OPERATION (NOP/Continue previous operation) ACTIVE (Select activate row) AUTO REFRESH LOAD MODE REGISTER PRECHARGE READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE (Deactivate bank banks) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE (Truncate READ burst, start PRECHARGE) BURST TERMINATE READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE (Truncate WRITE burst, start PRECHARGE) BURST TERMINATE NOTES
This table applies when CKEn-1 HIGH CKEn HIGH (see Truth Table after tXSR been previous state self refresh). This table bank-specific, except where noted, i.e., current state specific bank commands shown those allowed issued that bank when that state. Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/ accesses register accesses progress. Read: READ burst been initiated, with auto precharge disabled, terminated been terminated. Write: WRITE burst been initiated, with auto precharge disabled, terminated been terminated. following states must interrupted command issued same bank. COMMAND INHIBIT commands, allowable commands other bank should issued clock edge occurring during these states. Allowable commands other bank determined current state Truth Table according Truth Table Precharging: Starts with registration PRECHARGE command ends when met. Once met, bank will idle state. Activating: Starts with registration ACTIVE command ends when tRCD met. Once tRCD met, bank will active state. Read w/Auto Precharge Enabled: Starts with registration READ command with auto precharge enabled ends when been met. Once met, bank will idle state.
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NOTE (continued):
Starts with registration WRITE command with auto precharge enabled ends when been met. Once met, bank will idle state. following states must interrupted executable command; COMMAND INHIBIT commands must applied each positive clock edge during these states. Refreshing: Starts with registration AUTO REFRESH command ends when met. Once met, SDRAM will banks idle state. Accessing Mode Register: Starts with registration LOAD MODE REGISTER command ends when tMRD been met. Once tMRD met, SDRAM will banks idle state. Precharging All: Starts with registration PRECHARGE command ends when met. Once met, banks will idle state. states sequences shown illegal reserved. bank-specific; requires that banks idle. bank-specific; banks precharged, must valid state precharging. bank-specific; BURST TERMINATE affects most recent READ WRITE burst, regardless bank. READs WRITEs listed Command (Action) column include READs WRITEs with auto precharge enabled READs WRITEs with auto precharge disabled. Does affect state bank acts that bank. Write w/Auto Precharge Enabled:
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TRUTH TABLE CURRENT STATE BANK COMMAND BANK
(Notes: 1-6; notes appear below next page) CURRENT STATE Idle Activating, Active, Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (With Auto Precharge) Write (With Auto Precharge) RAS# CAS# NOTE: COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) OPERATION (NOP/Continue previous operation) Command Otherwise Allowed Bank ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE NOTES
This table applies when CKEn-1 HIGH CKEn HIGH (see Truth Table after tXSR been previous state self refresh). This table describes alternate bank operation, except where noted; i.e., current state bank commands shown those allowed issued bank (assuming that bank such state that given command allowable). Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/ accesses register accesses progress. Read: READ burst been initiated, with auto precharge disabled, terminated been terminated. Write: WRITE burst been initiated, with auto precharge disabled, terminated been terminated. Read w/Auto Precharge Enabled: Starts with registration READ command with auto precharge enabled, ends when been met. Once met, bank will idle state.
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NOTE (continued):
AUTO REFRESH, SELF REFRESH, LOAD MODE REGISTER commands only issued when banks idle. BURST TERMINATE command cannot issued another bank; applies bank represented current state only. states sequences shown illegal reserved. READs WRITEs bank listed Command (Action) column include READs WRITEs with auto precharge enabled READs WRITEs with auto precharge disabled. CONCURRENT AUTO PRECHARGE: Bank will initiate auto precharge command when burst been interrupted bank burst. Burst bank continues initiated. READ without auto precharge interrupted READ (with without auto precharge), READ bank will interrupt READ bank latency later (Figure READ without auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt READ bank when registered (Figures 10). should used clock prior WRITE command prevent contention. WRITE without auto precharge interrupted READ (with without auto precharge), READ bank will interrupt WRITE bank when registered (Figure 17), with data-out appearing latency later. last valid WRITE bank will data-in registered clock prior READ bank WRITE without auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt WRITE bank when registered (Figure 15). last valid WRITE bank will data-in registered clock prior READ bank READ with auto precharge interrupted READ (with without auto precharge), READ bank will interrupt READ bank latency later. PRECHARGE bank will begin when READ bank registered (Figure 24). READ with auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt READ bank when registered. should used clocks prior WRITE command prevent contention. PRECHARGE bank will begin when WRITE bank registered (Figure 25). WRITE with auto precharge interrupted READ (with without auto precharge), READ bank will interrupt WRITE bank when registered, with data-out appearing latency later. PRECHARGE bank will begin after met, where begins when READ bank registered. last valid WRITE bank will data-in registered clock prior READ bank (Figure 26). WRITE with auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt WRITE bank when registered. PRECHARGE bank will begin after met, where begins when WRITE bank registered. last valid WRITE bank will data registered clock prior WRITE bank (Figure 27).
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ABSOLUTE MAXIMUM RATINGS*
Voltage VDD, VDDQ Supply Relative +4.6V Voltage Inputs, Pins Relative +4.6V Operating Temperature, +70°C Extended Temperature -40°C +85°C Storage Temperature (plastic) -55°C +150°C Power Dissipation *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
(Notes: notes appear page (VDD, VDDQ +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test OUTPUT LEAKAGE CURRENT: disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA) SYMBOL VDD, VDDQ -0.3 UNITS NOTES
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
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SPECIFICATIONS CONDITIONS
(Notes: notes appear page (VDD, VDDQ +3.3V ±0.3V) PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN); latency STANDBY CURRENT: Power-Down Mode; LOW; banks idle STANDBY CURRENT: Active Mode; HIGH; HIGH; banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; banks active, latency AUTO REFRESH CURRENT: latency CKE, HIGH SELF REFRESH CURRENT: 0.2V
tRFC
SYMBOL IDD1
UNITS NOTES
IDD2 IDD3
IDD4
tRFC (MIN)
IDD5
IDD6
SPECIFICATIONS CONDITIONS
(Notes: notes appear page (VDD, VDDQ +3.3V ±0.3V) PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN); latency STANDBY CURRENT: Power-Down Mode; LOW; banks idle STANDBY CURRENT: Active Mode; HIGH; HIGH; banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; banks active, latency AUTO REFRESH CURRENT: latency CKE, HIGH SELF REFRESH CURRENT: 0.2V
tRFC tRFC
SYMBOL IDD1
UNITS NOTES
IDD2 IDD3
IDD4
(MIN)
IDD5
IDD6
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CAPACITANCE
(Note: notes appear page PARAMETER Input Capacitance: Input Capacitance: other input-only pins Input/Output Capacitance: SYMBOL UNITS
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
(Notes: notes appear page
CHARACTERISTICS PARAMETER Access time from (pos. edge) Address hold time Address setup time high-level width low-level width Clock cycle time UNITS NOTES 38.7 120k 16.5 16.5
hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time
Data-out low-impedance time Data-out hold time ACTIVE PRECHARGE command ACTIVE ACTIVE command period AUTO REFRESH period ACTIVE READ WRITE delay Refresh period (4,096 rows) PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time WRITE recovery time Exit SELF REFRESH ACTIVE command
SYMBOL tCKH tCKS tCMH tCMS tRFC tRCD tREF tRRD tXSR
38.7
120k
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ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
(Notes: notes appear page
CHARACTERISTICS PARAMETER Access time from (pos. edge) Address hold time Address setup time high-level width low-level width Clock cycle time SYMBOL tCKH tCKS tCMH tCMS tRAS tRFC tRCD tREF tRRD UNITS NOTES
hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time
1CLK+ 12ns
2.75 2.75 1CLK+ 14ns
Data-out low-impedance time Data-out hold time ACTIVE PRECHARGE command ACTIVE ACTIVE command period AUTO REFRESH period ACTIVE READ WRITE delay Refresh period (4,096 rows) PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time WRITE recovery time
120k
120k
Exit SELF REFRESH ACTIVE command
tXSR
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FUNCTIONAL CHARACTERISTICS
(Notes: notes appear page
PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVE command SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDAL tDAL tDPL tBDL tCDL tRDL tMRD tROH tROH tROH UNITS NOTES
Data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command
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64Mb: SDRAM
NOTES
voltages referenced VSS. This parameter sampled. VDD, VDDQ +3.3V; MHz, 25°C; under test biased 1.4V. range from 6pF. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range (0°C +70°C -40°C +85°C parts) ensured. initial pause 100µs required after powerup, followed AUTO REFRESH commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. VSSQ must same potential.) AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate. Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate. Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will decrease latency reduced. This fact that maximum cycle rate slower latency reduced. Address transitions average transition every clocks. must toggled minimum times during this period. Based -55, overshoot: VIH(MAX) VDDQ 1.2V pulse width 3ns, pulse width cannot greater than third cycle rate. undershoot: VIL(MIN) -1.2V pulse width 3ns, pulse width cannot greater than third cycle rate. clock frequency must remain constant during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. JEDEC PC100 specify three clocks. 5.5ns -5.5, VDD(MIN) 3.135V. Check factory availability specially screened devices having 10ns. slower (tCK 10ns higher) manual precharge.
30pF
Outputs measured 1.5V with equivalent load: defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have 2.75, with timing referenced 1.5V crossover point. Other input signals allowed transition more than once two-clock period otherwise valid levels.
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64Mb: SDRAM
INITIALIZE LOAD MODE REGISTER
tCKS
tCKH
tCMH tCMS
AUTO REFRESH
tCMH tCMS COMMAND
tCMH tCMS
PRECHARGE
AUTO REFRESH
LOAD MODE REGISTER
ACTIVE
A0-A9
CODE
BANKS SINGLE BANK
CODE
BA0,
BANKS
BANK
100µs (MIN) Power-up: stable
High-Z
tRCAR tRCAR tMRD
Precharge banks
AUTO REFRESH
AUTO REFRESH
Program Mode Register DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL*
tCLK tCLK tCLK
2.75 2.75
UNITS SYMBOL*
tCKH tCKS tCMH tCMS tMRD tRFC
UNITS
*CAS latency indicated parentheses.
NOTE: Mode Register loaded prior AUTO REFRESH cycles desired. Outputs guaranteed High-Z after command issued.
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POWER-DOWN MODE
tCKS tCKS tCKH
tCKS
tCMS tCMH COMMAND
PRECHARGE
ACTIVE
A0-A9
BANKS
SINGLE BANK
BA0,
BANK(S)
BANK
High-Z
clock cycles Precharge active banks banks idle, enter power-down mode
Input buffers gated while power-down mode banks idle Exit power-down mode DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL*
2.75 2.75
UNITS SYMBOL*
tCKH tCKS tCMH tCMS
UNITS
*CAS latency indicated parentheses.
NOTE: Violating refresh requirements during power-down result loss data.
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CLOCK SUSPEND MODE
tCKS tCKH tCKS tCKH
tCMS tCMH COMMAND
READ WRITE
tCMS tCMH DQM0-3 A0-A9
COLUMN
COLUMN
BA0,
BANK BANK
DOUT
DOUT
DOUT
DOUT
DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL*
tCKH
2.75 2.75
UNITS SYMBOL* tCKS
tCMH tCMS
UNITS
*CAS latency indicated parentheses.
NOTE: this example, burst length latency auto precharge disabled. "Don't Care."
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AUTO REFRESH MODE
tCKS tCMS COMMAND tCKH tCMH
AUTO REFRESH
PRECHARGE
AUTO REFRESH
ACTIVE
A0-A9
BANKS
SINGLE BANK
BA0,
BANK(S)
tRCAR tRCAR
BANK
High-Z
Precharge active banks
DON'T CARE
UNDEFINED DON'T CARE
TIMING PARAMETERS
SYMBOL*
2.75 2.75
UNITS SYMBOL* tCKH
tCKS tCMH tCMS tRFC
UNITS
*CAS latency indicated parentheses.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
SELF REFRESH MODE
tCKS
tRAS
tCKS tCMS COMMAND tCKH tCMH
AUTO REFRESH
tCKS
PRECHARGE
AUTO REFRESH
A0-A9
BANKS
SINGLE BANK
BA0,
BANK(S)
High-Z Precharge active banks Enter self refresh mode
tXSR Exit self refresh mode (Restart refresh time base)
DON'T CARE UNDEFINED
stable prior exiting self refresh mode
TIMING PARAMETERS
SYMBOL*
2.75 2.75
UNITS SYMBOL* tCKH
tCKS tCMH tCMS tRAS tXSR
38.7 120,000
120,000
UNITS 120,000
*CAS latency indicated parentheses.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
SINGLE READ
tCKS tCMS COMMAND tCMH tCMS DQML, DQMH A0-A9, BA0, BANK DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK COLUMN READ tCMH PRECHARGE ACTIVE tCKH
ACTIVE
BANKS
tRCD tRAS Latency
DOUT
DON'T CARE
TIMING PARAMETERS
SYMBOL*
tCKH tCKS
UNITS SYMBOL* tCMH tCMS
tRAS tRCD
UNITS 120,000
2.75 2.75
120,000 120,000
38.7
*CAS latency indicated parentheses.
NOTE: this example, burst length latency READ burst followed "manual" PRECHARGE. "Don't Care."
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
READ WITHOUT AUTO PRECHARGE
tCKS tCMS COMMAND tCMH
READ PRECHARGE ACTIVE
tCKH
ACTIVE
tCMS A0-A9 BA0,
tCMH
COLUMN
BANKS DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK
BANK
tRCD tRAS Latency
DOUT
DOUT
DOUT
DOUT
DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL*
tCKH tCKS
2.75 2.75 UNITS SYMBOL* tCMH
tCMS tRAS tRCD
UNITS
38.7 120,000
120,000
120,000
*CAS latency indicated parentheses.
NOTE:
this example, burst length latency READ burst followed "manual" PRECHARGE. "Don't Care."
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
READ WITH AUTO PRECHARGE
tCKS tCMS tCMH COMMAND
ACTIVE READ ACTIVE
tCKH
tCMS A0-A9
tCMH
COLUMN
ENABLE AUTO PRECHARGE
BA0,
BANK BANK
BANK
tRCD tRAS Latency
DOUT
DOUT
DOUT
DOUT
DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL*
tCKH tCKS
2.75 2.75
UNITS SYMBOL*
tCMH tCMS tRAS tRCD
120,000
UNITS 120,000
38.7 120,000
*CAS latency indicated parentheses.
NOTE: this example, burst length latency "Don't Care."
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
ALTERNATING BANK READ ACCESSES
tCKS tCMS COMMAND tCMH
READ ACTIVE READ ACTIVE
tCKH
ACTIVE
tCMS A0-A9
tCMH
COLUMN
COLUMN
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
BA0,
BANK BANK BANK BANK
BANK
tRCD BANK tRAS BANK BANK tRRD Latency BANK
DOUT
DOUT
DOUT
DOUT
DOUT
BANK
tRCD BANK
tRCD BANK
Latency BANK
DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL*
tCKH
2.75 2.75 UNITS SYMBOL* tCKS
tCMH tCMS tRAS tRCD tRRD
38.7
UNITS
120,000
120,000
120,000
*CAS latency indicated parentheses.
NOTE: this example, burst length latency "Don't Care."
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
READ FULL-PAGE BURST
tCKS tCMS COMMAND tCMH
READ
tCKH
ACTIVE
BURST TERM
tCMS
tCMH
A0-A9
COLUMN
BA0,
BANK
BANK
tRCD Latency
Dout
DOUT
DOUT
DOUT
DOUT
DOUT
locations within same
Full page completed Full-page burst does self-terminate. BURST TERMINATE command.
DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL*
2.75 2.75 UNITS SYMBOL* tCKH
tCKS tCMH tCMS tRCD
UNITS
*CAS latency indicated parentheses.
NOTE: this example, latency "Don't Care." Page left open; tRP.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
READ OPERATION
tCKS tCMS COMMAND tCMH
READ
tCKH
ACTIVE
tCMS A0-A9
tCMH
COLUMN ENABLE AUTO PRECHARGE
BA0,
BANK
DISABLE AUTO PRECHARGE BANK
tRCD Latency
DOUT
DOUT
DOUT
DON'T CARE UNDEFINED
TIMING PARAMETERS
SYMBOL*
2.75 2.75 UNITS SYMBOL* tCKH
tCKS tCMH tCMS tRCD
UNITS
*CAS latency indicated parentheses.
NOTE: this example, latency "Don't Care."
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
SINGLE WRITE
tCKS tCMS COMMAND tCMH
WRITE PRECHARGE ACTIVE
tCKH
ACTIVE
tCMS tCMH DQML, DQMH A0-A9,
COLUMN BANKS DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK
BA0,
BANK
tRCD tRAS
DON'T CARE
TIMING PARAMETERS
SYMBOL*
tCKH tCKS
2.75 2.75
UNITS SYMBOL*
tCMH tCMS tRAS tRCD
38.7
UNITS
120,000
120,000
120,000
*CAS latency indicated parentheses.
NOTE: this example, burst length WRITE burst followed "manual" PRECHARGE. 10ns required between <DIN PRECHARGE command, regardless frequency, meet tWR. "Don't Care."
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
WRITE WITHOUT AUTO PRECHARGE
tCKS tCMS COMMAND tCMH
WRITE PRECHARGE ACTIVE
tCKH
ACTIVE
tCMS tCMH A0-A9
COLUMN BANKs DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK
BA0,
BANK
tRCD tRAS
DON'T CARE
TIMING PARAMETERS
SYMBOL*
tCKH tCKS
2.75 2.75
UNITS SYMBOL* tCMH tCMS
tRAS tRCD tWR4
38.7 120,000
120,000
UNITS 120,000
*CAS latency indicated parentheses.
NOTE:
this example, burst length WRITE burst followed "manual" PRECHARGE. Faster frequencies require clocks (when tCK). "Don't Care." available running slower. Check factory availability.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
WRITE WITH AUTO PRECHARGE
tCKS tCMS COMMAND tCMH
WRITE ACTIVE
tCKH
ACTIVE
tCMS tCMH A0-A9
COLUMN ENABLE AUTO PRECHARGE
BA0,
BANK BANK
BANK
tRCD tRAS
DON'T CARE
TIMING PARAMETERS
SYMBOL*
2.75 2.75
UNITS SYMBOL*
38.7
UNITS
120,000
120,000
120,000
tCKH
tCKS
CLK+
CLK+
*CAS latency indicated parentheses.
NOTE: this example, burst length Faster frequencies require clocks (when tCK). "Don't Care."
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
ALTERNATING BANK WRITE ACCESSES
tCKS tCMS COMMAND tCMH
WRITE ACTIVE WRITE ACTIVE
tCKH
ACTIVE
tCMS A0-A9
tCMH
COLUMN
COLUMN
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
BA0,
BANK BANK BANK BANK
BANK
tRCD BANK tRAS BANK BANK tRRD
BANK
tRCD BANK
tWR2 BANK
tRCD BANK
BANK
DON'T CARE
TIMING PARAMETERS
SYMBOL*
tCKH tCKS tCMH tCMS
2.75 2.75
UNITS SYMBOL*
tRAS tRCD tRRD
38.7
UNITS
120,000
120,000
CLK+
CLK+
*CAS latency indicated parentheses.
NOTE: this example, burst length Faster frequencies require clocks (when tCK). "Don't Care."
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
WRITE FULL-PAGE BURST
tCKS tCMS COMMAND tCMH
WRITE
tCKH
ACTIVE
BURST TERM
tCMS tCMH
A0-A9
COLUMN
BA0,
BANK
BANK
tRCD
locations within same
Full-page burst does self-terminate. BURST TERMINATE command stop.2,
Full page completed
DON'T CARE
TIMING PARAMETERS
SYMBOL*
2.75 2.75
UNITS SYMBOL* tCKH tCKS
tCMH tCMS tRCD
UNITS
*CAS latency indicated parentheses. NOTE: "Don't Care." must satisfied prior PRECHARGE command. Page left open; tRP.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
WRITE OPERATION
tCKS tCMS COMMAND tCMH
WRITE
tCKH
ACTIVE
tCMS tCMH A0-A9
COLUMN ENABLE AUTO PRECHARGE
BA0,
DISABLE AUTO PRECHARGE BANK
BANK
tRCD
DON'T CARE
TIMING PARAMETERS
SYMBOL*
2.75 2.75
UNITS SYMBOL* tCKH
tCKS tCMH tCMS tRCD
UNITS
*CAS latency indicated parentheses.
NOTE: this example, burst length "Don't Care."
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00
Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.
64Mb: SDRAM
86-PIN PLASTIC TSOP (400 MIL)
22.22 ±.08 +.07 0.20 -.03 (2X)
DETAIL
2.80 (2X) 11.76 ±.10 10.16 ±.08
(2X) 1.00 (2X) +.03 -.02
+.10 -.05 1.20 DETAIL ±.10
NOTE:
dimensions millimeters typical where noted. Package width length include mold protrusion; allowable mold protrusion 0.025mm side.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron registered trademark Micron Technology, Inc.
64Mb: SDRAM 64MSDRAMx32_5.p65 Rev. 9/00 Micron Technology, Inc., reserves right change products specifications without notice. ©2000, Micron Technology, Inc.

SYNCHRONOUS DRAM PC100 functionality Fully synchronous; signals r

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