High-density board applications chip-to-chip intra system communicatio

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High-density board applications chip-to-chip intra system communicatio

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Fact Sheet MC92602FS/D Rev. 3/2003 Quad 1.25 Gbaud Reduced Interface SERDES
High-density board applications chip-to-chip intra system communications utilizing Ethernet protocol Blade applications with high number Ethernet ports High-speed data transfer applications high-bandwidth backplane chassis-to-chassis networking
OVERVIEW
Freescale Semiconductor, Inc.
MC92602 Quad high-speed, full-duplex, serializer/deserializer (SERDES) with four transceivers that transmit receive coded data rate gigabit second (Gbps) through each 1.25 gigabaud link. MC92602 built upon proven transceiver technology MC92600 Quad. designed with reduced width interfacing specifically high-density board applications where reduction number interface signals primary concern. Signal count reduced relative MC92600 device operating parallel interfaces Double Data Rate (DDR) 4-bits wide channel, direction. interface HSTL class-I, source terminated which accepted signaling method data FR-4 board traces inches. This aggressive signaling scheme offers excellent board density without making unreasonable signal integrity demands system logic which interfaces. Like predecessors, carefully designed power consumption nominally consumes less than with links operating full speed. MC92602 offered JEDEC standard body size package provide excellent board density applications with large number channels.
PRODUCT HIGHLIGHTS
Four full-duplex differential data links Selectable speed range: 1.25 Gbaud 0.625 Gbaud Rate adaption Ethernet packet streams Context sensitive rate adaption during receipt idle data code groups Supports Jumbo frame lengths bytes Supports frame bursting power: 1200 under typical conditions, while operating transceivers full speed Unused transceiver channels individually disabled reduce power consumption JTAG support full-speed built-in self test functions DATA INTERFACE Internal 8B/10B encoder/decoder that bypassed Ten-Bit Interface mode Double data rate (DDR), source synchronous, 4/5-bit data interfaces Transmit data clock selectable between per-channel transmit clock channel transmit clock Link-to-link synchronization supports aligned, multi-channel, word transfers. Synchronization mechanism tolerates 40-bit times link-to-link media delay Selectable Idle character alignment mode enables transfers with automatic realignment unaligned data transfers 10-bit mode) Received data clocked recovered clock reference clock frequencies LINK INTERFACE Links drive 50-ohm 75-ohm media (100- 150-ohm differential), backplane cable Link inputs have on-chip receiver link termination "hot-swap" compatible
More Information This Product, www.freescale.com
TECHNICAL SPECIFICATIONS
channels have: 8B/10B encoder/decoder that enabled bypassed Clock generation/recovery Independent, HSTL, 4/5-bit, interface with parallel-to-serial, serial-to-parallel conversion Idle/control character generation/detection Transceiver Links operate over 50-ohm 75-ohm media (100- 150-ohm differential) lengths meters FR-4 board/back-plane, meters coax external loop filter termination components required System BIST test modes with error counters Loopback BIST isolated from link inputs outputs IEEE 1149.1 JTAG boundary scan support Differential reference clock input with single-ended reference clock input option (125 max) Frequency offset tolerance between transmitter receiver excess Technology: High-performance 0.25 CMOS Process, five-layer metal
PARAMETRICS
Power Supply Core Power Supply: 0.15
HSTL Power Supply: 0.15 Link Power Supply: 0.15 Power Dissipation Typical operation: <300 channel maximum speed
PACKAGE
MAPBGA (15x15 body size, ball pitch)
Freescale Semiconductor, Inc.
Four transceivers
XMIT_x _[3:0] XMIT_x XMIT_x _CLK
Transmitter
Input Reg. Input Reg.
8B10B Encoder
XLINK_x_N
XLINK_x_P MEDIA
BIST
RECV_x_[3:0]
_Disable
Receiver Receiver Interface
MC92602 Block Diagram
Receiver
RECV_x_K RECV_x_E RECV_x_CLK
8B10B Decoder
RLINK_x
RLINK_x
RCCE, COMPA RECV_REF_A WSE, HSE, ADIE, TBIE BSYNC, DROP_SYNC T_0, T_1, STNDBY XMIT_A _REF, RESE
System
REF_CLK
REF_CLK_B
System Configuration Unit
JTAG Controller
TDI, TRST_B,
CONTACT INFORMATION
additional information this device, please contact Motorola SERDES Applications Phone: 480-814-2208 email: R4028C@motorola.com
MOTOROLA Stylized Logo registered Patent Trademark Office. other product service names property their respective owners. Motorola Inc. 2003 MC92602FS/D Rev. 03/2003
More Information This Product, www.freescale.com

High-density board applications chip-to-chip intra system communicatio

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