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MCF5407PB/D Rev. 3.3, 2/2003 MCF5407 Integrated ColdFire® Microprocessor Product Brief
This document overview MCF5407 ColdFire processor, focusing feature enhancements over MCF5307. includes general descriptions features various modules incorporated MCF5407. describes programming model implemented MCF5407.
Features
Harvard architecture memory system with 16-Kbyte instruction cache 8-Kbyte data cache Two, 2-Kbyte on-chip SRAMs Integer/fractional multiply-accumulate (MAC) unit Divide unit System debug interface DRAM controller synchronous asynchronous DRAM Four-channel controller general-purpose timers UARTs, that supports synchronous operations I2Cinterface Parallel interface System integration module (SIM)
MCF5407 integrated microprocessor combines Version ColdFire processor core with following components, shown Figure
Designed embedded control applications, MCF5407 delivers Dhrystone MIPS Dhrystone MIPS MHz.
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Features
COLDFIRE PROCESSOR COMPLEX JTAG
Branch Logic 8-Entry Branch Cache
Instruction Fetch Pipeline (IFP)
128-Entry Prediction Table
Ten-Instruction FIFO Buffer Operand Execution Pipeline (OEP)
LIFO Return Stack
Debug Module
PSTCLK
GeneralPurpose Registers A0-A7 D0-D7
SRAM Controller RAMBAR0 RAMBAR1 2-Kbyte SRAM0 2-Kbyte SRAM1 Local Memory Data
CLKIN on-chip peripherals)
Local Memory Instruction
Harvard Cache Controller CACR ACR2 ACR3 ACR0 ACR1 8-Kbyte Data Cache
CLKIN RSTI
PCLK RSTO
16-Kbyte Instruction Cache
4-Entry Store Buffer
SYSTEM INTEGRATION MODULE (SIM) Control
Parallel Port
System Control
SWIVR SYPCR SWSR
Base Address
MBAR
Master Park
MPARK
Four Channels Software Watchdog
DRAM Controller DRAM Control
Chip-Select Module
CSARs CSCRs CSMRs
External Interface
Interrupt Controller
ICRs IRQPAR
Module UARTs GeneralPurpose Timers
Addr/Cntrl
DACR0/1
Mask
DMR0/1
CS[7:0]
32-Bit Address 32-Bit Data
IRQ[1,3,5,7]
RAS[1:0] CAS[3:0]
Figure MCF5407 Block Diagram
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MCF5407 Features
Although MCF5407 offers obvious performance upgrade advantages, rich memory peripheral integration inexpensive prices should overlooked. Features common many embedded applications, such DMAs, various DRAM controller interfaces, on-chip memories, integrated cost-effective manner using aggressive process technologies. MCF5407 extends legacy Motorola's family providing compatible path ColdFire customers which development tools customer code quickly leveraged. fact, customers moving from ColdFire code translation emulation tools that facilitate modifying assembly code ColdFire architecture. package, pinout, integration MCF5407 create especially simple upgrade current MCF5307 designs with over triple system performance. revolutionary ColdFire microprocessor architecture provides levels price performance cost-sensitive markets. Based concept variable-length RISC technology, ColdFire family combines architectural simplicity conventional 32-bit RISC with memory-saving, variable-length instruction set. defining ColdFire architecture embedded processing applications, 68K-code compatible core created that combines performance advantages RISC architecture with optimum code density streamlined, variable-length M68000 instruction set. using variable-length instruction architecture, embedded system designers using ColdFire RISC processors enjoy significant advantages over conventional fixed-length RISC architectures. denser binary code ColdFire processors consumes less memory than many fixed-length instruction RISC processors available. This improved code density means more efficient system memory given application, allows slower, less costly memory help achieve target performance level. MCF5407 first standard product implement Version ColdFire microprocessor core. microarchitecture implements number advanced techniques, including Harvard memory architecture, branch cache acceleration logic, limited superscalar support (dual-instruction issue), which contribute Dhrystone MIPS performance level. Increasing internal speed core also allows higher performance while providing system designer with easy-to-use lower speed system interface. processor complex frequency integer multiple, times, external frequency. core clock stopped support low-power mode MCF5407. Serial communication channels provided programmable full-duplex UARTs, which provides synchronous communications soft-modem applications, interface module. Four channels allow fast data transfer using programmable burst mode independent processor execution. 16-bit general-purpose multimode timers provide separate input output signals. system protection, processor includes programmable 16-bit software watchdog timer. addition, common system functions such chip selects, interrupt control, arbitration, IEEE 1149.1 JTAG module included. sophisticated debug interface supports background-debug mode plus real-time trace debug with expanded on-chip breakpoint registers. This interface present ColdFire standard products allows common emulator support across entire family microprocessors.
MCF5407 Features
ColdFire processor core Variable-length RISC, clock-multiplied Version microprocessor core Implements Revision ColdFire instruction architecture (ISA), which leverages programming model
following list summarizes MCF5407 features:
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MCF5407 Features
independent decoupled pipelines: four-stage instruction fetch pipeline (IFP) five-stage operand execution pipeline (OEP) Ten-instruction FIFO buffer provides decoupling between pipelines Limited superscalar design achieves performance levels close dual-issue performance Programmable two-level branch acceleration mechanism with 8-entry branch cache plus 128-entry prediction table increased performance 32-bit internal address supporting Gbytes linear address space 32-bit data user-accessible, 32-bit-wide, general-purpose registers Supervisor/user modes system protection Vector base register relocate exception-vector table
Optimized high-level language constructs Multiply accumulate unit (MAC) Provides high-speed, complex arithmetic processing applications Tightly coupled Three-stage execute pipeline with clock issue rate operations Supports multiplies, with 32-bit accumulate Supports signed unsigned integers, plus signed fractional operands Hardware integer divide unit Supports unsigned signed integer divides Tightly coupled Supports 32/16, 32/32 operations producing quotient and/or remainder results 16-Kbyte instruction cache, 8-Kbyte data cache Four-way set-associative organization Operates higher processor core frequency Provides pipelined, single-cycle access critical code data Data cache supports write-through copyback modes Four-entry, 32-bit store buffer improve performance operand writes Two, 2-Kbyte SRAMs Programmable location anywhere within 4-Gbyte linear address space Operates higher core frequency Provides pipelined, single-cycle access critical code and/or data Each block mapped either instruction data operand controller Four fully-programmable channels: support external requests external acknowledges Supports dual-address single-address transfers with 16-, 32-bit data capability Source/destination address pointers that increment remain constant 24-bit transfer counter channel
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MCF5407 Features
Operand packing unpacking supported Auto-alignment transfers supported efficient block movement Supports bursting cycle steal Provides clock internal access Automatic transfers from on-chip UARTs using internal interrupts DRAM controller Support synchronous DRAM (SDRAM), extended-data-out (EDO) DRAM, fast page mode Supports Mbytes DRAM Programmable timer provides CAS-before-RAS refresh asynchronous DRAMs Support separate memory blocks
UARTs UART offers synchronous mode with expanded buffers soft modem support Full-duplex operation Flexible baud-rate generator Modem control signals available (CTS, RTS) Processor-interrupt capability
Dual 16-bit general-purpose multiple-mode timers 8-bit prescaler Timer input output pins Processor-interrupt capability 18.5-nS resolution
module Interchip interface EEPROMs, controllers, converters, keypads Fully compatible with industry-standard Master slave modes support multiple masters Automatic interrupt generation with programmable level
System interface module (SIM) Chip selects provide direct interface 16-, 32-bit SRAM, ROM, FLASH, memory-mapped devices Eight, fully-programmable chip selects, each with base address register Programmable wait states port sizes chip select User-programmable processor clock/input clock frequency ratio Programmable interrupt controller interrupt latency Four external interrupt request inputs Programmable autovector generator Software watchdog timer
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ColdFire Module Description
16-bit general-purpose interface IEEE 1149.1 test (JTAG) module System debug support Real-time trace determining dynamic execution path while emulator mode Background debug mode (BDM) debug features while halted Real-time debug support, including user-visible hardware breakpoint registers Supports servicing critical, real-time interrupt requests while emulator mode Supports comprehensive emulator functions through trace breakpoint logic
On-chip Accepts various clock input (CLKIN) frequencies between Supports core frequencies between Supports low-power mode
Product offerings Dhrystone MIPS Dhrystone MIPS Implemented 0.22 quad-layer-metal process technology with 1.8-V operation (3.3-V compliant pads) 208-pin plastic package operating temperature operating temperature
1.2.1
Process
MCF5407 manufactured 0.22-µ CMOS process with quad-layer-metal routing technology. This process combines high performance power needed embedded system applications. Inputs 3.3-V tolerant; outputs CMOS open-drain CMOS with outputs operating from with guaranteed TTL-level specifications.
1.3.1
ColdFire Module Description
ColdFire Core
following sections provide overviews various modules incorporated MCF5407.
Version ColdFire core consists two, independent decoupled pipelines maximize performance-the instruction fetch pipeline (IFP) operand execution pipeline (OEP).
1.3.1.1
Instruction Fetch Pipeline (IFP)
four-stage instruction fetch pipeline (IFP) designed prefetch instructions operand execution pipeline (OEP). Because fetch execution pipelines decoupled ten-instruction FIFO buffer, fetch mechanism prefetch instructions advance their OEP, thereby minimizing
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ColdFire Module Description
time stalled waiting instructions. maximize performance conditional branch instructions, Version implements sophisticated two-level acceleration mechanism. first level 8-entry, direct-mapped branch cache with 2-bit prediction state (strongly/weakly, taken/not-taken) each entry. branch cache implements instruction folding techniques that allow conditional branch instructions which predicted correctly taken execute zero cycles. those conditional branches with information branch cache, second-level, direct-mapped prediction table containing entries accessed. Again, each entry uses same 2-bit prediction state definition branch cache. This branch prediction state then used predict direction prefetched conditional branch instructions. Other change-of-flow instructions, including unconditional branches, jumps, subroutine calls, similar mechanism where calculates target address. performance subroutine return instructions improved through four-entry, LIFO return stack.
cases, these mechanisms allow redirect fetch stream down path predicted taken well advance actual instruction execution. effect significantly improved performance.
1.3.1.2
Operand Execution Pipeline (OEP)
prefetched instruction stream gated from FIFO buffer into five-stage OEP. consists two, traditional two-stage RISC compute engines with register file access feeding arithmetic/logic unit (ALU). compute engine located typically used operand memory address calculations (the address ALU), while compute engine located bottom pipeline used instruction execution (the execution ALU). resulting structure provides Gbytes/S data operand bandwidth compute engines supports single-cycle execution speeds most instructions, including load, store most embedded-load operations. response users developers, design supports execution ColdFire Revision instruction set, which adds small number instructions improve performance code density. also implements advanced performance features. dynamically determines appropriate location instruction execution (either address execution ALU) based pipeline state. address compute engine, conjunction with register renaming resources, used execute number heavily-used opcodes forward results subsequent instructions without pipeline stalls. Additionally, implements instruction folding techniques involving MOVE instructions that instructions issued single machine cycle. resulting microarchitecture approaches performance full superscalar implementation, much lower silicon cost.
1.3.1.3
Module
unit provides signal processing capabilities MCF5407 variety applications including digital audio servo control. Integrated execution unit processor's OEP, unit implements three-stage arithmetic pipeline optimized multiplies. Both 32-bit input operands supported this design addition full extensions signed unsigned integers plus signed, fixed-point fractional input operands.
1.3.1.4
Integer Divide Module
Some embedded applications benefit greatly from integer divide unit. Integrated another engine processor's OEP, divide module performs variety operations using signed unsigned integers. module supports word longword divides producing quotients and/or remainders.
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ColdFire Module Description
1.3.2
Harvard Architecture
Harvard memory architecture implemented support increased bandwidth requirements processor pipelines. this design featuring separate instruction data buses processor-local memories, available bandwidth processor reaches Gbytes/S conflicts between instruction fetches operand accesses removed.
1.3.2.1
16-Kbyte Instruction Cache/8-Kbyte Data Cache
Attached Harvard memory architecture 16-Kbyte instruction cache 8-Kbyte data cache. These four-way, set-associative designs improve system performance providing pipelined, single-cycle access instruction fetches operand accesses that these memories. with ColdFire caches, these controllers implement non-lockup, streaming design maximize performance. processor-local memories decouples performance from external memory speeds increases available bandwidth external devices on-chip 4-channel DMA. Both caches implement line-fill buffers optimize performance line-sized (16-byte) burst accesses. Additionally, data cache supports operation copyback, write-through noncacheable modes. 4-entry, 32-bit buffer used cache line push operations configured deferred write buffering while write-through non-cacheable modes. INTOUCH instruction used prefetch instructions locked instruction cache using cache locking feature. This function desirable certain systems where deterministic real-time performance critical.
1.3.2.2
Internal 2-Kbyte SRAMs
2-Kbyte on-chip SRAM modules also connected Harvard memory architecture, provide pipelined, single-cycle access those memory regions mapped these devices. Each memory independently mapped 0-modulo-2K location within 4-Gbyte address space, configured respond either instruction data accesses. Time-critical functions mapped onto instruction memory bus, while system stack and/or heavily-referenced data operands mapped onto data memory bus.
1.3.3
DRAM Controller
MCF5407 DRAM controller provides direct interface blocks DRAM. controller supports 16-, 32-bit memory widths, easily interface PC-100 DIMMs. unique addressing scheme allows increases system memory size without rerouting address lines rewiring boards. controller operates normal mode page mode supports SDRAMs DRAMs.
1.3.4
Controller
MCF5407 provides four fully-programmable channels quick data transfer. Dual- single-address modes provide ability program bursting cycle steal. Data transfers bits long with packing unpacking supported along with auto-alignment option efficient block transfers. Automatic block transfers from on-chip serial UARTs also supported through channels.
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ColdFire Module Description
1.3.5
UART Modules
MCF5407 contains UARTs, which function independently. UART been enhanced provide synchronous operation CODEC interface soft modem support. Each UART clocked system clock, eliminating need external crystal. Each UART module interfaces directly CPU, shown Figure
Serial Communications Channel System clock External clock (TIN)
16-Bit Timer Baud-Rate Generation
Internal Channel Control Logic
Interrupt Control Logic
Figure UART Module Block Diagram
Each UART module consists following major functional areas: Serial communication channel 16-bit timer baud-rate generation Internal channel control logic Interrupt control logic
addition, UART1 enhanced provide CODEC interface soft modem support. UART1 programmed function like UART0 three following modem modes: 8-bit CODEC interface 16-bit CODEC interface audio CODEC (AC97) digital interface controller
Each UART contains on-chip baud-rate generator, which provides both standard nonstandard baud rates. Data formats bits with even, odd, parity, stop bits 1/16 increments. UARTs include following transmit receive FIFO buffers: UART0 4-byte FIFO receive buffer 2-byte FIFO transmit buffer. UART1, FIFOs hold following: 1-byte samples when programmed UART 8-bit CODEC interface 2-byte samples when programmed 16-bit CODEC interface 20-bit samples when programmed Digital Controller
UART modules also provide several error-detection maskable-interrupt capabilities. Modem support includes request-to-send (RTS) clear-to-send (CTS) lines.
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ColdFire Module Description
CLKIN provides time base through programmable prescaler. UART time scale also sourced from timer input. Full-duplex, auto-echo loopback, local loopback, remote loopback modes allow testing UART connections. programmable UARTs interrupt various normal error-condition events.
1.3.6
Timer Module
timer module includes general-purpose timers, each which contains free-running 16-bit timer three modes. mode captures timer value with external event. Another mode triggers external signal interrupts when timer reaches value, while third mode counts external events. timer unit 8-bit prescaler that allows programming clock input frequency, which derived from system cycle external clock input (TIN). programmable timer-output generates either active-low pulse toggles output.
1.3.7
Module
interface two-wire, bidirectional serial used quick data exchanges between devices. minimizes interconnection between devices system best suited applications that need occasional bursts rapid communication over short distances among several devices. operate master, slave multiple-master modes.
1.3.8
System Interface
MCF5407 processor provides direct interface 16-, 32-bit FLASH, SRAM, ROM, peripheral devices through fully-programmable chip selects write enables. Support burst ROMs also included. Through on-chip PLL, users input slower clock MHz) that internally multiplied create faster processor clock (100 MHz).
1.3.8.1
External Interface
interface controller transfers information between ColdFire core DMA, memory, peripherals, other devices external bus. external interface provides bits address space, 32-bit data bus, associated control signals. This interface implements extended synchronous protocol that supports bursting operations. Simple two-wire request/acknowledge arbitration between MCF5407 processor another master, such external device, glueless with arbitration logic internal MCF5407 processor. Multiple-master arbitration also available with some simple external arbitration logic.
1.3.8.2
Chip Selects
Eight fully-programmable chip select outputs support external memory peripheral circuits with user-defined wait-state insertion. These signals interface 16-, 32-bit ports. base address, access permissions, internal transfer terminations programmable with configuration registers each chip select. also provides global chip select functionality boot upon reset initializing MCF5407.
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ColdFire Module Description
1.3.8.3
16-Bit Parallel Port Interface
16-bit general-purpose programmable parallel port serves either input output pin-by-pin basis.
1.3.8.4
Interrupt Controller
interrupt controller provides user-programmable control internal peripheral interrupts implements four external fixed interrupt-request pins. Each internal interrupt programmed seven interrupt levels four priority levels within each these levels. Additionally, external interrupt request pins mapped levels levels Autovector capability available both internal external interrupts.
1.3.8.5
JTAG
help with system diagnostics manufacturing testing, MCF5407 processor includes dedicated user-accessible test logic that complies with IEEE 1149.1a standard boundary-scan testability, often referred Joint Test Action Group, JTAG. more information, refer IEEE 1149.1a standard.
1.3.9
System Debug Interface
ColdFire processor core debug interface provided support system debugging conjunction with low-cost debug emulator development tools. Through standard debug interface, users access real-time trace debug information. This allows processor system debugged full speed without need costly in-circuit emulators. debug unit contained MCF5407 compatible upgrade MCF52xx MCF53xx debug modules with added breakpoint registers support interrupt request servicing while emulator mode. on-chip breakpoint resources include total programmable registers-two sets address registers (each with 32-bit registers), sets data registers (each with 32-bit data register plus 32-bit data mask register), 32-bit register plus 32-bit mask register three additional 32-bit registers. These registers accessed through dedicated debug serial communication channel, from processor's supervisor mode programming model. breakpoint registers configured generate triggers combining address, data conditions variety single dual-level definitions trigger event programmed generate processor halt, initiate debug interrupt exception. MCF5407's interrupt servicing options during emulator mode allow real-time critical interrupt service routines serviced while processing debug interrupt event, thereby ensuring that system continues operate even during debugging. support program trace, Version debug module combined processor status debug data outputs into single 8-bit (PSTDDATA[7:0]). This along with PSTCLK output provide execution status, captured operand data branch target addresses defining processor activity one-half CPU's clock rate.
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Programming Model, Addressing Modes, Instruction
1.3.10 Module
MCF5407 module shown Figure
CLKIN on-chip peripherals) BCLKO
CLKIN DIVIDE[2:0] RSTI
PCLK core)
Debug Module
RSTO PSTCLK PCLK/2)
Figure Module
module's three modes operation (reset, normal, reduced power) described follows. Reset mode-When RSTI asserted, enters reset mode. reset, asserts RSTO from MCF5407. core:bus frequency ratio along with other MCF5407 configuration information sampled during reset. Normal mode-In normal mode, input frequency programmed reset clock-multiplied provide processor clock (PCLK). Reduced-power mode-In reduced-power mode, PCLK disabled executing sequence including programming control system configuration register (SCR) then executing STOP instruction. Register contents retained reduced-power mode, system reenabled quickly when unmasked interrupt reset detected.
Programming Model, Addressing Modes, Instruction
ColdFire programming model separated into privilege modes-supervisor user, which indicated status register (SR). processor identifies logical address accessing either supervisor user address space, which differentiates between supervisor user modes. User mode-When processor user mode (SR[S] only subset registers accessed privileged instructions cannot executed. Typically, most application processing occurs user mode. Entry into user mode usually accomplished executing return from exception instruction (RTE) (assuming value SR[S] saved stack MOVE, instruction (assuming SR[S] Supervisor mode-Supervisor mode protects system resources from uncontrolled access users. supervisor mode, complete access registers entire ColdFire instruction provided. Typically, system programmers supervisor programming model implement operating system functions provide control. supervisor programming model provides access same registers user model, plus additional registers configuring on-chip system resources, described Section 1.4.3, "Supervisor Registers." Exceptions (including interrupts) handled supervisor mode.
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Programming Model, Addressing Modes, Instruction
1.4.1
Programming Model
Figure shows MCF5407 programming model.
Data registers
Address registers
User Registers
Stack pointer Program counter Condition code register status register accumulator mask register Status register Vector base register Cache control register Access control register (data) Access control register (data) Access control register (instruction) Access control register (instruction) Module base address register base address register base address register
MACSR MASK
Supervisor Registers
(CCR) Must zeros
CACR ACR0 ACR1 ACR2 ACR3 MBAR RAMBAR0 RAMBAR1
Figure ColdFire MCF5407 Programming Model
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Programming Model, Addressing Modes, Instruction
1.4.2
User Registers
Table User-Level Registers
user programming model, shown Figure summarized Table
Register Data registers (D0-D7) Description These 32-bit registers bit, byte, word, longword operands. They also used index registers.
Address registers These 32-bit registers serve software stack pointers, index registers, base address registers. (A0-A7) base address registers used word longword operations. functions hardware stack pointer during stacking subroutine calls exception handling. Program counter (PC) Contains address instruction currently being executed MCF5407 processor. lower byte contains indicator flags that reflect result previous operation used conditional instruction execution.
Condition code register (CCR)
status Defines operating configuration unit contains indicator flags from results register (MACSR) instructions. Accumulator (RACC) Mask register (RMASK) General-purpose register used accumulate results operations. General-purpose register provides optional address mask instructions that fetch operands from memory. useful implementation circular queues operand memory.
1.4.3
Supervisor Registers
Table Supervisor-Level Registers
Table summarizes MCF5407 supervisor-level registers.
Register Status register (SR) Description upper byte provides interrupt information addition variety mode indicators signaling operating state ColdFire processor. lower byte CCR, shown Figure Defines upper bits base address exception vector table used during exception processing. low-order bits forced zero, locating vector table 0-modulo-1 Mbyte address. Defines operating modes Version cache memories. Control fields configuring instruction, data branch cache provided this register, along with default attributes 4-Gbyte address space. Define address ranges attributes associated with various memory regions within 4-Gbyte address space. Each defines location given memory region assigns attributes such write-protection cache mode (copyback, write-through, cacheability). ACR0 ACR1 support data memory; ACR2 ACR3 support instruction memory. Additionally, CACR fields assign default attributes instruction data memory spaces. Provide logical base address 2-Kbyte SRAM modules define attributes access types allowed corresponding SRAM. Defines logical base address memory-mapped space containing control registers on-chip peripherals.
Vector base register (VBR) Cache configuration register (CACR) Access control registers (ACR0/1, ACR2/3)
base address registers (RAMBAR0, RAMBAR1) Module base address register (MBAR)
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Programming Model, Addressing Modes, Instruction
1.4.4
Addressing Modes
Operands signed unsigned contained registers, memory, instructions themselves. operand specifiers size each operation either explicitly encoded instruction implicitly defined instruction's definition. Table shows MCF5407 data formats.
Table MCF5407 Data Formats
Data Format Byte Word Longword Size bits bits bits
Table shows notational conventions used throughout this document.
Table Notational Conventions
Instruction Operand Syntax Opcode Wildcard Logical condition (example: equal) Register Specifications Ay,Ax Dy,Dx Ry,Rx address register (example: address register Source destination address registers, respectively data register (example: data register Source destination data registers, respectively control register (example vector base register) registers (ACC, MAC, MASK) address data register Destination register (used instructions only) source destination registers, respectively index register (can address data register: Register Names MACSR MASK accumulator register Condition code register (lower byte status register mask register Program counter Status register Port Name PSTDDATA Processor status.debug data port
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Programming Model, Addressing Modes, Instruction Table Notational Conventions (continued)
Instruction Operand Syntax Miscellaneous Operands #<data> <ea> <ea>y,<ea>x <label> <list> <shift> <size> Immediate data following 16-bit operation word instruction Effective address Source destination effective addresses, respectively Assembly language program label List registers MOVEM instruction (example: D3-D0) Shift operation: shift left (<<), shift right (>>) Operand data size: byte (B), word (W), longword Both instruction data caches Data cache Instruction cache Identifies 4-bit vector number trap instructions identifies indirect data address referencing memory identifies absolute address referencing memory Signal displacement value, bits wide (example: 16-bit displacement) Scale factor (x1, indexed addressing mode, <<1n>> operations) Operations sign-extended Arithmetic addition postincrement indicator Arithmetic subtraction predecrement indicator Arithmetic multiplication Arithmetic division Invert; operand logically complemented Logical Logical Logical exclusive Shift left (example: shift left bits) Shift right (example: shift right bits) Source operand moved destination operand operands exchanged bits upper portion made equal high-order lower portion
<vector> <xxx>
<condition> Test condition. true, operations after `then' performed. condition false then <operations> optional `else' clause present, operations after `else' performed. condition false else <operations> else omitted, instruction performs operation. Refer instruction description example.
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Programming Model, Addressing Modes, Instruction Table Notational Conventions (continued)
Instruction Operand Syntax Subfields Qualifiers Address Optional operation Identifies indirect address Displacement value, n-bits wide (example: 16-bit displacement) Calculated effective address (pointer) selection (example: Least significant (example: Least significant byte Least significant word Most significant Most significant byte Most significant word Condition Code Register Names Carry Negative Overflow Extend Zero
1.4.4.1
Addressing Capability Summary
MCF5407 processor supports seven addressing modes (refer Table Register indirect addressing modes support postincrement, predecrement, offset, indexing, which particularly useful handling data structures common sophisticated embedded applications high-level languages. program counter indirect mode also indexing offset capabilities. This addressing mode typically required support position-independent code. part indexed addressing mode, ColdFire architecture supports optional scale factor that applied index register easily access byte, word, longword entries within array (x1, x4). instruction's effective addressing mode specify operand three ways: specify data value directly immediate operand specify register containing operand specify addressing calculation needed reference memory location containing operand
Each addressing mode unique assembler syntax. addition generalized format where addressing mode specified directly instruction, some opcodes implicitly define effective address. Table summarizes supported effective addressing modes.
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Programming Model, Addressing Modes, Instruction Table ColdFire Effective Addressing Modes
Addressing Modes Register direct Data Address Syntax Mode Field Reg. Field Category Data Memory Control Alterable
reg. reg. reg. reg. reg. reg. reg.
Register indirect Address (An) Address with Postincrement (An)+ Address with Predecrement -(An) Address with Displacement (d16,
Address register indirect with scaled index 8-bit displacement Program counter indirect with displacement Program counter indirect with scaled index 8-bit displacement Absolute data addressing Short Long Immediate
(d8, Xi*SF) (d16, (d8, Xi*SF) (xxx).W (xxx).L #<xxx>
Table lists addressing modes MOVE instructions. Table Specific Effective Addressing Modes MOVE Instructions
Source <EA> (Ay) (Ay)+ -(Ay) Destination <EA>
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Programming Model, Addressing Modes, Instruction Table Specific Effective Addressing Modes MOVE Instructions (continued)
Source <EA> (d16,Ay) (d16,PC) Destination <EA> (Ax) (Ax)+ -(Ax) (d16,Ax) (Ax) (Ax)+ -(Ax) (Ax) (Ax)+ -(Ax) (Ax) (Ax)+ -(Ax) (d16,Ax)
(d8,Ay,Xi*SF) (d8,PC,Xi*SF)
(xxx).W (xxx).L
#<data>
Note that this applies only move.b move.w instructions
Table lists additional addressing variants. Table Addressing Variants Used Certain Instructions
Addressing Variant <ea-1> Allowable Modes (An) (An)+ -(An) (d16,An) (An) (d16,An) (An) (d16,An) (d8,An,Xi*SF) (xxx).W (xxx).L (d16,PC) (d8,PC,Xi*SF)
<ea-2> <ea-3>
1.4.5
Instruction
Version ColdFire core implements Revision instruction set, which adds opcodes enhance support byte- word-sized operands position-independent code. ColdFire instruction supports high-level languages optimized those instructions most commonly generated compilers embedded applications. Table Table provide alphabetized listing ColdFire
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Programming Model, Addressing Modes, Instruction
instruction opcodes, supported operation sizes, assembler syntax. two-operand instructions, first operand syntax generally source operand, second operand destination. Because ColdFire architecture provides upgrade path customers, instruction supports most common opcodes. majority instructions binary compatible optimized opcodes. This feature, when coupled with code conversion tools from third-party developers, generally minimizes software porting issues customers with applications. following list summarizes enhanced instructions Revision ISA: instructions: INTOUCH loads blocks instructions locked instruction cache MOV3Q.L moves 3-bit immediate data destination location MVS.{B,W} sign-extends source operand moves destination register MVZ.{B,W} zero-fills source operand moves destination register SATS.L updates destination register depending overflow TAS.B tests byte operand being addressed. Enhancements existing Revision instructions: Longword support branch instructions (Bcc, BRA, BSR) Byte word support compare instructions (CMP, CMPI) Byte longword support MOVE.x where source type #<data> destination type d16(Ax); that move.b #<data>, d16(Ax)
Table ColdFire Extension Summary
Instruction Branch Always Branch Conditionally Branch Subroutine Compare Compare Immediate Instruction Fetch Touch Move 3-Bit Data Quick Move Data Source Destination Move with Sign Extend Move with Zero-Fill Signed Saturate Test Operand Mnemonic bra.l bcc.l bsr.l cmp.{b,w} cmpi.{b,w} intouch mov3q.l move.{b,w} mvs.{b,w} mvz.{b,w} sats.l tas.b
Table lists enhanced instructions.
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Programming Model, Addressing Modes, Instruction
Table describes supervisor-level instructions.
Table Supervisor-Level Instruction Summary
Instruction CPUSHL Operand Syntax (An) Operand Size Unsized Operation Invalidate instruction cache line Push invalidate data cache line Push data cache line invalidate (I,D)-cache lines Enter halted state Touch instruction space address Source Register Definition 0x002 Cache control register (CACR) 0x004 Access control register (ACR0) 0x005 Access control register (ACR1) 0x006 Access control register (ACR2) 0x007 Access control register (ACR3) 0x801 Vector base register (VBR) 0xC04 base address register (RAMBAR0) 0xC05 base address register (RAMBAR1) (SP+2) SP+4 (SP) formatfield Immediate data enter stopped state <ea-2>y debug module
HALT INTOUCH MOVE from MOVE MOVEC
none (Ax) Dy,SR #<data>,SR Ry,Rc
Unsized Unsized
STOP WDEBUG
None #<data> <ea-2>y
Unsized
HALT instruction configured allow user-mode execution setting CSR[UHE].
Table describes user-level instructions.
Table User-Level Instruction Summary
Instruction ADDA ADDI ADDQ ADDX ANDI BCHG Operand Syntax Dy,<ea>x <ea>y,Dx <ea>y,Ax #<data>,Dx #<data>,<ea>x Dy,Dx Dy,<ea>x <ea>y,Dx #<data>,Dx Dy,Dx #<data>,Dx Dy,Dx #<data>,Dx <label> Dy,<ea>x #<data>,<ea-1>x .B,.W,.L .B,.L .B,.L Operand Size Operation Source destination destination Source destination destination Immediate data destination destination Immediate data destination destination Source destination destination Source destination destination Immediate data destination destination #<data>) #<data>) condition true, then ~(<bit number> destination) destination
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Programming Model, Addressing Modes, Instruction Table User-Level Instruction Summary (continued)
Instruction BCLR BSET BTST Operand Syntax Dy,<ea>x #<data>,<ea-1>x <label> Dy,<ea>x #<data>,<ea-1>x <label> Dy,<ea>x #<data>,<ea-1>x <ea>y,Dx <ea>y,Ax <ea>y,Dx <ea>y,Dx <ea-1>y,Dx <ea>y,Dx <ea-1>y,Dx Dy,<ea>x Dy,<ea>x #<data>,Dx #<data>,Dx None <ea-3>y <ea-3>y <ea-3>y,Ax Ax,#<d16> Dy,Dx #<data>,Dx Dy,Dx #<data>,Dx Ry,RxSF Ry,RxSF,<ea-1>y,Rw .B,.L .B,.L .B,.W,.L .B,.L .B,.L .B,.W,.L .B,.L .B,.L .B,.W,.L .B,.W,.L .B,.W,.L .B,.W,.L Unsized Unsized Unsized .B,.W,.L Operand Size Operation ~(<bit number> destination) destination ~(<bit number> destination) destination next sequential (SP); ~(<bit number> destination) destination Destination source Destination source Destination immediate data /<ea>y {16-bit remainder; 16-bit quotient} /<ea>y {32-bit quotient} Signed operation /<ea>y {16-bit remainder; 16-bit quotient} /<ea>y {32-bit quotient} Unsigned operation Source destination destination Immediate data destination destination Sign-extended destination destination Sign-extended destination destination Enter halted state Address <ea> next sequential (SP); <ea> <ea> (SP); #<data>) #<data>) Rx){<< Rx){<< ACC; (<ea>y{&MASK}) Rx){<< Rx){<< ACC; (<ea-1>y{&MASK}) 3-bit immediatedestination <ea>y <ea>x
CMPA CMPI DIVS
DIVU
EORI EXTB HALT LINK MACL
MOV3Q MOVE
#<data>,<ea>x <ea>y,<ea>x
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Programming Model, Addressing Modes, Instruction Table User-Level Instruction Summary (continued)
Instruction MOVE from Operand Syntax MASK,Rx ACC,Rx MACSR,Rx MACSR,CCR MOVE Ry,ACC Ry,MACSR Ry,MASK #<data>,ACC #<data>,MACSR #<data>,MASK Operand Size Operation
MACSR
#<data>
MOVE from MOVE MOVEA MOVEM MOVEQ MSAC MSACL MULS MULU NEGX PULSE REMS REMU
CCR,Dx Dy,CCR #<data>,CCR <ea>y,Ax #<list>,<ea-2>x <ea-2>y,#<list> #<data>,Dx Ry,RxSF Ry,RxSF,<ea-1>y,Rw <ea>y,Dx <ea>y,Dx <ea>y,Dx <ea-1>y,Dx none <ea>y,Dx Dy,<ea>x #<data>,Dx <ea-3>y none <ea-1>,Dx <ea-1>,Dx none
.W,.L .B,.W .B,.W Unsized Unsized Unsized
#<data> Source destination Listed registers destination Source listed registers Sign-extended immediate data destination Rx){<< Rx){<< ACC; (<ea-1>y{&MASK}) Source destination destination Signed operation Source destination destination Unsigned operation Sign-extended source destination Zero-filled source destination destination destination destination destination Synchronize pipelines; Destination destination Source destination destination Immediate data destination destination Address <ea> (SP) PST= Dx/<ea>y {32-bit remainder} Signed operation Dx/<ea>y {32-bit remainder} Unsigned operation (SP)
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General Device Information Table User-Level Instruction Summary (continued)
Instruction SATS Operand Syntax Operand Size CCR.V=1, then Dx[31] then 0x80000000 else 0x7FFFFFFF else unchanged condition true, then destination; Else destination Destination source destination Destination source destination Destination immediate data destination Destination immediate data destination Destination source destination CCR; <ea>x SP;PC (SP); SP;SR (SP); format (SP); Vector address condition codes (SP) <ea>y DDATA port Operation
SUBA SUBI
<ea>y,Dx Dy,<ea>x <ea>y,Ax #<data>,Dx #<data>,<ea>x Dy,Dx <ea>x #<vector>
Unsized
SUBQ SUBX SWAP TRAP
TRAPF
None #<data> <ea>y <ea>y
Unsized .B,.W,.L Unsized .B,.W,.L
UNLK WDDATA
default HALT instruction supervisor-level instruction; however, configured allow user-mode execution setting CSR[UHE].
General Device Information
Table MCF5407 Package/Frequency
Package plastic plastic Operating Temperature Frequency CLKIN/ PCLK CLKIN/ PCLK
Table shows MCF5407 package, temperature, frequency specifications,
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Table lists additional MCF5407 documentation.
Table Documentation
Documentation Number MCF5407UM/AD MCF5200PRM/AD MCF5407 User's Manual Application Note: Migrating from ColdFire MCF5307 MCF5407 ColdFire Family Programmer's Reference Manual Documentation Title
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