This document provides overview MCF5307 ColdFire processor. includes g

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MCF5307PB/D Rev. 1/2002 MCF5307 Integrated Microprocessor Product Brief
This document provides overview MCF5307 ColdFire processor. includes general descriptions modules features incorporated MCF5307.
Features
8-Kbyte unified cache 4-Kbyte on-chip SRAM Integer/fractional multiply-accumulate (MAC) unit Divide unit System debug interface DRAM controller synchronous asynchronous DRAM Four-channel controller general-purpose timers UARTs I2Cinterface Parallel interface System integration module (SIM)
MCF5307 integrated microprocessor combines ColdFire processor core with following components, shown Figure
Designed embedded control applications, MCF5307 delivers Dhrystone MIPS while minimizing system costs.
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Features
COLDFIRE PROCESSOR COMPLEX JTAG Instruction Unit
Branch Logic GeneralPurpose Registers A0-A7
Instruction Fetch Pipeline (IFP)
Eight-Instruction FIFO Buffer Operand Execution Pipeline (OEP)
D0-D7
DSOC AGEX
Debug Module Local Memory
PSTCLK
SRAM Controller RAMBAR
BCLKO (sent off-chip on-chip peripherals)
4-Kbyte SRAM Cache Controller CACR ACR0 ACR1 8-Kbyte Cache
CLKIN RSTI
PCLK RSTO
Local Memory
4-Entry Store Buffer
SYSTEM INTEGRATION MODULE (SIM) Control
Parallel Port
System Control
SWIVR SYPCR SWSR
Base Address
MBAR
Master Park
MPARK
Four Channels Software Watchdog
DRAM Controller DRAM Control
Chip-Select Module
CSARs CSCRs CSMRs
External Interface
Interrupt Controller
ICRs IRQPAR
Module UARTs GeneralPurpose Timers
Addr/Cntrl Mask
DACR0/1 DMR0/1
DRAM Controller Outputs CS[7:0]
32-Bit Address 32-Bit Data Control Signals
IRQ[1,3,5,7]
Figure MCF5307 Block Diagram
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MOTOROLA
MCF5307 Features
Features common many embedded applications, such DMAs, various DRAM controller interfaces, on-chip memories, integrated using advanced process technologies. MCF5307 extends legacy Motorola's family providing compatible path ColdFire customers which development tools customer code leveraged. fact, customers moving from ColdFire code translation emulation tools that facilitate modifying assembly code ColdFire architecture. Based concept variable-length RISC technology, ColdFire family combines architectural simplicity conventional 32-bit RISC with memory-saving, variable-length instruction set. defining ColdFire architecture embedded processing applications, 68K-code compatible core combines performance advantages RISC architecture with optimum code density streamlined, variable-length M68000 instruction set.
using variable-length instruction architecture, embedded system designers using ColdFire RISC processors enjoy significant advantages over conventional fixed-length RISC architectures. denser binary code ColdFire processors consumes less memory than many fixed-length instruction RISC processors available. This improved code density means more efficient system memory given application allows slower, less costly memory help achieve target performance level. MCF5307 first standard product implement Version ColdFire microprocessor core. reach higher levels frequency performance, numerous enhancements were made architecture. Most notable deeper instruction pipeline, branch acceleration, unified cache, which together provide (Dhrystone 2.1) MIPS MHz. Increasing internal speed core also allows higher performance while providing system designer with easy-to-use lower speed system interface. processor complex frequency integer multiple, times, external frequency. core clock stopped support low-power mode. Serial communication channels provided interface module programmable full-duplex UARTs. Four channels allow fast data transfer using programmable burst mode independent processor execution. 16-bit general-purpose multimode timers provide separate input output signals. system protection, processor includes programmable 16-bit software watchdog timer. addition, common system functions such chip selects, interrupt control, arbitration, IEEE 1149.1 JTAG module included. sophisticated debug interface supports background-debug mode plus real-time trace debug with expanded flexibility on-chip breakpoint registers. This interface present ColdFire standard products allows common emulator support across entire family microprocessors.
MCF5307 Features
ColdFire processor core Variable-length RISC, clock-multiplied Version microprocessor core Fully code compatible with Version processors independent decoupled pipelines: four-stage instruction fetch pipeline (IFP) two-stage operand execution pipeline (OEP) Eight-instruction FIFO buffer provides decoupling between pipelines Branch prediction mechanisms accelerating program execution 32-bit internal address supporting Gbytes linear address space
following list summarizes MCF5307 features:
MOTOROLA
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MCF5307 Features
32-bit data user-accessible, 32-bit-wide, general-purpose registers Supervisor/user modes system protection Vector base register relocate exception-vector table Optimized high-level language constructs Multiply accumulate unit (MAC) High-speed, complex arithmetic processing applications Tightly coupled Three-stage execute pipeline with clock issue rate operations multiplies support, with 32-bit accumulate Signed unsigned integer support, plus signed fractional operands Hardware integer divide unit Unsigned signed integer divide support Tightly coupled 32/16 32/32 operation support producing quotient and/or remainder results 8-Kbyte unified cache Four-way set-associative organization Operates higher processor core frequency Provides pipelined, single-cycle access critical code data Supports write-through copyback modes Four-entry, 32-bit store buffer improve performance operand writes 4-Kbyte SRAM Programmable location anywhere within 4-Gbyte linear address space Higher core-frequency operation Pipelined, single-cycle access critical code data controller Four fully programmable channels: support external requests Dual-address single-address transfer support with 16-, 32-bit data capability Source/destination address pointers that increment remain constant 24-bit transfer counter channel Operand packing unpacking supported Auto-alignment transfers supported efficient block movement Bursting cycle steal support Two-bus-clock internal access Automatic transfers from on-chip UARTs using internal interrupts DRAM controller Synchronous DRAM (SDRAM), extended-data-out (EDO) DRAM, fast page mode support
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MOTOROLA
Mbytes DRAM
MCF5307 Features
Programmable timer provides CAS-before-RAS refresh asynchronous DRAMs Support separate memory blocks UARTs Full-duplex operation Programmable clock Modem control signals available (CTS, RTS) Processor-interrupt capability Dual 16-bit general-purpose multiple-mode timers 8-bit prescaler Timer input output pins Processor-interrupt capability 22-nS resolution module Interchip interface EEPROMs, controllers, converters, keypads Fully compatible with industry-standard Master slave modes support multiple masters Automatic interrupt generation with programmable level System interface module (SIM) Chip selects provide direct interface 16-, 32-bit SRAM, ROM, FLASH, memory-mapped devices Eight fully programmable chip selects, each with base address register Programmable wait states port sizes chip select User-programmable processor clock/input clock frequency ratio Programmable interrupt controller interrupt latency Four external interrupt request inputs Programmable autovector generator Software watchdog timer 16-bit general-purpose interface IEEE 1149.1 test (JTAG) module System debug support Real-time trace determining dynamic execution path while emulator mode Background debug mode (BDM) debug features while halted Real-time debug support, including user-visible hardware breakpoint registers supporting variety breakpoint configurations Supports comprehensive emulator functions through trace breakpoint logic
MOTOROLA
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ColdFire Module Description
On-chip Supports processor clock/bus clock ratios 66/33, 66/22, 66/16.5, 90/45, 90/30, 90/22.5 Supports low-power mode
Product offerings Dhrystone MIPS Implemented 0.35 triple-layer-metal process technology with 3.3-V operation (5.0-V compliant pads) 208-pin plastic package 0°-70° operating temperature
1.2.1
Process
MCF5307 manufactured 0.35-µ CMOS process with triple-layer-metal routing technology. This process combines high performance power needed embedded system applications. Inputs 3.3-V tolerant; outputs CMOS open-drain CMOS with outputs operating from with guaranteed TTL-level specifications.
1.3.1
ColdFire Module Description
ColdFire Core
following sections provide overviews various modules incorporated MCF5307.
Version ColdFire core consists independent decoupled pipelines maximize performance-the instruction fetch pipeline (IFP) operand execution pipeline (OEP).
1.3.1.1
Instruction Fetch Pipeline (IFP)
four-stage instruction fetch pipeline (IFP) designed prefetch instructions operand execution pipeline (OEP). Because fetch execution pipelines decoupled eight-instruction FIFO buffer, fetch mechanism prefetch instructions advance their OEP, thereby minimizing time stalled waiting instructions. maximize performance branch instructions, Version implements branch prediction mechanism. Backward branches predicted taken. prediction forward branches controlled Condition Code Register (CCR). These predictions allow redirect fetch stream down path predicted taken well advance actual instruction execution. result significantly improved performance.
1.3.1.2
Operand Execution Pipeline (OEP)
prefetched instruction stream gated from FIFO buffer into two-stage OEP. consists traditional two-stage RISC compute engine with register file access feeding arithmetic/logic unit (ALU). decodes instruction, fetches required operands then executes required function.
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Freescale Semiconductor, Inc. 1.3.1.3 Module
ColdFire Module Description
unit provides signal processing capabilities MCF5307 variety applications including digital audio servo control. Integrated execution unit processor's OEP, unit implements three-stage arithmetic pipeline optimized multiplies. Both 32-bit input operands supported this design addition full extensions signed unsigned integers, plus signed, fixed-point fractional input operands.
1.3.1.4
Integer Divide Module
Integrated into OEP, divide module performs operations using signed unsigned integers. module supports word longword divides producing quotients and/or remainders.
1.3.1.5
8-Kbyte Unified Cache
MCF5307 architecture includes 8-Kbyte unified cache. This four-way, set-associative cache provides pipelined, single-cycle access cached instructions operands. with ColdFire caches, cache controller implements non-lockup, streaming design. processor-local memories decouples performance from external memory speeds increases available bandwidth external devices on-chip 4-channel DMA. cache implements line-fill buffers optimize 16-byte line burst accesses. Additionally, cache supports copyback, write-through, cache-inhibited modes. 4-entry, 32-bit buffer used cache line push operations configured deferred write buffering write-through cache-inhibited modes.
1.3.1.6
Internal 4-Kbyte SRAM
4-Kbyte on-chip SRAM module provides pipelined, single-cycle access memory regions mapped these devices. memory mapped 0-modulo-32K location 4-Gbyte address space. SRAM module useful storing time-critical functions, system stack, heavily-referenced data operands.
1.3.2
DRAM Controller
MCF5307 DRAM controller provides direct interface blocks DRAM. controller supports 16-, 32-bit memory widths easily interface PC-100 DIMMs. unique addressing scheme allows increases system memory size without rerouting address lines rewiring boards. controller operates normal mode page mode supports SDRAMs DRAMs.
1.3.3
Controller
MCF5307 provides four fully programmable channels quick data transfer. Dual- single-address modes support bursting cycle steal. Data transfers bits long with packing unpacking supported along with auto-alignment option efficient block transfers. Automatic block transfers from on-chip serial UARTs also supported through channels.
MOTOROLA
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ColdFire Module Description
1.3.4
UART Modules
MCF5307 contains UARTs, which function independently. Either UART clocked system clock, eliminating need external crystal. Each UART module interfaces directly CPU, shown Figure
UART Internal Channel Control Logic Serial Communications Channel System Integration Module (SIM) Interrupt Controller Interrupt Control Logic Programmable Clock Generation BCLKO External clock (TIN)
Figure UART Module Block Diagram
Each UART module consists following major functional areas: Serial communication channel 16-bit divider clock generation Internal channel control logic Interrupt control logic
Each UART contains programmable clock-rate generator. Data formats bits with even, odd, parity, stop bits 1/16 increments. UARTs include 4-byte 2-byte FIFO buffers. UART modules also provide several error-detection maskable-interrupt capabilities. Modem support includes request-to-send (RTS) clear-to-send (CTS) lines. BCLKO provides time base through programmable prescaler. UART time scale also sourced from timer input. Full-duplex, auto-echo loopback, local loopback, remote loopback modes allow testing UART connections. programmable UARTs interrupt various normal error-condition events.
1.3.5
Timer Module
timer module includes general-purpose timers, each which contains free-running 16-bit timer three modes. mode captures timer value with external event. Another mode triggers external signal interrupts when timer reaches value, while third mode counts external events. timer unit 8-bit prescaler that allows programming clock input frequency, which derived from system cycle external clock input (TIN). programmable timer-output generates either active-low pulse toggles output.
1.3.6
Module
interface two-wire, bidirectional serial used quick data exchanges between devices. minimizes interconnection between devices system best suited applications that
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MOTOROLA
ColdFire Module Description
need occasional bursts rapid communication over short distances among several devices. operate master, slave, multiple-master modes.
1.3.7
System Interface
MCF5307 processor provides direct interface 16-, 32-bit FLASH, SRAM, ROM, peripheral devices through fully programmable chip selects write enables. Support burst ROMs also included. Through on-chip PLL, users input slower clock (16.6 MHz) that internally multiplied create faster processor clock (33.3 MHz).
1.3.7.1
External Interface
interface controller transfers information between ColdFire core memory, peripherals, other devices external bus. external interface provides bits address space, 32-bit data bus, associated control signals. This interface implements extended synchronous protocol that supports bursting operations. Simple two-wire request/acknowledge arbitration between MCF5307 processor another master, such external device, glueless with arbitration logic internal MCF5307 processor. Multiple-master arbitration also available with some simple external arbitration logic.
1.3.7.2
Chip Selects
Eight fully programmable chip select outputs support external memory peripheral circuits with user-defined wait-state insertion. These signals interface 16-, 32-bit ports. base address, access permissions, internal transfer terminations programmable with configuration registers each chip select. also provides global chip select functionality boot upon reset initializing MCF5307.
1.3.7.3
16-Bit Parallel Port Interface
16-bit general-purpose programmable parallel port serves either input output pin-by-pin basis.
1.3.7.4
Interrupt Controller
interrupt controller provides user-programmable control internal peripheral interrupts implements four external fixed interrupt-request pins. Each internal interrupt programmed seven interrupt levels four priority levels within each these levels. Additionally, external interrupt request pins mapped levels levels Autovector capability available both internal external interrupts.
1.3.7.5
JTAG
help with system diagnostics manufacturing testing, MCF5307 processor includes dedicated user-accessible test logic that complies with IEEE 1149.1a standard boundary-scan testability, often referred Joint Test Action Group, JTAG. more information, refer IEEE 1149.1a standard.
MOTOROLA
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ColdFire Module Description
1.3.8
System Debug Interface
ColdFire processor core debug interface provided support system debugging conjunction with low-cost debug emulator development tools. Through standard debug interface, users access real-time trace debug information. This allows processor system debugged full speed without need costly in-circuit emulators. debug unit MCF5307 compatible upgrade MCF52xx debug module with added flexibility breakpoint registers command view program counter (PC). on-chip breakpoint resources include total programmable registers-a address registers (with 32-bit registers), data registers (with 32-bit data register plus 32-bit data mask register), 32-bit register plus 32-bit mask register. These registers accessed through dedicated debug serial communication channel from processor's supervisor mode programming model. breakpoint registers configured generate triggers combining address, data, conditions variety single dual-level definitions. trigger event programmed generate processor halt initiate debug interrupt exception. MCF5307's interrupt servicing options during emulator mode allow real-time critical interrupt service routines serviced while processing debug interrupt event, thereby ensuring that system continues operate even during debugging. support program trace, Version debug module provides processor status (PST[3:0]) debug data (DDATA[3:0]) ports. These buses PSTCLK output provide execution status, captured operand data, branch target addresses defining processor activity CPU's clock rate.
1.3.9
Module
RSTO PCLK PSTCLK CLKIN CLKIN Divide Divide BCLKO
MCF5307 module shown Figure
FREQ[1:0] RSTI DIVIDE[1:0]
Figure Module
module's three modes operation described follows. Reset mode-When RSTI asserted, enters reset mode. reset, asserts RSTO from MCF5307. core:bus frequency ratio other MCF5307 configuration information sampled during reset. Normal mode-In normal mode, input frequency programmed reset clock-multiplied provide processor clock (PCLK).
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Programming Model, Addressing Modes, Instruction
Reduced-power mode-In reduced-power mode, PCLK disabled executing sequence that includes programming control system configuration register (SCR) then executing STOP instruction. Register contents retained reduced-power mode, system reenabled quickly when unmasked interrupt reset detected.
Programming Model, Addressing Modes, Instruction
ColdFire programming model privilege levels-supervisor user. status register (SR) indicates privilege level. processor identifies logical address that differentiates between supervisor user modes accessing either supervisor user address space.
User mode-When processor user mode (SR[S] only subset registers accessed, privileged instructions cannot executed. Typically, most application processing occurs user mode. User mode usually entered executing return from exception instruction (RTE, assuming value SR[S] saved stack MOVE, instruction (assuming SR[S] Supervisor mode-This mode protects system resources from uncontrolled access users. supervisor mode, complete access provided registers entire ColdFire instruction set. Typically, system programmers supervisor programming model implement operating system functions provide control. supervisor programming model provides access same registers user model, plus additional registers configuring on-chip system resources, described Section 1.4.3, "Supervisor Registers." Exceptions (including interrupts) handled supervisor mode.
1.4.1
Programming Model
Figure shows MCF5307 programming model.
MOTOROLA
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Programming Model, Addressing Modes, Instruction
Data registers
Address registers
User Registers
Stack pointer Program counter Condition code register status register accumulator mask register Status register Vector base register Cache control register Access control register Access control register base address register Module base address register
MACSR MASK
Supervisor Registers
(CCR) Must zeros
CACR ACR0 ACR1 RAMBAR MBAR
Figure ColdFire MCF5307 Programming Model
1.4.2
User Registers
Table User-Level Registers
user programming model shown Figure summarized Table
Register Data registers (D0-D7) Address registers (A0-A7) Program counter (PC) Description These 32-bit registers bit, byte, word, longword operands. They also used index registers. These 32-bit registers serve software stack pointers, index registers, base address registers. base address registers used word longword operations. functions hardware stack pointer during stacking subroutine calls exception handling. Contains address instruction currently being executed MCF5307 processor
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Programming Model, Addressing Modes, Instruction
Table User-Level Registers (continued)
Register Condition code register (CCR)
Description lower byte contains indicator flags that reflect result previous operation used conditional instruction execution.
status register Defines operating configuration unit contains indicator flags from results (MACSR) instructions. Accumulator (ACC) General-purpose register used accumulate results operations Mask register (MASK) General-purpose register provides optional address mask instructions that fetch operands from memory. useful implementation circular queues operand memory.
1.4.3
Supervisor Registers
Table Supervisor-Level Registers
Table summarizes MCF5307 supervisor-level registers.
Register Status register (SR) Description upper byte provides interrupt information addition variety mode indicators signaling operating state ColdFire processor. lower byte CCR, shown Figure Defines upper bits base address exception vector table used during exception processing. low-order bits forced zero, locating vector table 0-modulo-1 Mbyte address. Defines operating modes Version cache memories. Control fields configuring instruction, data, branch cache provided this register, along with default attributes 4-Gbyte address space. Define address ranges attributes associated with various memory regions within 4-Gbyte address space. Each defines location given memory region assigns attributes such write-protection cache mode (copyback, write-through, cacheability). Additionally, CACR fields assign default attributes instruction data memory spaces. Provide logical base address 4-Kbyte SRAM module define attributes access types allowed SRAM. Defines logical base address memory-mapped space containing control registers on-chip peripherals.
Vector base register (VBR) Cache configuration register (CACR) Access control registers (ACR0/1)
base address register (RAMBAR) Module base address register (MBAR)
1.4.4
Instruction
ColdFire instruction supports high-level languages optimized those instructions most commonly generated compilers embedded applications. Section 2.6, "Instruction Summary," MCF5307 User's Manual provides alphabetized listing ColdFire instruction opcodes, supported operation sizes, assembler syntax. two-operand instructions, first operand generally source operand second destination. Because ColdFire architecture provides upgrade path customers, instruction supports most common opcodes. majority instructions binary compatible optimized opcodes. This feature, when coupled with code conversion tools from third-party developers, generally minimizes software porting issues customers with applications.
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Programming Model, Addressing Modes, Instruction
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Programming Model, Addressing Modes, Instruction
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MOTOROLA
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MCF5307PB/D
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This document provides overview MCF5307 ColdFire processor. includes g

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