This document provides overview MCF5272 microprocessor features, inclu
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MCF5272PB/D Rev. 1/2002 MCF5272 Integrated Microprocessor Product Brief
This document provides overview MCF5272 microprocessor features, including major functional components.
Features
Static Version ColdFire variable-length RISC processor 32-bit address data path on-chip 66-MHz processor core frequency Sixteen general-purpose 32-bit data address registers Multiply-accumulate unit (MAC) fast multiply operations Dhrystone MIPS
block diagram MCF5272 shown Figure main features follows:
On-chip memories 4-Kbyte SRAM internal 16-Kbyte internal 1-Kbyte instruction cache
Power management Fully-static operation with processor sleep whole-chip stop modes Very rapid response interrupts from low-power sleep mode (wake-up feature) Clock enable/disable each peripheral when used Software-controlled disable external clock input virtually zero power consumption (low-power stop mode) universal asynchronous/synchronous receiver transmitters (UARTs) Full-duplex operation Based MC68681 dual-UART (DUART) programming model Flexible baud rate generator Modem control signals available (CTS RTS) Processor interrupt wake-up capability Enhanced FIFOs, bytes each
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Features
ColdFire Processor Complex Instruction Unit JTAG Instruction Address Generation Instruction Fetch FIFO Instruction Buffer
D[31:0]
Decode, Select, Operand Fetch Address Generation, Execute
Local Memory RAMBAR SRAM Controller 4-Kbyte SRAM Controller 16-Kbyte Local Memory Data
Local Memory Instruction
ROMBAR
Instruction Cache Controller ACR0 ACR1 CACR 1-Kbyte Cache
4-Entry Store Buffer
SYSTEM INTEGRATION MODULE (SIM) System Control
ALPR WRRR WIRR
PLIC Parallel Port
QSPI
PADR- PCDR
Base Address
MBAR
Identification
PACNT- PADDR- PDCNT PCDDR
SDRAM Controller SDRAM Control
SDCR
Chip Select Module
CSORs CSBRs
External Interface
Interrupt Controller
ICRs PITR PIWR PIVR
Ethernet UARTs Four GeneralPurpose Timers
SDRAM Timer
SDTR
DRAM Controller Outputs CS[7:0]
32-Bit Data 32-Bit Address Control Signals
INT[6:1]
Figure MCF5272 Block Diagram
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MOTOROLA
Ethernet Module baseT capability, half- full-duplex baseT capability, half duplex limited throughput full-duplex (MCF5272) On-chip transmit receive FIFOs Off-chip flexible buffer descriptor rings Media-independent interface (MII) Universal serial (USB) module Mbps (full-speed) Fully compatible with specifications Eight endpoints (control, bulk, interrupt isochronous) Endpoint FIFOs Selectable on-chip analog interface External memory interface External glueless 32-bit SRAM interface SDRAM controller supports 16-256 Mbit devices External configurable bits width SDRAM Glueless interface SRAM devices with without byte strobe inputs Programmable wait state generator Queued serial peripheral interface (QSPI) Full-duplex, three-wire synchronous transfer four chip selects available Master operation Programmable master rates preprogrammed transfers Timer module 4x16-bit general-purpose multi-mode timer Input capture output compare pins timers Programmable prescaler 15-nS resolution 66-MHz clock frequency Software watchdog timer Software watchdog generate interrupt before reset Processor interrupt each timer Pulse width modulation (PWM) unit Three identical channels Independent prescaler point Period/duty range variable System integration module (SIM) System configuration including internal external address mapping System protection hardware watchdog
Features
MOTOROLA
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MCF5272 Architecture
Versatile programmable chip select signals with wait state generation logic three 16-bit parallel input/output ports Latchable interrupt inputs with programmable priority edge triggering Programmable interrupt vectors on-chip peripherals Physical layer interface controller (PLIC) Allows connection using general circuit interface (GCI) interchip digital link (IDL) physical layer protocols data Three physical interfaces Four time-division multiplex (TDM) ports IEEE 1149.1 boundary-scan test access port (JTAG) board-level testing Operating voltage: ±0.3 Operating temperature: 0°-70°C Operating frequency: MHz, from external CMOS oscillator Compact ultra low-profile ball-molded plastic ball-grid array package (PGBA)
1.2.1
MCF5272 Architecture
Version ColdFire Core
This section briefly describes MCF5272 core, SIM, UART, timer modules, test access port.
Based concept variable-length RISC technology, ColdFire combines simplicity conventional 32-bit RISC architectures with memory-saving, variable-length instruction set. main features MCF5272 core follows: 32-bit address directly addresses Gbytes address space 32-bit data Variable-length RISC Optimized instruction high-level language constructs Sixteen general-purpose 32-bit data address registers unit applications Supervisor/user modes system protection Vector base register relocate exception-vector table Special core interfacing signals integrated memories Full debug support
Version ColdFire core 32-bit address 32-bit data bus. address allows direct addressing Gbytes. supports misaligned data accesses arbitration unit multiple masters. Version ColdFire supports enhanced subset 68000 instruction set. provides instructions applications; otherwise, Version ColdFire user code runs unchanged 68020, 68030, 68040, 68060 processors. removed instructions include BCD, field, logical rotate,
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MOTOROLA
MCF5272 Architecture
decrement branch, integer division, integer multiply with 64-bit result. Also, four indirect addressing modes have been eliminated. ColdFire core incorporates complete debug module that provides real-time trace, background debug mode, real-time debug support.
1.2.2
System Integration Module (SIM)
MCF5272 provides external interface ColdFire architecture. also eliminates most glue logic that typically supports microprocessor interface with peripheral memory system. provides programmable circuits perform address-decoding chip selects, wait-state insertion, interrupt handling, clock generation, discrete I/O, power management features.
1.2.2.1
External Interface
external interface (EBI) handles transfer information between internal core memory, peripherals, other processing elements external address space.
1.2.2.2
Chip Select Wait State Generation
Programmable chip select outputs provide signals enable external memory peripheral circuits, providing handshaking timing signals automatic wait-state insertion data sizing. Base memory address block size programmable, with some restrictions. example, starting address must boundary that multiple block size. Each chip select general purpose; however, chip selects programmed provide read write enable signals suitable with most popular static RAMs peripherals. Data width (8-bit, 16-bit, 32-bit) programmable chip selects, further decoding available protection from user mode access read-only access.
1.2.2.3
System Configuration Protection
provides configuration registers that allow general system functions controlled monitored. example, on-chip registers relocated block programming module base address, power management modes selected, source most recent RESET BERR checked. hardware watchdog features enabled disabled, time-out period programmed. software watchdog timer also provided system protection. programmed, timer causes reset MCF5272 refreshed periodically software.
1.2.2.4
Power Management
sleep stop power management modes reduce power consumption allowing software shut down core, peripherals, whole device during inactive periods. reduce power consumption further, software individually disable internal clocks on-chip peripheral modules. power-saving modes described follows: Sleep mode uses interrupt control logic allow interrupt condition wake processor. MCF5272 fully static, sleep mode simply disabling core's clock after current instruction completes. interrupt from internal external source causes on-chip power
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MOTOROLA
MCF5272 Architecture
management logic reenable core's clock; execution resumes with next instruction. This allows rapid return from power-down state compared dynamic implementation that must perform power-on reset processing before software handle interrupt request. interrupts enabled appropriate priority level, program control passes relevant interrupt service routine. Stop mode entered disabling external clock input achieved software setting control register. Program execution stops after current instruction. stop mode, neither core peripherals active. MCF5272 consumes very little power this mode. resume normal operation, external interrupts cause power management logic re-enable external clock input. MCF5272 resumes program execution from where entered stop mode interrupt pending), starts interrupt exception processing interrupts pending.
1.2.2.5
Parallel Input/Output Ports
MCF5272 three 16-bit general-purpose parallel ports, each line which programmed either input output. Some port lines have dedicated pins others shared with other MCF5272 functions. Some outputs have high drive current capability.
1.2.2.6
Interrupt Inputs
MCF5272 flexible latched interrupt inputs each which generate separate, maskable interrupt with programmable interrupt priority level triggering edge (falling rising). Each interrupt interrupt vector.
1.2.3
UART Module
MCF5272 full-duplex UART modules with on-chip baud rate generator providing both standard non-standard baud rates Mbps. module functionally equivalent MC68681 DUART with enhanced features including 24-byte FIFOs. Data formats bits with even, odd, parity stop bits 1/16-bit increments. Receive transmit FIFOs minimize service calls. wide variety error detection maskable interrupt capability provided. Using programmable prescaler external source, MCF5272 system clock supports various baud rates. Modem support provided with request-to-send (RTS) clear-to-send (CTS) lines available externally. Full-duplex autoecho loopback, local loopback, remote loopback modes selected. UART programmed interrupt wake-up various normal abnormal events. reduce power consumption, UART disabled software use.
1.2.4
Timer Module
timer module contains five timers arranged submodules. submodule contains programmable software watchdog timer. other contains four independent, identical general-purpose timer units, each containing free-running 16-bit timer various modes, including capturing timer value with external event, counting external events, triggering external signal interrupting when timer reaches value. Each unit 8-bit prescaler deriving clock input frequency from system clock external clock input. output associated with each timer programmable modes. reduce power consumption, timer module disabled software.
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System Design
1.2.5
Test Access Port
system diagnostics manufacturing testing, MCF5272 includes user-accessible test logic that complies with IEEE 1149.1 standard boundary scan testing, often referred JTAG (Joint Test Action Group). IEEE 1149.1 Standard provides more information.
System Design
This section presents issues consider when designing with MCF5272. describes differences between MCF5272 (core peripherals) various other standard components that replaced moving integrated device like MCF5272.
1.3.1
System Configuration
MCF5272 flexibility system interfacing dynamic sizing feature which 32-,16-, 8-bit data sizes programmable per-chip select basis. programmable nature strobe signals (including OE/RD, R/W, BS[3:0], CSn) should ensure that external decode logic minimal nonexistent. Configuration software required upon power-on reset before chip-selected devices used, except chip select (CS0), which active after power-on reset until programmed otherwise. BUSW1 BUSW0 select initial data width only. wake-up from sleep mode restart from stop mode does require reconfiguration chip select registers other system configuration registers.
1.4.1
MCF5272-Specific Features
Physical Layer Interface Controller (PLIC)
This section describes features peculiar MCF5272.
physical layer interface controller (PLIC) allows MCF5272 connect physical level with external CODECs other peripheral devices that either general circuit interface (GCI), interchip digital link (IDL), physical layer protocols. This module primarily intended facilitate designs that include ISDN interfaces.
1.4.2
Pulse-Width Modulation (PWM) Unit
unit intended control applications. With suitable low-pass filter, used digital-to-analog converter. This module generates synchronous series pulses. duty cycle pulses under software control. main features include following: Double-buffered width register Variable-divide prescale Three identical, independent modules Byte-wide width register provides programmable control duty cycle.
implements simple free-running counter with width register comparator such that output cleared when counter exceeds value width register. When counter wraps around,
MOTOROLA
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MCF5272-Specific Features
value greater than width register value, output high. With suitable low-pass filter, used digital-to-analog converter.
1.4.3
Queued Serial Peripheral Interface (QSPI)
QSPI module provides serial peripheral interface with queued transfer capability. supports stacked transfers time, making intervention between transfers unnecessary. Transfer RAMs QSPI indirectly accessible using address data registers. Functionality similar QSPI portion (queued serial module) implemented MC68332. QSPI following features: Programmable queue support transfers without user intervention Supports transfer sizes bits 1-bit increments Four peripheral chip-select lines control devices Baud rates from 129.4 Kbps Mbps MHz. Programmable delays before after transfers Programmable clock phase polarity Supports wrap-around mode continuous transfers
1.4.4
Universal Serial (USB) Module
controller MCF5272 supports device mode data communications with host (typically PC). host attached peripherals share bandwidth through host-scheduled, token-based protocol. uses tiered star topology with center each star. Each wire segment point-to-point connection between host connector peripheral connector.
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MOTOROLA
MCF5272-Specific Features
MOTOROLA
MCF5272 Integrated Microprocessor Product Brief More Information This Product, www.freescale.com
MCF5272-Specific Features
MCF5272 Integrated Microprocessor Product Brief More Information This Product, www.freescale.com
MOTOROLA
MCF5272-Specific Features
MOTOROLA
MCF5272 Integrated Microprocessor Product Brief More Information This Product, www.freescale.com
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