DESCRIPTIO 1.25Msps Sample Rate Single Supply Power Dissipation:

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DESCRIPTIO 1.25Msps Sample Rate Single Supply Power Dissipation:

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LTC1415 12-Bit, 1.25Msps, 55mW Sampling Converter FEATURES
DESCRIPTIO
1.25Msps Sample Rate Single Supply Power Dissipation: 55mW Sleep Power Shutdown Modes ±0.35LSB ±0.25LSB 72dB S/(N 80dB 100kHz External Internal Reference Operation True Differential Inputs Reject Common Mode Noise Input Range: 4.096V (1mV/LSB) 28-Pin SSOP Packages
LTC1415 700ns, 1.25Msps, 12-bit sampling converter that draws only 55mW from single supply. This easy-to-use device includes high dynamic range sample-and-hold, precision reference trimmed internal clock. power shutdown modes provide flexibility power systems. LTC1415's full-scale input range 4.096V. linearity errors ±0.35LSB INL, 0.25LSB make ideal imaging systems. Outstanding performance includes 72dB S/(N 80dB with input frequency 100kHz. unique differential input sample-and-hold acquire single-ended differential input signals 18MHz bandwidth. 60dB common mode rejection allows users eliminate ground loops common mode noise measuring signals differentially from source. compatible, 12-bit parallel output port. There pipeline delay conversion results. separate convert start input data ready signal (BUSY) ease connections FIFOs, DSPs microprocessors. separate output logic supply allows direct connection components.
APPLICATI
High Speed Data Acquisition Imaging Systems Digital Signal Processing Multiplexed Data Acquisition Systems Telecommunications
registered trademarks Linear Technology Corporation.
TYPICAL APPLICATI
LTC1415 DIFFERENTIAL +AIN ANALOG INPUT 4.096V) -AIN 2.50V VREF OUTPUT REFCOMP AGND 10µF D11(MSB) 12-BIT PARALLEL DGND
1.25MHz, 12-Bit Sampling Converter
AVDD DVDD OVDD BUSY CONVST SHDN NAP/SLP OGND CONTROL LINES OUTPUT LOGIC SUPPLY 10µF
Effective Bits Signal-to-(Noise Distortion) Input Frequency
NYQUIST FREQUENCY
EFFECTIVE BITS
100k INPUT FREQUENCY (Hz) fSAMPLE 1.25Msps
1415 TA01
SIGNAL/(NOISE DISTORTION) (dB)
LTC1415 TA02
LTC1415 ABSOLUTE RATI
PACKAGE/ORDER ATIO
VIEW +AIN -AIN VREF REFCOMP AGND (MSB) DGND PACKAGE 28-LEAD PLASTIC SSOP AVDD DVDD OVDD BUSY CONVST SHDN NAP/SLP OGND PACKAGE 28-LEAD PLASTIC WIDE
AVDD DVDD =OVDD (Notes
Supply Voltage (VDD) Analog Input Voltage (Note 0.3V 0.3V Digital Input Voltage (Note 0.3V Digital Output Voltage 0.3V 0.3V Power Dissipation 500mW Operating Temperature Range LTC1415C 70°C LTC1415I 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1415CG LTC1415CSW LTC1415IG LTC1415ISW
TJMAX 110°C, 95°C/W TJMAX 110°C, 130°C/W (SW)
Consult factory Military grade parts.
VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco
With Internal Reference (Notes
CONDITIONS (Note (Note
0.35 0.25
UNITS Bits ppm/°C
IOUT(REF)
ALOG
SYMBOL PARAMETER tjitter CMRR
(Note
CONDITIONS 4.75V 5.25V High Between Conversions During Conversions
4.096
UNITS
Analog Input Range (Note Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio
-1.5
psRMS
VDD,
LTC1415
ACCURACY
SYMBOL S/(N SFDR PARAMETER
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance REFCOMP Output Voltage CONDITIONS IOUT IOUT 4.75V 5.25V
IOUT 0.1mA
DIGITAL PUTS DIGITAL OUTPUTS
SYMBOL PARAMETER High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage 4.75V 10µA 200µA 4.75V 160µA 1.6mA VOUT VDD, High High (Note VOUT VOUT CONDITIONS 5.25V 4.75V
Level Output Voltage
ISOURCE ISINK
Hi-Z Output Leakage Hi-Z Output Capacitance Output Source Current Output Sink Current
POWER REQUIRE
SYMBOL PARAMETER Supply Voltage Supply Current Mode Sleep Mode Power Dissipation Mode Sleep Mode
(Note
CONDITIONS 100kHz Input Signal 600kHz Input Signal 100kHz Input Signal, First Harmonics 600kHz Input Signal, First Harmonics 600kHz Input Signal fIN1 29.37kHz, fIN2 32.446kHz S/(N 68dB UNITS
Signal-to-(Noise Distortion) Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth
(Note
2.480 2.500 0.01 4.096 2.520 UNITS ppm/°C LSB/V
IOUT
(Note
UNITS
0.05 0.10
(Note
CONDITIONS (Notes High SHDN NAP/SLP (Note SHDN NAP/SLP (Note High SHDN NAP/SLP SHDN NAP/SLP
4.75
0.01
5.25
UNITS
LTC1415
CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ PARAMETER Maximum Sampling Frequency Conversion Acquisition Time Conversion Time Acquisition Time Setup Time CONVST Setup Time NAP/SLP SHDN Setup Time (Notes (Notes (Notes
denotes specifications which apply over full operating temperature range; other limits typicals 25°C. Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect ground with DGND AGND wired together unless otherwise noted. Note When these voltages taken below ground above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below ground above without latchup. Note When these voltages taken below ground, they will clamped internal diodes. This product handle input currents greater than 100mA below ground without latchup. These pins clamped VDD. Note fSAMPLE 1.25MHz, unless otherwise specified.
(Note
CONDITIONS
UNITS
1.25
SHDN CONVST Wake-Up Time Mode (Note Sleep Mode, CREFCOMP 10µF (Note CONVST Time CONVST BUSY Delay Data Ready Before BUSY
(Notes 25pF
Delay Between Conversions Wait Time After BUSY Data Access Time After
(Note (Note 25pF
100pF
Relinquish Time 70°C 40°C 85°C Time CONVST High Time Aperture Delay Sample-and-Hold
Note Linearity, offset full-scale specifications apply singleended +AIN input with grounded. Note Integral nonlinearity defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Bipolar offset offset voltage measured from 0.5LSB when output code flickers between 0000 0000 0000 1111 1111 1111. Note Guaranteed design, subject test. Note Recommended operating conditions. Note falling edge CONVST starts conversion. CONVST returns high critical point during conversion create small errors. best performance ensure that CONVST returns high either within 425ns after start conversion after BUSY rises. Note CONVST
LTC1415 TYPICAL PERFORMANCE CHARACTERISTICS
S/(N Input Frequency Amplitude
AMPLITUDE BELOW FUNDAMENTAL)
SIGNAL/(NOISE DISTORTION) (dB)
SIGNAL-TO -NOISE RATIO (dB)
-20dB
-60dB
100k INPUT FREQUENCY (Hz)
Spurious-Free Dynamic Range Input Frequency
SPURIOUS-FREE DYNAMIC RANGE (dB)
-120 100k INPUT FREQUENCY (Hz) 100k 200k 300k FREQUENCY (Hz) 400k
AMPLITUDE (dB)
Integral Nonlinearity Output Code
1.00 1.00
0.50
ERROR (LSBs)
ERROR (LSBs)
0.00
-0.50
-1.00 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
LTC1415 TPC07
LTC1415 TPC01 LTC1415 TPC04
Signal-to-Noise Ratio Input Frequency
-100
Distortion Input Frequency
100k INPUT FREQUENCY (Hz)
LTC1415 TPC03
100k INPUT FREQUENCY (Hz)
LTC1415 TPC02
Intermodulation Distortion Plot
fSAMPLE 1.25MHz fIN1 86.97509766kHz fIN2 113.2202148kHz
-100
500k
600k
LTC1415 TPC05
Differential Nonlinearity Output Code
0.50
0.00
-0.50
-1.00 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
LTC1415 TPC06
LTC1415 TYPICAL PERFORMANCE CHARACTERISTICS
AMPLITUDE POWER SUPPLY FEEDTHROUGH (dB)
Power Supply Feedthrough Ripple Frequency
-100 DGND OVDD 100k RIPPLE FREQUENCY (Hz) COMMON MODE REJECTION (dB)
CTIO
(Pin Positive Analog Input, 4.096V. (Pin Negative Analog Input, 4.096V. VREF (Pin 2.50V Reference Output. REFCOMP (Pin Bypass AGND with 10µF tantalum parallel with 0.1µF 10µF ceramic. AGND (Pin Analog Ground. (Pins 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground. (Pins 18): Three-State Data Outputs. OGND (Pin 19): Digital Output Buffer Ground. NAP/SLP (Pin 20): Power Shutdown Mode. High quick wake-up mode. SHDN (Pin 21): Power Shutdown Input. logic level will invoke Shutdown mode selected NAP/SLP pin. high unused. (Pin 22): Read Input. This enables output drivers when low. CONVST (Pin 23): Conversion Start Signal. This active signal starts conversion falling edge. (Pin 24): Chip Select input must recognize CONVST inputs. BUSY (Pin 25): BUSY output shows converter status. when conversion progress. rising edge used latch output data. 0VDD (Pin 26): Digital output buffer supply. Short output. driving logic. DVDD (Pin 27): Positive Supply. Short AVDD (Pin 28): Positive Supply. Bypass AGND with 10µF tantalum parallel with 0.1µF 10µF ceramic.
Input Common Mode Rejection Input Frequency
100k INPUT FREQUENCY (Hz)
LTC1415 TPC09
LTC1415 TPC08
LTC1415
CTIO BLOCK DIAGRA
CSAMPLE +AIN CSAMPLE VREF 2.5V ZEROING SWITCHES AVDD DVDD
REFCOMP (4.096V) AGND DGND INTERNAL CLOCK CONTROL LOGIC SUCCESSIVE APPROXIMATION REGISTER OUTPUT LATCHES
TEST CIRCUITS
Load Circuits Access Timing
100pF 100pF
Hi-Z
12-BIT CAPACITIVE COMP
OVDD OGND
NAP/SLP SHDN CONVST
BUSY
1415
Load Circuits Relinquish Time
Hi-Z
1415 TC01
Hi-Z
Hi-Z
1415 TC02
LTC1415
APPLICATIONS INFORMATION
CONVERSION DETAILS LTC1415 uses successive approximation algorithm internal sample-and-hold circuit convert analog signal 12-bit parallel output. complete with precision reference internal clock. control logic provides easy interface microprocessors DSPs (please refer Digital Interface section data format). Conversion start controlled CONVST inputs. start conversion successive approximation register (SAR) reset. Once conversion cycle begun cannot restarted. During conversion, internal differential 12-bit capacitive output sequenced from most significant (MSB) least significant (LSB). Referring Figure +AIN -AIN inputs connected sample-and-hold capacitors (CSAMPLE) during acquire phase comparator offset nulled zeroing switches. this acquire phase, minimum delay 150ns will provide enough time sampleand-hold capacitors acquire analog signal. During convert phase comparator zeroing switches open, putting comparator into compare mode. input switches connect CSAMPLE capacitors ground, transferring differential analog input charge onto summing junction. This input charge successively compared
+CSAMPLE +AIN SAMPLE HOLD SAMPLE -CSAMPLE HOLD +CDAC ZEROING SWITCHES HOLD
AMPLITUDE (dB)
-AIN
HOLD
+VDAC -CDAC COMP
-VDAC
OUTPUT LATCHES
LTC1415
Figure Simplified Block Diagram
with binary weighted charges supplied differential capacitive DAC. decisions made high speed comparator. conversion, differential output balances input charges. contents 12-bit data word) which represents difference loaded into 12-bit output latches. DYNAMIC PERFORMANCE LTC1415 excellent high speed sampling capability. (Fast Fourier Transform) test techniques used test ADC's frequency response, distortion noise rated throughput. applying distortion sine wave analyzing digital output using algorithm, ADC's spectral content examined frequencies outside fundamental. Figure shows typical LTC1415 plot.
-100 -120 FREQUENCY (kHz) fSAMPLE 1.25MHz 99.792kHz SFDR 87.5 SINAD 72.1
LTC1415
Figure LTC1415 Nonaveraged, 4096 Point
Signal-to-Noise Ratio signal-to-noise plus distortion ratio [S/(N SINAD ratio between amplitude fundamental input frequency amplitude other frequency components output. output band limited frequencies from above below half sampling frequency. Figure shows typical spectral content with 1.25MHz sampling rate 100kHz input. dynamic performance excellent input frequencies Nyquist limit 625kHz.
LTC1415
APPLICATIONS INFORMATION
Effective Number Bits effective number bits (ENOBs) measurement resolution directly related S/(N equation: [S/(N 1.76]/6.02 where effective number bits resolution S/(N expressed maximum sampling rate 1.25MHz LTC1415 maintains very good ENOBs Nyquist input frequency 625kHz (refer Figure Total Harmonic Distortion Total Harmonic Distortion (THD) ratio harmonics input signal fundamental itself. out-of-band harmonics alias into frequency
AMPLITUDE BELOW FUNDAMENTAL)
EFFECTIVE BITS
100k INPUT FREQUENCY (Hz)
LT1415
Figure Effective Bits Signal/(Noise Distortion) Input Frequency
AMPLITUDE (dB)
-100 -120 100k 200k 300k FREQUENCY (Hz) 400k 500k 600k
LTC1415
Figure Intermodulation Distortion Plot
band between half sampling frequency. expressed .Vn2 where amplitude fundamental frequency through amplitudes second through harmonics. input frequency shown Figure LTC1415 good distortion performance Nyquist frequency beyond. 20Log Intermodulation Distortion input signal consists more than spectral component, transfer function nonlinearity produce intermodulation distortion (IMD) addition THD. change sinusoidal input caused
-100 100k INPUT FREQUENCY (Hz)
LTC1415
SIGNAL/(NOISE DISTORTION) (dB)
Figure Distortion Input Frequency
fSAMPLE 1.25MHz fIN1 86.97509766kHz fIN2 113.2202148kHz
LTC1415
APPLICATIONS INFORMATION
presence another sinusoidal input different frequency. pure sine waves frequencies applied input, nonlinearities transfer function create distortion products difference frequencies nfb, where etc. example, order terms include fb). input sine waves equal magnitude, value decibels) order products expressed following formula:
IMD( 20Log Amplitude Amplitude
ACQUISITION TIME (µs)
Peak Harmonic Spurious Noise peak harmonic spurious noise largest spectral component excluding input signal This value expressed decibels relative value full-scale input signal. Full-Power Full-Linear Bandwidth full-power bandwidth that input frequency which amplitude reconstructed fundamental reduced full-scale input signal. full-linear bandwidth input frequency which S/(N dropped 68dB effective bits). LTC1415 been designed optimize input bandwidth, allowing undersample input signals with frequencies above converter's Nyquist Frequency. noise floor stays very high frequencies; S/(N becomes dominated distortion frequencies beyond Nyquist. Driving Analog Input differential analog inputs LTC1415 easy drive. inputs driven differentially singleended input (i.e., -AIN input grounded). +AIN -AIN inputs sampled same instant. unwanted signal that common mode both inputs will reduced common mode rejection sample-and-hold circuit. inputs draw only small current spike while charging sample-and-hold capacitors conversion. During conversion analog inputs draw
only small leakage current. source impedance driving circuit low, then LTC1415 inputs driven directly. source impedance increases will acquisition time (see Figure minimum acquisition time with high source impedance, buffer amplifier should used. only requirement that amplifier driving analog input(s) must settle after small current spike before next conversion starts (settling time must 150ns full throughput rate).
0.01 0.01
SOURCE RESISTANCE
1415
Figure Acquisition Time Source Resistance
Choosing Input Amplifier Choosing input amplifier easy requirements taken into consideration. First, limit magnitude voltage spike seen amplifier from charging sampling capacitor, choose amplifier that output impedance 100) closed-loop bandwidth frequency. example, amplifier used gain unity-gain bandwidth 50MHz, then output impedance 50MHz should less than 100. second requirement that closed-loop bandwidth must greater than 20MHz ensure adequate small-signal settling full throughput rate. slower amps used, more settling time provided increasing time between conversions. best choice drive LTC1415 will depend application. Generally applications fall into categories: applications where dynamic specifications most critical time domain applications where accuracy settling time most critical.
LTC1415
APPLICATIONS INFORMATION
following list summary amps that suitable driving LTC1415, more detailed information available Linear Technology databooks LinearViewCD-ROM. 1215/LT1216: Dual quad 23MHz, 50V/µs single supply amps. Single ±15V supplies, 6.6mA specifications, 90ns settling 0.5LSB. LT1223: 100MHz video current feedback amplifier. ±15V supplies, supply current. distortion above 400kHz. noise. Good applications. LT1227: 140MHz video current feedback amplifier. ±15V supplies, 10mA supply current. Lowest distortion frequencies above 400kHz. noise. Best applications. LT1229/LT1230: Dual quad 100MHz current feedback amplifiers. ±15V supplies, supply current each amplifier. noise. Good specs. LT1360: 37MHz voltage feedback amplifier. ±15V supplies. 3.8mA supply current. Good specs. 70ns settling 0.5LSB. LT1363: 50MHz, 450V/µs amps. ±15V supplies. 6.3mA supply current. Good specs. 60ns settling 0.5LSB. LT1364/LT1365: Dual quad 50MHz, 450V/µs amps. ±15V supplies, 6.3mA supply current amplifier. 60ns settling 0.5LSB. Input Filtering noise distortion input amplifier other circuitry must considered since they will LTC1415 noise distortion. small-signal bandwidth sample-and-hold circuit 20MHz. noise distortion products that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter sufficient many applications. example Figure shows 1000pF capacitor from +AIN ground source resistor limit input bandwidth 1.6MHz. 1000pF
LinearView trademark Linear Technology Corporation.
capacitor also acts charge reservoir input sample-and-hold isolates input from sampling glitch sensitive circuitry. High quality capacitors resistors should used since these components distortion. silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors also generate distortion from self heating from damage that occur during soldering. Metal film surface mount resistors much less susceptible both problems.
1000pF -AIN LTC1415 VREF
ANALOG INPUT
+AIN
10µF
REFCOMP
AGND
LTC1415
Figure Input Filter
Input Range 4.096V input range LTC1415 optimized noise. Most single supply amps also perform well over this same range, allowing direct coupling analog inputs eliminating need special translation circuitry. Some applications require other input ranges. LTC1415 differential inputs reference circuitry accommodate other input ranges often with little additional circuitry. following sections describe reference input circuitry they affect input range. Internal Reference LTC1415 on-chip, temperature compensated, curvature corrected, bandgap reference that factory trimmed 2.500V. connected internally reference amplifier available VREF (Pin Figure resistor series with output that easily overdriven external reference other
LTC1415
APPLICATIONS INFORMATION
circuitry. reference amplifier gains voltage VREF 1.638 create required internal reference voltage 4.096V. This provides buffering between VREF high speed capacitive DAC. reference amplifier compensation (REFCOMP, must bypassed with capacitor ground. reference amplifier stable with capacitors greater. best noise performance 10µF ceramic tantalum parallel with 0.1µF ceramic recommended.
DIFFERENTIAL ANALOG INPUT RANGE (VREF)(1.638) +AIN -AIN LTC1415 1.25V VREF
2.500V
BANDGAP REFERENCE
4.096V
REFCOMP
REFERENCE
10µF
AGND
LTC1415
LTC1415 F08a
Figure LTC1415 Reference Circuit
LT1019A-2.5 VOUT ANALOG INPUT +AIN -AIN VREF
LTC1415
10µF
REFCOMP
AGND
1415 F08b
Figure Using LT1019-2.5 External Reference
VREF driven with other means shown Figure This useful applications where peak input signal amplitude vary. input span then adjusted match peak input signal, maximizing signal-to-noise ratio. filtering internal LTC1415 reference amplifier will limit
LTC1450 12-BIT RAIL-TO-RAIL
10µF
REFCOMP
AGND
LTC1415
Figure Driving VREF with Adjust Full Scale
bandwidth settling time this circuit. settling time should allowed after reference adjustment. Differential Inputs LTC1415 unique differential sample-and-hold circuit that allows rail-to-rail inputs. will always convert difference +AIN (-AIN) independent common mode voltage. common mode rejection constant from 1MHz, Figure 10a. only requirement that both inputs exceed AVDD AGND power supply voltages. Integral nonlinearity errors (INL) differential nonlinearity errors (DNL) independent common mode voltage, however, bipolar zero error (BZE) will vary. change typically less than 0.1% common mode voltage. Differential inputs allow greater flexibility accepting different input ranges. Figure shows circuit that shifts input range voltage 200mV. This useful applications where amplifier driving input able swing ground, because output loading settling time issues. Some applications have their performance limited distortion. Most circuits exhibit higher distortion when signals approach supply ground. Distortion reduced reducing signal amplitude keeping common mode voltage approximately midsupply. circuit Figure reduces full scale from
LTC1415
APPLICATIONS INFORMATION
4.096V 2.048V shifts common mode voltage from half full scale 2.274V. Coupled Inputs analog inputs coupled applications where input information. input
SIGNAL/(NOISE DISTORTION) (dB) 100k INPUT FREQUENCY (Hz)
LTC1415 F10b LTC1415 F10a
Figure 10a. CMRR Input Frequency
ANALOG INPUT 1.25V 3.298V VOUT 1.2V LT1004-1.2 LTC1415 +AIN -AIN VREF
10µF
REFCOMP
AGND
LTC1415 F10c
Figure 10c. 2.048V Input Range with Common Mode Voltage 2.274V. Distortion Applications
ANALOG INPUT 2.048VP-P LT1004-1.2 +AIN -AIN VREF
Figure 10e. 2.048VP-P Input Range with Coupling. Distortion Applications
does need biased midscale. Figures demonstrate coupling required biasing. Figure shows with full scale 4.096V, common mode voltage 2.048V input that swings from 4.096V. This circuit lowest noise (SINAD 72dB 100kHz) will have distortion
ANALOG INPUT +AIN 0.2V 4.296V 3.9k
-AIN LTC1415 VREF
REFCOMP
10µF AGND
Figure 10b. Shifting Input Range from Ground 200mV
ANALOG INPUT 4.096VP-P 10µF AGND
LTC1415 F10d
+AIN -AIN VREF LTC1415 REFCOMP
Figure 10d. 4.096VP-P Input Range with Coupling. Noise Applications
LTC1415 REFCOMP
10µF
AGND
LTC1415 F10e
LTC1415
APPLICATIONS INFORMATION
limitations high input frequencies (THD 75dB 600kHz). Figure full scale 2.048V common mode 2.27V. reduced signal swing this circuit results improved distortion higher input frequencies (THD 82dB 600kHz) with worse SINAD frequencies (SINAD 70dB 100kHz). Full-Scale Offset Adjustment Figure shows ideal input/output characteristics LTC1415. code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB,. 1.5LSB, 0.5LSB). output straight binary with 1LSB FS/4096 4.096V/4096 1mV.
10µF ANALOG INPUT 0.1µF
111.111 111.110 111.101 OUTPUT CODE
000.010 000.001 000.000 1LSB INPUT VOLTAGE 1LSB
LTC1415 F11a
Figure 11a. LTC1415 Transfer Characteristics
applications where absolute accuracy important, offset full-scale errors adjusted zero. Offset error must adjusted before full-scale error. Figure shows extra components required full-scale error adjustment. Zero offset achieved adjusting offset applied input. zero offset error apply 0.5mV (i.e., 0.5LSB) +AIN adjust offset input (R8) until output code flickers between 0000 0000 0000 0000 0000 0001. full-scale adjustment, input voltage 4.0945V 1.5LSBs) applied analog input adjusted until
+AIN -AIN VREF
LTC1415
REFCOMP
AGND
LTC1415 F11b
Figure 11b. Offset Full-Scale Adjust Circuit
output code flickers between 1111 1111 1110 1111 1111 1111. BOARD LAYOUT GROUNDING Wire wrap boards recommended high resolution high speed converters. obtain best performance from LTC1415, printed circuit board with ground plane required. ground plane under area should free breaks holes possible, such that impedance path between grounds decoupling capacitors provided. critical prevent digital noise from being coupled analog input, reference analog power supply lines. Layout should ensure that digital analog signal lines separated much possible. Particular care should taken digital track alongside analog signal track. analog ground plane separate from logic system ground should established under around ADC. (AGND), (ADC's DGND) other analog grounds should connected this single analog ground point. REFCOMP bypass capacitor DVDD bypass capacitor should also connected this analog ground plane. other digital grounds should connected this analog ground plane. impedance analog digital power supply common returns essential noise operation foil
LTC1415
APPLICATIONS INFORMATION
width these tracks should wide possible. applications where data outputs control signals connected continuously active microprocessor bus, possible errors conversion results. These errors feedthrough from microprocessor successive approximation comparator. problem eliminated forcing microprocessor into WAIT state during conversion using three-state buffers isolate data bus. traces connecting pins bypass capacitors must kept short should made wide possible. LTC1415 differential inputs minimize noise coupling. Common mode noise leads will rejected input CMRR. input used ground sense input; LTC1415 will hold convert difference voltage between AIN. leads (Pin (Pin should kept short possible. applications where this possible, traces should side side equalize coupling. SUPPLY BYPASSING High quality, series resistance ceramic, 10µF bypass capacitors should used REFCOMP pins shown Typical Application fist page this data sheet. Surface mount ceramic capacitors such Murata GRM235Y5V106Z016 provide excellent bypassing small board space. Alternatively 10µF tantalum capacitors parallel with 0.1µF ceramic capacitors used. Bypass capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible. Example Layout Figures 13a, 13b, show schematic layout suggested evaluation board. layout demonstrates proper decoupling capacitors ground plane with layer printed circuit board.
ANALOG INPUT CIRCUITRY
+AIN -AIN REFCOMP AGND 10µF 0.1µF
Figure Power Supply Grounding Practice
LTC1415 AVDD DVDD 0.1µF OVDD DGND OGND
DIGITAL SYSTEM
LTC1415
10µF ANALOG GROUND PLANE
3.3V
LTC1415
74HC574
1.2k
1000pF
1000pF LTC1415 COMP OGND NAP/SLP BUSY CONVST SHDN AVDD DVDD OVDD AGND DGND OVDD 10µF 10µF OVDD HC14 15pF VREF +AIN 74HC574
1000pF
APPLICATIONS INFORMATION
HEADER
10µF
HC14
HC14
JP4D
JP4C
HC14 HC14
DGND DGND
JP4B
SHDN
JP4A
NAP/SLP
LTC1415 F13a
HC14
NOTES: UNLESS OTHERWISE SPECIFIED RESISTOR VALUE OHMS, 1/10W, CAPACITOR VALUES 25V, 50V,
0.1µF
HC14
Figure 13a. Suggested Evaluation Circuit Schematic
AGND DGND
JP2A 3.3V OVDD
OPTIONAL
LT1121-5
VOUT
22µF JP2B 0.1µF 0.1µF
10µF
SS12
LTC1415
APPLICATIONS INFORMATION
Figure 13b. Suggested Evaluation Circuit Board Component Side Silkscreen
Figure 13c. Suggested Evaluation Circuit Board Component Side Layout
LTC1415
APPLICATIONS INFORMATION
Figure 13d. Suggested Evaluation Circuit Board Solder Side Layout
DIGITAL INTERFACE converter designed interface with microprocessors memory mapped device. control inputs common peripheral memory interfacing. separate CONVST used initiate conversion. Internal Clock converter internal clock that eliminates need synchronization between external clock signals found other ADCs. internal clock factory trimmed achieve typical conversion time 0.70µs maximum conversion time over full operating temperature range 0.75µs. external adjustments required. guaranteed maximum acquisition time 150ns. addition, throughput time 800ns minimum sampling rate 1.25Msps guaranteed. Power Shutdown LTC1415 provides power shutdown modes, Sleep, save power during inactive periods.
mode reduces power leaves only digital logic reference powered wake-up time from active 200ns. Follow setup time shown Figure avoid inadvertently invoking Sleep mode. Sleep mode bias currents shut down only leakage current remains, about 1µA. Wake-up time from Sleep mode much slower since reference circuit must power settle 0.01% full 12-bit accuracy. Sleep mode wake-up time dependent value capacitor connected REFCOMP (Pin wake-up time 10ms with recommended 10µF capacitor. Shutdown controlled (SHDN); shutdown when low. shutdown mode selected with (NAP/SLP); high selects Nap.
NAP/SLP SHDN
1415 F14a
Figure 14a. NAP/SLP SHDN Timing
LTC1415
APPLICATI
SHDN
ATIO
CONVST
1415 F14b
Figure 14b. SHDN CONVST Wake-Up Timing
Timing Control Conversion start data read operations controlled three digital inputs: CONVST, logic applied CONVST will start conversion after been selected (i.e., low). Once initiated, cannot restarted until conversion complete. Converter status indicated BUSY output. BUSY during conversion. Figures through show several different modes operation. modes (Figures both tied low. falling edge CONVST starts conversion. data outputs always enabled data latched with BUSY rising edge. Mode shows operation with narrow logic CONVST pulse. Mode shows narrow logic high CONVST pulse. mode (Figure tied low. falling edge CONVST signal again starts conversion. Data outputs three-state until read with signal. Mode used operation with shared databus.
CONV CONVST BUSY DATA DATA DB11 DATA DB11 DATA DB11
1415
Figure Mode CONVST Starts Conversion. Data Outputs Always Enabled
slow memory modes (Figures tied CONVST tied together. starts conversion reads output with signal. Conversions started external sample clock). slow memory mode processor applies logic CONVST), starting conversion. BUSY goes low, forcing processor into WAIT state. previous conversion result appears data outputs. When conversion complete, conversion results appear data outputs; BUSY goes high, releasing processor processor takes CONVST) back high reads conversion data. mode, processor takes CONVST) low, starting conversion reading previous conversion result. After conversion complete, processor read result initiate another conversion.
CONVST
1415
Figure CONVST Setup Timing
LTC1415
APPLICATI
ATIO
tCONV CONVST BUSY DATA DATA DB11
Figure Mode CONVST Starts Conversion. Data Read
tCONV CONVST BUSY
DATA DATA DB11
1415
Figure Mode CONVST Starts Conversion. Data Read
DATA DB11 DATA DB11
1415
LTC1415
APPLICATI
ATIO
CONV CONVST BUSY DATA DATA DB11 DATA DB11
Figure Slow Memory Mode Timing
CONVST BUSY DATA
CONV
DATA DB11
Figure Mode Timing
DATA DB11 DATA DB11-DB0
1415
DATA DB11
1415
LTC1415
PACKAGE DESCRIPTIO
0.205 0.212** (5.20 5.38)
0.005 0.009 (0.13 0.22)
0.022 0.037 (0.55 0.95)
*DIMENSIONS INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSIONS INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
Dimensions inches (millimeters) unless otherwise noted.
Package 28-Lead Plastic SSOP (0.209)
(LTC 05-08-1640)
0.397 0.407* (10.07 10.33)
0.301 0.311 (7.65 7.90)
0.068 0.078 (1.73 1.99)
0.0256 (0.65)
0.010 0.015 (0.25 0.38)
0.002 0.008 (0.05 0.21)
SSOP 0694
LTC1415
PACKAGE DESCRIPTIO
0.291 0.299** (7.391 7.595) 0.010 0.029 (0.254 0.737)
0.009 0.013 (0.229 0.330)
NOTE 0.016 0.050 (0.406 1.270)
NOTE: IDENT, NOTCH CAVITIES BOTTOM PACKAGES MANUFACTURING OPTIONS. PART SUPPLIED WITH WITHOUT OPTIONS *DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
Dimensions inches (millimeters) unless otherwise noted.
Package 28-Lead Plastic Small Outline (Wide 0.300)
(LTC 05-08-1620)
0.697 0.712* (17.70 18.08)
NOTE
0.394 0.419 (10.007 10.643)
0.093 0.104 (2.362 2.642)
0.037 0.045 (0.940 1.143)
0.050 (1.270)
0.014 0.019 (0.356 0.482)
0.004 0.012 (0.102 0.305)
(WIDE) 0996
LTC1415 RELATED PARTS
PART NUMBER LTC1273/75/76 LTC1274/77 LTC1278/79 LTC1282 LTC1409 LTC1410 LTC1419 LTC1605 DESCRIPTION Complete Sampling 12-Bit ADCs with 70dB SINAD Nyquist Power 12-Bit ADCs with Sleep Mode Shutdown High Speed Sampling 12-Bit ADCs with Shutdown Complete 12-Bit with 12mW Power Dissipation Power 12-Bit, 800ksps Sampling 12-Bit, 1.25Msps Sampling with Shutdown 14-Bit, 800ksps Sampling 16-Bit, 100ksps Sampling COMMENTS Lower Power 75mW Cost Effective fSAMPLE 300ksps Lowest Power (10mW) fSAMPLE 100ksps Cost Effective 12-Bit ADCs with Convert Start Input Best 300ksps fSAMPLE 600ksps Fully Specified 3V-Powered Applications, fSAMPLE 140ksps Best Dynamic Performance, fSAMPLE 800ksps, 80mW Dissipation Best Dynamic Performance, SINAD Nyquist 81.5dB SINAD, 150mW from Supplies Single Supply, ±10V Input Range, Power
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417 (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 www.linear-tech.com
sn1415 1415fs LT/TP 0497 PRINTED
LINEAR TECHNOLOGY CORPORATION 1996

DESCRIPTIO 1.25Msps Sample Rate Single Supply Power Dissipation:

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