Literature Number: SPRU782A March 2004 Products Amplifiers Data C

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OMAP5912 Multimedia Processor Real-Time Clock Split Power Reference Guide
Literature Number: SPRU782A March 2004
Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Mailing Address:
Texas Instruments Post Office 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This document describes real-time clock (RTC) block. embedded real-time clock module directly accessible from TIPB interface. This document also describes split power.
Notational Conventions
This document uses following conventions.
Hexadecimal numbers shown with suffix example,
following number hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
following documents describe OMAP5910 device related peripherals. Copies these documents available Internet www.ti.com. Tip: Enter literature number search provided www.ti.com. OMAP5912 Multimedia Processor Device Overview Architecture Reference Guide (literature number SPRU748) introduces setup, components, features OMAP5912 multimedia processor provides high-level view device architecture. OMAP5912 Multimedia Processor OMAP Subsystem Reference Guide (literature number SPRU749) introduces briefly defines main features OMAP3.2 subsystem OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Sybsystem Reference Guide (literature number SPRU750) describes OMAP5912 multimedia processor subsystem. digital signal processor (DSP) subsystem built around core processor peripherals that interface with:
SPRU782A OMAP5912
Related Documentation From Texas Instruments
ARM926EJS microprocessor unit interface (MPUI); Various standard memories external memory interface (EMIF); Various system peripherals peripheral (TIPB) bridge. OMAP5912 Multimedia Processor Clocks Reference Guide (literature number SPRU751) describes clocking mechanisms OMAP5912 multimedia processor. OMAP5912, various clocks created from special components such digital phase locked loop (DPLL) analog phase-locked loop (APLL). OMAP5912 Multimedia Processor Initialization Reference Guide (literature number SPRU752) describes reset architecture, configuration, initialization, boot OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) describes power management OMAP5912 multimedia processor. ultralow-power device (ULPD) generates manages clocks reset signals OMAP3.2 some peripherals. controls chip-level power-down modes handles chip-level wake-up events. deep sleep mode, this module still active monitor wake-up events.This book describes ULPD module outline architecture. OMAP5912 Multimedia Processor Security Features Reference Guide (literature number SPRU754) describes security features OMAP5912 multimedia processor. OMAP5912 security scheme relies OMAP3.2 secure mode. distributed security OMAP3.2 platform Texas Instruments solution address m-commerce security issues within mobile phone environment. OMAP3.2 secure mode developed bring hardware robustness overall OMAP5912 security scheme. OMAP5912 Multimedia Processor Direct Memory Access (DMA) Support Reference Guide (literature number SPRU755) describes direct memory access support OMAP5912 multimedia processor. OMAP5912 processor three DMAs: system embedded OMAP3.2. handles transfers associated with shared peripherals. embedded OMAP3.2. handles transfers associated with peripherals. generic distributed (GDD) OMAP5912 resource attached peripheral. handles only transfers associated with peripheral.
OMAP5912
SPRU782A
Related Documentation From Texas Instruments
OMAP5912 Multimedia Processor Memory Interfaces Reference Guide (literature number SPRU756) describes memory interfaces OMAP5912 multimedia processor. SDRAM (external memory interface fast, EMIFF) Asynchronous synchronous burst memory (external memory interface slow, EMIFS) NAND flash (hardware controller software controller) CompactFlash EMIFS interface Internal static OMAP5912 Multimedia Processor Interrupts Reference Guide (literature number SPRU757) describes interrupts OMAP5912 multimedia processor. Three level interrupt controllers used OMAP5912: level interrupt handler (also referred interrupt level implemented outside OMAP3.2 handle interrupts. level interrupt handler (also referred interrupt level 2.1) instantiated outside OMAP3.2 handle interrupts. OMAP3.2 level interrupt handler (referenced interrupt level 2.0) handle interrupts. OMAP5912 Multimedia Processor Peripheral Interconnects Reference Guide (literature number SPRU758) describes various periperal interconnects OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Timers Reference Guide (literature number SPRU759) describes various timers OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Serial Interfaces Reference Guide (literature number SPRU760) describes serial interfaces OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Universal Serial (USB) Reference Guide (literature number SPRU761) describes universal serial (USB) host OMAP5912 multimedia processor. OMAP5912 processor provides several varieties functionality. Flexible multiplexing signals from OMAP5912 host controller, OMAP5912 function controller, other OMAP5912 peripherals allow wide variety system-level capabilities. Many OMAP5912 pins used USB-related signals signals from other OMAP5912 peripherals. OMAP5912 top-level multiplexing
SPRU782A OMAP5912
Related Documentation From Texas Instruments
controls each individually select several possible internal signal interconnections. When these shared pins programmed signals, OMAP5912 signal multiplexing selects signals associated with three OMAP5912 host ports OMAP5912 function controller brought OMAP5912 pins. OMAP5912 Multimedia Processor Multi-channel Buffered Serial Ports (McBSPs) Reference Guide (literature number SPRU762) describes three multi-channel buffered serial ports (McBSPs) available OMAP5912 device. OMAP5912 device provides multiple highspeed multichannel buffered serial ports (McBSPs) that allow direct interface codecs other devices system. OMAP5912 Multimedia Processor Camera Interface Reference Guide (literature number SPRU763) describes camera inerfaces implemented OMAP5912 multimedia processor: compact serial camera port camera parallel interface. OMAP5912 Multimedia Processor Display Interface Reference Guide (literature number SPRU764) describes display interface OMAP5912 multimedia processor. module data conversion module pulse generator Display interface OMAP5912 Multimedia Processor Multimedia Card (MMC/SD/SDIO) (literature number SPRU765) describes multimedia card (MMC) interface OMAP5912 multimedia processor. multimedia card/secure data/secure digital (MMC/SD/SDIO) host controller provides interface between local host, such microprocessor unit (MPU) digital signal processor (DSP), either memory card, plus four serial flash cards. host controller handles MMC/SD/SDIO serial port interface (SPI) transactions with minimal local host intervention. OMAP5912 Multimedia Processor Keyboard Interface Reference Guide (literature number SPRU766) describes keyboard interface OMAP5912 multimedia processor. MPUIO module enables direct communication between (through public TIPB) external devices. types used: specific I/Os dedicated keyboard connection, general-purpose I/Os. OMAP5912 Multimedia Processor General-Purpose Interface Reference Guide (literature number SPRU767) describes general-purpose OMAP5912 SPRU782A
Related Documentation From Texas Instruments
terface OMAP5912 multimedia processor. There four GPIO modules OMAP5912. Each GPIO peripheral controls dedicated pins configurable either input output general purposes. Each independent control direction programmable register. two-edge control registers configure events (rising edge, falling edge, both edges) input trigger interrupts wake-up requests (depending system mode). addition, interrupt mask register masks specified pins. Finally, GPIO peripherals provide clear capabilities data output registers interrupt mask registers. After detection, event sources merged single synchronous interrupt (per module) generated active mode, whereas unique wake-up line issued idle mode. Eight data output lines GPIO3 ORed together generate global output line OMAP5912 boundary. This global output line used conjunction with provide CMT-APE interface OMAP5912. OMAP5912 Multimedia Processor VLYNQ Serial Communications Interface Reference Guide (literature number SPRU768) describes VLYNQ OMAP5912 multimedia processor. VLYNQ serial communications interface that enables extension internal segment more external physical devices. external devices mapped into local, physical address space appear they internal OMAP 5912. external devices must also have VLYNQ interface. VLYNQ module serializes transactions device, transfers serialized data between devices VLYNQ port, de-serializes transaction external device. OMAP5912 includes VLYNQ module connected OCPT2 target port OCPI initiator port. These connections configured static switch, which selects either VLYNQ module. This switch, forbids simultaneous GDD/SSI VLYNQ. switch controlled VLYNQ_EN OMAP5912 configuration control register (CONF_5912_CTRL). OMAP5912 Multimedia Processor Pinout Reference Guide (literature number SPRU769) provides pinout OMAP5912 multimedia processor. After power-up reset, user change configuration default interfaces. another interface available default, possible enable interface each ball setting corresponding 3-bit field associated FUNC_MUX_CTRL register. also possible configure on-chip pullup/pulldown. This document
SPRU782A OMAP5912
Trademarks
also describes various power domains that user apply different interfaces seamlessly with external components. OMAP5912 Multimedia Processor Window Tracer (WT) Reference Guide (literature number SPRU770) describes window tracer module used capture memory transactions from four interfaces: EMIFF, EMIFS, OCP-T1, OCP-T2. This module located OMAP3.2 traffic controller (TC). OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (literature number SPRUxxx) describes real-time clock OMAP5912 multimedia processor. real-time clock (RTC) block embedded real-time clock module directly accessible from TIPB interface.
Trademarks
OMAP OMAP symbol trademarks Texas Instruments.
OMAP5912
SPRU782A
Contents
Contents
Overview Split Power Overview Internal Level Shifters Split Power Block Interface Block Backup Block Output Control Backup Signal Management On-Chip Reset Generation Resets OMAP5912 Device With Split Power Feature Enabled Resets OMAP5912 Device With Split Power Feature Used RTC_WAKE_INT Using Split Power Functions Incompatible With Split Power Functions Compatible With Split Power Description Description
Interrupt Management Timer Interrupt Alarm Interrupt Oscillator Drift Compensation
Split Power Compatibility Registers 11.1 Time Calendar Registers Time Calendar Alarm Registers 11.2 General Registers 11.3 Compensation Registers Setting Time Calendar Information 12.1 Modify Time Calendar Registers 12.2 Rounding Seconds 12.2.1 Time Calendar Registers
Figures
Figures
Real-Time Clock Split Power System OMAP5912 Internal Level Shifter Split Power Block Diagram ASIC Reset Scheme PWRON_RESET Connection RTC_WAKE_INT Generation OMAP5912 RESET_MODE RTC_CTRL_REG.SPLIT_POWER Startup With RTC_CTRL_REG.SPLIT_POWER OMAP5912 RESET_MODE With SPLIT POWER OMAP5912 RESET_MODE With RTC_CTRL_REG.SPLIT_POWER OMAP5912 RESET_MODE Periodic Interrupt Alarm Interrupt Oscillator Drift Compensation Time Calendar Register Time Calendar Alarm Register Access Compensation Scheduling
OMAP5912
SPRU782A
Tables
Tables
Timer Interrupt Events Registers Time Calendar Register Time Units Seconds Register (SECONDS_REG) Minutes Register (MINUTES_REG) Hours Register (HOURS_REG) Days Register (DAYS_REG) Months Register (MONTHS_REG) Years Register (YEARS_REG) Weeks Register (WEEKS_REG) Reserved Alarm Seconds Register (ALARM_SECONDS_REG) Alarm Minutes Register (ALARM_MINUTES_REG) Alarm Hours Register (ALARM_HOURS_REG) Alarm Days Register (ALARM_DAYS_REG) Alarm Months Register (ALARM_MONTHS_REG) Alarm Years Register (ALARM_YEARS_REG) Control Register (RTC_CTRL_REG) Status Register (RTC_STATUS_REG) Interrupts Register (RTC_INTERRUPTS_REG) Compensation Register (RTC_COMP_LSB_REG) Compensation Register (RTC_COMP_MSB_REG) Oscillator Register (RTC_OSC_REG)
SPRU782A
OMAP5912
Real Time Clock (RTC)
Overview
real-time clock (RTC) block embedded real-time clock module directly accessible from TIPB interface. basic functions block are:
Time information (seconds/minutes/hours) directly binary coded
decimal (BCD) code
Calendar information (day/month/year/day week) directly
code year 2099
Interrupt generation, periodically (1s/1m/1h/1d period) precise time
(alarm function)
30-s time correction Oscillator frequency calibration
Figure shows real-time clock block.
SPRU782A
Real-Time Clock (RTC)
Split Power Overview
Figure
Real-Time Clock
32-kHz counter
Compensation
Week days
Control
Seconds
Minutes
Hours
Days
Months
Years
IRQ_ALARM Interrupt Alarm IRQ_ALARM
IRQ_TIMER
Split Power Overview
achieve minimum consumption state device equipment, some active logic elements supplied. Those elements real-time clock (RTC) 32-kHz oscillator (OSC32K) digital baseband (DBB), power-on reset (POR) dedicated regulator analog baseband (ABB). This approach possible when using split power, which splits core power domain into subdomains powered with different voltage supplies. Internal level shifters handle separation between core active domain.
Real-Time Clock (RTC)
SPRU782A
Internal Level Shifters
Figure
Split Power System OMAP5912
OMAP5912 CVDDRTC DVDDRTC RESERWRON_CORE RESET_MODE RTC_ON_NOFF RTC_WAKE_INT Split power logic control POWERDOWN Split power ring level shifters
PWRON_RESET CLK32K_OUT reset select CLK32K_IN XO32K conf registers XO32K CLK32K
External level shifter Internal level shifter Direct
Internal Level Shifters
Internal level shifters library-standard macrocells that interface core domains powered with different voltage supplies. cell seen means isolate power domain from other. case where domain shut down. level shifters ensure known state boundary domains. level shifters divided into parts:
UC469: Powered primary power supply. Because input signal
creates which buffered inverted, respectively.
SPRU782A Real-Time Clock (RTC)
Split Power Block
UC470: Powered secondary power supply. Because
differential signals, (given UC469), creates signal that equivalent input UC469 second core supply domain. This cell PWRDN signal that when power supply UC469 does exist (input signals ambiguous), this cell does have through-current output
Figure
Internal Level Shifter
CVDD CVDDRTC
UC469
UC470 PWRDN
PWRDN PWRDN
Split Power Block
split power module contains blocks: interface block backup block. interface block, between core backup elements, supplied core power supply CVDD. backup block contains some logic.
Real-Time Clock (RTC)
SPRU782A
Output Control
Figure
Split Power Block Diagram
UC469 UC470
CLK_32kHz_CORE
UC469 UC469
UC470 pwrdn
UC470 pwrdn
UC469
UC470
pwrdn
UC469
UC470 pwrdn
UC469
UC470
pwrdn TIPB pwrdn
Interface block
Backup block
Interface Block
This block separates backup elements ASIC core. also contains UC469 some logic. logic allows masking TIPB signals avoid consumption internal level shifters, except accesses.
Backup Block
This block contains elements kept mode DBB, RTC, 32-kHz clock, UC470, logic force mode. module input/outputs RTC_ON_NOFF, PWRON_RESET, RTC_WAKE_ INT, RESET_MODE, POWERDOWN.
Output Control
keep them from supplying ASIC core, split power block outputs forced logical zero.
SPRU782A
Real-Time Clock (RTC)
On-Chip Reset Generation
Backup Signal Management
mode, only split power module supplied. ON_OFF, RTC_WAKE_INT, PWRON_RESET signals, which control activity management DBB, also active.
On-Chip Reset Generation
RTC_CTRL_REG.SPLIT_POWER RESET_MODE then
OMAP5912 reset only PWRON_RESET.:
RESET_MODE RTC_CTRL_REG.SPLIT_POWER= then
PWRON_RESET RTC_ON_NOFF will reset OMAP5912.:
Figure
ASIC Reset Scheme
PWRON_RESET RTC_ON_NOFF RESPWRON_CORE
RTC_CTRL_REG.SPLIT_POWER
RESET_MODE
Resets OMAP5912 Device With Split Power Feature Enabled
module internal real time counter reset PWRON_RESET during power OMAP5912 ASIC gates reset PWRON_RESET_CORE. Subsequent resets asserted with RTC_ON_NOFF. module reset assertion RTC_ON_NOFF. While RTC_ON_NOFF asserted low, system powers down OMAP5912 ASIC gates.
Resets OMAP5912 Device With Split Power Feature Used
OMAP5912 devices that forced during reset reset mode PWRON_RESET_CORE logically equal PWRON_RESET only PWRON_RESET. OMAP5912 devices that forced during reset reset mode (OMAP1510 legacy) split power, PWRON_RESET_CORE logically equal PWRON_RESET only PWRON_RESET.
Real-Time Clock (RTC)
SPRU782A
On-Chip Reset Generation
Figure
PWRON_RESET Connection
ON_OFF Split power block RESPWRON_CORE ULPD CHIP_RESET
PWRON_RESET RESET_MODE
Core reset
RTC_WAKE_INT
RTC_WAKE_INT collects interrupt sources used awaken ULPD from deep sleep. gated with RTC_CTRL_REG.SPLIT_POWER alarm. mode IRQ_SET only IRQ_ALARM_EXT generate interrupt RTC_WAKE_INT. With device state, both IRQ_ALARM_EXT IRQ_SET generate RTC_WAKE_INT. RTC_CTRL_REG.SPLIT_POWER signal generates RTC_WAKE_INT avoid RTC_WAKE_INT mode ABB. Figure shows generation RTC_WAKE_INT. OMAP5912 core, IRQ_SET used RTC_WAKE_INT used only ABB.
SPRU782A
Real-Time Clock (RTC)
Using Split Power
Figure
RTC_WAKE_INT Generation
IRQ_ALARM_EXT SPLIT_POWER
RTC_WAKE_INT
Interrupts from that awake ULPD IRQ_SET
Using Split Power Functions Incompatible With Split Power
split power. power cannot core.
Figure
OMAP5912 RESET_MODE RTC_CTRL_REG.SPLIT_POWER
Power Reset release
CLK32K_IN
Unknown
PWRON_RESET
Unknown
RTC_ON_NOFF
Don't care
RESPWRON_CORE
Unknown
CLK32K_CORE
Unknown
POWERDOWN
Unknown
RESET_MODE_0
Real-Time Clock (RTC)
SPRU782A
Using Split Power
Functions Compatible With Split Power
Figure Startup With RTC_CTRL_REG.SPLIT_POWER OMAP5912 RESET_MODE
Main battery insertion Start core clock
CLK_32_OUT
RTC_ON_NOFF
RESPWRON_CORE
CLK32K_CORE
RESET_MODE
Figure assumes that backup battery already inserted, only power domain powered that isolated from core (RTC_ON_NOFF ball held low, SPLIT_POWER Once `the main battery plugged core domain reset PWRON_RESET_CORE until RTC_ON_NOFF becomes high; isolation mode also becomes inactive. ULPD state machine start.
SPRU782A
Real-Time Clock (RTC)
Using Split Power
Figure
Description
With SPLIT POWER OMAP5912 RESET_MODE
Switch event
Internal 32kHz Clock PWRON_RESET RTC_ON_NOFF
RESPWRON_CORE CLK32K_CORE POWERDOWN RESET_MODE_0
switch-off event, RTC_ON_NOFF 32-kHz clock OMAP5912 core anymore, PWRON_RESET_CORE indicate that device goes into state. PWRON_RESET_CORE becomes active, DBBcore reset. POWERDOWN becomes active backup module isolated. circuit disables CORE regulators, thus core powered.
Real-Time Clock (RTC)
SPRU782A
Using Split Power
Figure
Description
With RTC_CTRL_REG.SPLIT_POWER OMAP5912 RESET_MODE
Switch Event Start 32-kHz Core Clock
Internal CLK_32 PWRON_RESET RTC_ON_NOFF
RESPWRON_CORE CLK32K_CORE POWERDOWN
RESET_MODE_0
switch-on event, ASIC regulators enabled. core also supplied reset PWRON_RESET_CORE until RTC_ON_NOFF Then, isolation mode inactive, ULPD state machine receives PWRON_RESET_CORE, clock starts state machine.
Interrupt Management
generate three interrupts:
timer interrupt (IRQ_TIMER), alarm interrupt (IRQ_ALARM_CHIP) alarm interrupt external (IRQ_ALARM_EXT IRQ_ALARM_CHIP
inverted)
Timer Interrupt
IRQ_TIMER interrupt generated periodically, every second, every minute, every hour, everyday (RTC_INTERRUPTS_REG[1:0]).
SPRU782A
Real-Time Clock (RTC)
Using Split Power
IT_TIMER interrupt register enables this interrupt. negative edge-sensitive interrupt (low-level pulse duration µs). RTC_STATUS_REG[5:2] only updated each interrupt show events that have occurred, according Table
Table
Timer Interrupt Events
RTC_INTERRUPTS_REG[1:0] RTC_STATUS_REG[5] (DAY) RTC_STATUS_REG[4] (HOUR) RTC_STATUS_REG[3] (MIN) RTC_STATUS_REG[2] (SEC)
when this event concurrent with programmed periodical period.
Figure
CLK_32kHz
Periodic Interrupt
CPT_32kHz
32766
32767
BUSY
IRQ_ALARM
Alarm Interrupt
IRQ_ALARM_CHIP interrupt generated when time into time calendar ALARM registers identical time calendar registers. This interrupt then generated IT_ALARM interrupt register set. This interrupt low-level sensitive. RTC_STATUS_REG[6] indicates that IRQ_ALARM_CHIP occurred. This interrupt disabled writing into RTC_STATUS_REG[6].
Real-Time Clock (RTC)
SPRU782A
Using Split Power
Figure
CLK_32kHz
Alarm Interrupt
CPT_32kHz
32767
BUSY Alarm register register
IRQ_ALARM
Write into STATUS[6]
Oscillator Drift Compensation
compensate inaccuracy 32-kHz oscillator, perform calibration oscillator frequency, calculate drift compensation versus one-hour period, load compensation registers with drift compensation value. Autocompensation enabled AUTO_COMP_EN RTC_CTRL register. COMP_REG value positive, compensation occurs after second change event. COMP_REG cycles removed from next second. COMP_REG value negative, compensation occurs before second change event. COMP_REG cycles added current second. This compensation enables 32-kHz period accuracy each hour. waveform Figure summarizes positive negative compensation effect.
SPRU782A
Real-Time Clock (RTC)
Using Split Power
Figure
Oscillator Drift Compensation
compensation
Timer counter Second update 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 0000 0001
Negative compensation: COMP_REG Timer counter Second update cycles removed from next cond. Positive compensation: COMP_REG (0xFFFE) Timer counter Second update cycles added current second.
7FFA
7FFB
7FFC
7FFD
7FFE
7FFF
0002
0003
7FFA
7FFB
7FFC
7FFD
7FFE
7FFF
7FFE
7FFF
0000
Split Power Compatibility
32-kHz oscillator only elements that must active device state. Therefore, been modified split power. register been modified (RTC_CTRL_REG), register been added (RTC_RES_PROG_REG). RTC_CTRL_REG, RTC_CTRL_REG.SPLIT_POWER been added user choose whether power split mode. RTC_RES_PROG_REG been added back resistance value oscillator state.
Real-Time Clock (RTC)
SPRU782A
Using Split Power
power-down signal been added outputs OFF.
Registers
There three types registers:
Time calendar, time calendar alarm General Compensation
These three types have their access constraints.
11.1
Time Calendar Registers Time Calendar Alarm Registers
read write correct data from/to time calendar registers time calendar alarm registers, must first read BUSY STATUS register until BUSY equal zero. From this time, time (the available access period), perform several accesses into time calendar registers time calendar alarm registers with guaranteed read/write data. available access period, must restart previous sequence. accesses time calendar registers during unavailable access period, access ensured.
remove possibility interrupting registers read process, thus introducing potential risk violating authorized 15-µs access period, strongly recommended that user disable incoming interrupts during register read process.
SPRU782A
Real-Time Clock (RTC)
Using Split Power
Figure
Time Calendar Register Time Calendar Alarm Register Access
Available regiter access Read BUSY Forbidden register access Available regiter access Available regiter access
STROBE
Read/Write register access BUSY
CLK_32kHz
CPT_32kHz
32766
32767
UPDATE
11.2
General Registers
access STATUS_REG CTRL_REG time (with exception CTRL_REG[5] bit, which must changed only when stopped). INTERRUPTS_REG, must respect available access period prevent spurious interrupt. RTC_DISABLE CTRL register must used only completely disable function. When this set, 32-kHz clock gated, frozen. From this point, resetting this zero lead unexpected behavior. This must only used function unwanted application, save power.
11.3
Compensation Registers
Access COMP_MSB_REG COMP_LSB_REG registers must respect available access period. These registers must updated during compensation (first second each hour), they updated during second access period preceding compensation event. example, load compensation value into these registers after each hour event during available access period.
Real-Time Clock (RTC)
SPRU782A
Using Split Power
Figure
Compensation Scheduling
HOURS SECONDS
Load comp registers Compensation event Compensation event
HOURS COMP_EN SECONDS BUSY
Hour event
Load comp registers
Compensation event
12.1
Setting Time Calendar Information Modify Time Calendar Registers
modify current time, writes time into time calendar registers time/calendar information. write into time calendar registers without stopping RTC, this case must read status register sure that updating takes place more than (bit BUSY must must perform changes less than prevent partial updating between beginning writingsequence into time calendar registers. Also, stop clearing STOP_RTC control register (owing internal resynchronization, status must checked ensure that frozen), updating time calendar values, restarting resetting STOP_RTC bit.
SPRU782A
Real-Time Clock (RTC)
Using Split Power
12.2
Rounding Seconds
Time rounded closest minute setting ROUND_30S control register. When this set, time calendar values closest minute value next second. ROUND_30S automatically cleared when rounding time performed. Example: current time 10H59M45S, round operation changes time 11H00M00S. current time 10H59M29S, round operation changes time 10H59M00S. Table lists registers. tables below describe register bits. register types grouped follows:
General registers Compensation registers Time calendar alarm registers Time calendar registers
Table
Name
Registers
Base Address 0xFFFB 4800 Description Seconds Minutes Hours Days Months Years Weeks Reserved Alarm seconds Alarm minutes Alarm hours Alarm days Alarm months Alarm years Reserved Address Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38
SECONDS_REG MINUTES_REG HOURS_REG DAYS_REG MONTHS_REG YEARS_REG WEEKS_REG RESERVED ALARM_SECONDS_REG ALARM_MINUTES_REG ALARM_HOURS_REG ALARM_DAYS_REG ALARM_MONTHS_REG ALARM_YEARS_REG RESERVED
Real-Time Clock (RTC)
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Using Split Power
Table
Name RESERVED
Registers (Continued)
Base Address 0xFFFB 4800 Description Reserved control status interrupt compensation compensation oscillator Address Offset 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54
RTC_CTRL_REG RTC_STATUS_REG RTC_INTERRUPTS_REG RTC_COMP_LSB_REG RTC_COMP_MSB_REG RTC_OSC_REG
12.2.1
Time Calendar Registers
time calendar information available dedicated registers, called time calendar registers. These register values written binary coded decimal (BCD) code.
Table
Time Unit Year
Time Calendar Register Time Units
Range Remarks Leap year: year divisible four Common year: other years
Month
months months month (leap year) month (common year)
Week Hour
Weekday hours mode AM/PM mode
SPRU782A
Real-Time Clock (RTC)
Using Split Power
Table
Minutes Seconds
Time Calendar Register Time Units (Continued)
Table
Seconds Register (SECONDS_REG)
Base Address 0xFFFB 4800, Offset 0x00 Name SEC1 Function digit seconds Range Reset 0000
SEC0
digit seconds Range
0000
Table
Minutes Register (MINUTES_REG)
Base Address 0xFFFB 4800, Offset 0x04 Name MIN1 Function digit minutes Range Reset 0000
MIN0
digit minutes Range
0000
Table
Hours Register (HOURS_REG)
Base Address 0xFFFB 4800, Offset 0x08 Name PM_AM Function Only used PM_AM mode (otherwise Reset
HOUR1
digit hours Range
HOUR0
digit hours Range
0000
Table
Days Register (DAYS_REG)
Real-Time Clock (RTC) SPRU782A
Using Split Power
Table
Days Register (DAYS_REG) (Continued)
Base Address 0xFFFB 4800, Offset 0x0C Name DAY1 Function digit days Range Reset 0000
DAY0
digit days Range
0001
Table
Months Register (MONTHS_REG)
Base Address 0xFFFB 4800, Offset 0x10 Name MONTH1 Function digit months Range Reset 0000
MONTH0
digit months Range
0001
Usual notation taken month value: January February December
Table
Years Register (YEARS_REG)
Base Address 0xFFFB 4800, Offset 0x14 Name YEAR1 Function digit years Range Reset 0000
YEAR0
digit years Range
0000
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Real-Time Clock (RTC)
Using Split Power
Table Weeks Register (WEEKS_REG)
Base Address 0xFFFB 4800, Offset 0x18 Name WEEK Function digit days week Range Reset 0000
Table
???:0
Reserved
Base Address 0xFFFB 4800, Offset 0x1C Name RESERVED Function Reserved Reset
Table Alarm Seconds Register (ALARM_SECONDS_REG)
Base Address 0xFFFB 4800, Offset 0x20 Name ALARM_SEC1 Function digit seconds Range ALARM_SEC0 digit seconds Range 0000 Reset 0000
Table Alarm Minutes Register (ALARM_MINUTES_REG)
Base Address 0xFFFB 4800, Offset 0x24 Name ALARM_MIN1 Function digit minutes Range ALARM_MIN0 digit minutes Range 0000 Reset 0000
Real-Time Clock (RTC)
SPRU782A
Using Split Power
Table Alarm Hours Register (ALARM_HOURS_REG)
Base Address 0xFFFB 4800, Offset 0x28 Name ALARM_PM_AM Function Only used PM_AM mode (otherwise ALARM_HOUR1 digit hours Range ALARM_HOUR0 digit hours Range 0000 Reset
Table Alarm Days Register (ALARM_DAYS_REG)
Base Address 0xFFFB 4800, Offset 0x2C Name ALARM_DAY1 Function digit days Range ALARM_DAY0 digit days Range 0001 Reset 0000
Table Alarm Months Register (ALARM_MONTHS_REG)
Base Address 0xFFFB 4800, Offset 0x30 Name ALARM_MONTH1 Function digit months Range ALARM_MONTH0 digit months Range 0001 Reset 0000
Table Alarm Years Register (ALARM_YEARS_REG)
Base Address 0xFFFB 4800, Offset 0x34 Name ALARM_YEAR1 Function digit years Range Reset 0000
SPRU782A
Real-Time Clock (RTC)
Using Split Power
Table Alarm Years Register (ALARM_YEARS_REG) (Continued)
Base Address 0xFFFB 4800, Offset 0x34 Name ALARM_YEAR0 Function digit years Range Reset 0000
Table Control Register (RTC_CTRL_REG)
Base Address 0xFFFB 4800, Offset 0x40 Name SPLIT_POWER Function Cannot split power split power RTC_disable enabled disabled 32-kHz clock) SET_32_COUNTER action 32-kHz counter with COMP_REG value. TEST_MODE Functional mode Test mode (autocompensation enabled when 32-kHz counter reaches end) MODE_12_24 24-hour mode 12-hour mode (PM/AM mode) AUTO_COMP autocompensation Autocompensation enabled ROUND_30S update When written, time rounded closest minute. STOP_RTC frozen. running. Reset
SET_32_COUNTER must only used when frozen. ROUND_30S toggle bit. only write clears sets ROUND_30S then reads read until round-to-the-closest-minute performed next second.
Real-Time Clock (RTC) SPRU782A
Using Split Power
MODE_12_24: possible switch between modes time without disturbing RTC. Read write always performed with current mode.
Table Status Register (RTC_STATUS_REG)
Base Address 0xFFFB 4800, Offset 0x44 Name POWER_UP ALARM Function Indicates that reset occurred Indicates that alarm interrupt been generated occurred. hour occurred. minute occurred. second occurred. frozen. running. BUSY Updating event more than Updating event Reset
1D_EVENT 1H_EVENT 1M_EVENT 1S_EVENT
alarm interrupt keeps level until writes ALARM RTC_STATUS_REG register. timer interrupt low-level pulse (15-µs duration). shows real state RTC. Because STOP_RTC signal resynchronized 32-kHz clock, action this delayed. POWER_UP reset cleared writing this bit.
SPRU782A
Real-Time Clock (RTC)
Using Split Power
Table Interrupts Register (RTC_INTERRUPTS_REG)
Base Address 0xFFFB 4800, Offset 0x48 Name IT_ALARM Function Enables interrupt when alarm value reached (time calendar alarm registers) time calendar registers Enable periodic interrupt Interrupt disabled Interrupt enabled EVERY Interrupt period Every second Every minute Every hour Every Reset
IT_TIMER
Note: must respect BUSY period prevent spurious interrupt.
Table Compensation Register (RTC_COMP_LSB_REG)
Base Address 0xFFFB 4800, Offset 0x4C Name RTC_COMP_LSB Function Indicates number 32-kHz periods added into 32-kHz counter every hour Reset 0x00
Note: This register must written twos complement. This means that 32-kHz oscillator period every hour, must write FFFF into RTC_COMP_MSB_REG RTC_COMP_LSB_REG. remove 32-kHz oscillator period every hour, must write 0001 into RTC_COMP_MSB_REG RTC_COMP_LSB_REG. 7FFF value allowed.
Real-Time Clock (RTC)
SPRU782A
Using Split Power
Table Compensation Register (RTC_COMP_MSB_REG)
Base Address 0xFFFB 4800, Offset 0x50 Name RTC_COMP_MSB Function Indicates number 32-kHz periods added into 32-kHz counter every hour Reset 0x00
Table Oscillator Register (RTC_OSC_REG)
Base Address 0xFFFB 4800, Offset 0x54 Name OSC32K_PWRDN_R Function Control 32-kHz oscillator power down (function mode) Value oscillator resistance Reset
SW_RES_PROG
oscillator receives register value when TST_OSC32K_MUX_CTRL (functional mode otherwise, value resistance power down from JTAG register.
SPRU782A
Real-Time Clock (RTC)
Real-Time Clock (RTC)
SPRU782A
Index
Index
Internal level shifters registers setting time calendar information split power split power block split power compatibility using split power related documentation from Texas Instruments interrupt management oscillator drift compensation output control registers
notational conventions
Onchip reset generation
Power management, real time clock
Setting time calendar information Split power Split power block Split power compatibility Split power overview
Real time clock internal level shifters interrupt management onchip reset generation oscillator drift compensation output control
trademarks
SPRU782A
Index

Literature Number: SPRU782A March 2004 Products Amplifiers Data C

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