MSC8101 Programmer's Quick Reference 16-Bit Digital Signal Proces
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MSC8101 Programmer's Quick Reference
16-Bit Digital Signal Processor
MSC8101PG/D Revision December 2000
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USA/EUROPE Motorola Literature Distribution P.O. 5405 Denver, Colorado 80217 JAPAN Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre King Street Industrial Estate N.T., Hong Kong 852-26668334 Home Page http://www.mot.com/SPS/DSP Helpline email: dsphelp@dsp.sps.mot.com
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Introduction
MSC8101 Block Diagram
Pins External Signals
Reset
Memory Maps
Registers
Interrupts
Instructions
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Introduction
MSC8101 Block Diagram
Pins External Signals
Reset
Memory Maps
Registers
Interrupts
Instructions
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Contents
Introduction MSC8101 Block Diagram Pins External Signals Package Pinout. External Signals Dedicated Assignments Port. Reset. Reset Causes Reset Actions Each Reset Source External Configuration Signals Hard Reset Configuration Word Host-Port Registers After Reset. Memory Maps. Registers Core Registers Extended Core Registers Registers CPM, Parallel Ports Interrupts. Interrupt Structure Interrupt Priorities Vector Tables CPM. Protocols Supported. Interfaces Supported Serial Performance. Parameter Values Command Operation Codes (Opcodes) Instructions. SC140 Instruction Type Grouping Rules. Conventions, Syntax, Abbreviations Instructions Grouped Alphabetically
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Figures
Figure 2-1. Figure 3-1. Figure 3-2. Figure 6-1. Figure 6-2. Figure 7-1. MSC8101 Block Diagram MSC8101 Flip Chip Plastic Ball Grid Array (FC-PBGA), View MSC8101 Flip Chip Plastic Ball Grid Array (FC-PBGA), Bottom View SC140 Programming Model Port Functional Block Diagram. MSC8101 Interrupt Flow Diagram
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Tables
Table 1-1. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 6-5. Table 6-6. Table 6-7. Table 6-8. Table 6-9. Table 6-10. Table 6-11. Table 6-12. Table 6-13. Table 6-14. Table 7-1. Table 7-2. Table 7-3. Table 8-1. MSC8101 Related Documentation External Signals-SIU Extended Core External Signals-CPM Port A-Dedicated Assignment (PPARA Port Dedicated Assignment (PPARB Port Dedicated Assignment (PPARC Port Dedicated Assignment (PPARD Reset Causes Reset Actions Each Reset Source External Configuration Signals. Hard Reset Configuration Word Core-Side Registers After Reset Host-Side Registers After Reset SC140 Core Internal Memory QBus Memory Map-Bank0 QBus Memory Map-Bank1 PowerPC Local Memory PowerPC Memory Register Description Conventions Core Registers Summary Core Registers. QBus Registers HDI16 Registers EFCOP Registers Registers Registers Reset Registers Interrupt Registers. Clocks Registers Memory Controller Registers Registers Parallel Port Registers SIC_EXT Interrupt Source Priority SIC_EXT Interrupt Vectors Interrupt Vectors MSC8101 Protocols Supported versus Channels
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Tables
Table 8-2. Table 8-3. Table 8-4. Table 8-5. Table 8-6. Table 9-1. Table 9-2. Table 9-3. Table 9-4. Table 9-5.
Interfaces Supported MSC8101 Serial Performance Parameter Command Register Command Operation Codes (Opcodes) Instruction Conventions Operations Syntax. Assembler Syntax Register Abbreviations Instructions Grouped Alphabetically
viii
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Introduction
This quick reference designed give programmers fast, easy access summary information aspects MSC8101 device. synthesizes condenses information from multiple sources, including documentation both SC140 core MSC8101 device. details topics covered here, refer documents listed Table 1-1.
Table 1-1. MSC8101 Related Documentation
Name MSC8101 Data Sheet Description Details signals, AC/DC characteristics, PLL/DLL performance issues, package pinout, electrical design considerations MSC8101. Details program MSC8101. Outlines system-level components describes MSC8101 functions system level. Describes MSC8101 architecture functionality detail, with chapter each MSC8101 blocks. Covers SC140 core architecture, instruction set, clock generator, enhanced OnCE(EOnCE). Available http://www.mot.com/SPS/DSP Cover various programming topics related StarCore MSC8101; available http://www.mot.com/SPS/DSP Tools-related documentation available http://www.mot.com/SPS/DSP Order Number MSC8101/D
MSC8101 User's Guide
MSC8101UG/D
MSC8101 Reference Manual
MSC8101RM/D
SC140 Core Reference Manual
MNSC140CORE/D
Application Notes
SC100 Application Binary Interface Reference Manual SC100 Assemply Language Tools User's Manual SC100 C/C++ Compiler User's Manual
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MSC8101 Block Diagram
`MCC' UART HDLC Transparent Enet FastEnet SCCs UTOPIA Interface Interrupt Controller Timers Parallel Baud Rate Generators Dual Ported Bridge SDMA RISC 64-bit PowerPC Local Q2PPC 128-bit QBus Bridge Boot HDI16 SRAM Interface MEMC Engine
64-bit PowerPCBus MEMC 64/32-bit PowerPC System
Serial Interface
System Protection Reset Control Clock Control SIC_EXT
TDMs
Interrupts
Other Peripherals
Extended Core
Program Sequencer Address Register File Address EOnCEClock/PLL Data Register File Data
Interrupts EFCOP 8/16-bit Host Interface
SC140 Core
JTAG
Power Management
128-bit P-Bus 64-bit Data 64-bit Data
Figure 2-1. MSC8101 Block Diagram
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Package Pinout
Pins External Signals
Package Pinout
View
IRQ5
IRQ1
IRQ3
PWE6
BADDR BADDR BADDR
THERM
IRQ4
THERM
IRQ2
IRQ6
PWE5
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
PSDA PWE7
IRQ7
BCTL0
PA31
TRST
VDDH
VDDH
VDDH
PB30
PD31
PC31
PB31
BADDR BADDR
PWE4
PA29
PD30
PC30
PA30
VDDH
VDDH
PSDA
PGTA
PWE3
PA28
PD29
PC29
PB29
VDDH
PWE2
VDDH
PWE1
PWE0
PA27
PB28
PC28
PC27
BCTL1
PB27
PC26
PB26
VDDH
PA26
PA16
PC25
PA25
PB25
PC23
PD17
CLKIN
TSIZ3
VDDH
VDDH
PC24
PA24
PB24
PA23
PB20
DLL_IN
PC22
SPARE PB22
PA22
PB18
PA19
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
PB21
PA20
PA17
PC13
PC14
SYN1 SYN1
PA12
AACK
VDDH
PA21
PB19
PD18
PD16
CONF
PA13
PA10
SPARE ARTRY TBST TSIZ0
PB23
PD19
PC15
PC12
NMI_ HRESET
PA11
PA18
PA15 SRESET RESET TEST
PA14
_OUT
TSIZ2
TSIZ1
Note:
Signal names this figure default signals reset, except signals D18, which show secondary signal reset.
Figure 3-1. MSC8101 Flip Chip Plastic Ball Grid Array (FC-PBGA), View
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Package Pinout
Bottom View
IRQ5
BADDR BADDR
PWE6
IRQ3
IRQ1
IRQ4
THERM
BADDR
PWE5
IRQ6
IRQ2
THERM
PSDA PWE7
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
BCTL0
IRQ7
VDDH
VDDH
VDDH
TRST
PA31
PWE4
BADDR BADDR
PB31
PC31
PD31
PB30
PWE3
PGTA
PSDA
VDDH
VDDH
PA30
PC30
PD30
PA29
BCTL1
PWE0
PWE1
VDDH
PWE2
VDDH
PB29
PC29
PD29
PA28
PC27
PC28
PB28
PA27
PA16
PA26
VDDH
PB26
PC26
PB27
VDDH
VDDH
TSIZ3
CLKIN
PD17
PC23
PB25
PA25
PC25
DLL_IN
PB20
PA23
PB24
PA24
PC24
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
PA19
PB18
PA22
SPARE PB22
PC22
VDDH
AACK
PA12
SYN1 SYN1
PC14
PC13
PA17
PA20
PB21
TBST ARTRY SPARE TSIZ0
PA10
PA13
CONF
PD16
PD18
PB19
PA21
PA11
HRESET NMI_
PC12
PC15
PD19
PB23
TSIZ1
TSIZ2
_OUT
PA14
TEST RESET SRESET PA15
PA18
Note:
Signal names this figure default signals reset, except signals D18, which show secondary signal reset.
Figure 3-2. MSC8101 Flip Chip Plastic Ball Grid Array (FC-PBGA), Bottom View
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External Signals
External Signals
UTOPIA TXENB/MII COL/PA31 UTOPIA TXCLAV/TXCLAV0/RTS/MII CRS/PA30 UTOPIA TXSOC/MII TX_ER/PA29 UTOPIA RXENB/MII TX_EN/PA28 UTOPIA RXSOC/MII RX_DV/PA27 UTOPIA RXCLAV/RXCLAV0/MII RX_ER/PA26 UTOPIA TXD0/MSNUM0/PA25 UTOPIA TXD1/MSNUM1/PA24 UTOPIA TXD2/PA23 UTOPIA TXD3/PA22 UTOPIA TXD4/TXD32/PA21 UTOPIA TXD5/TXD22/PA20 UTOPIA TXD6/TXD12/PA19 UTOPIA TXD7/TXD02/TXD1/PA18 UTOPIA RXD7/RXD02/RXD1/PA17 UTOPIA RXD6/RXD12/PA16 UTOPIA RXD5/RXD22/PA15 UTOPIA RXD4/RXD32/PA14 UTOPIA RXD3/MSNUM2/PA13 UTOPIA RXD2/MSNUM3/PA12 UTOPIA RXD1/MSNUM4/PA11 UTOPIA RXD0/MSNUM5/PA10 SMC2 SMTXD/L1TXD0/PA9 SMC2 SMRXD/NBL L1RXD0/L1RXD/PA8 SMC2 SMSYN, L1TSYNC/GRANT/PA7 L1RSYNC/PA6 TX_ER/SCC2 RXD/L1TXD/PB31 SCC2 TXD/MII RX_DV/L1RXD/PB30 TX_EN/L1RSYNC/PB29 FCC2 RTS/MII RX_ER/SCC2 RTS, TENA/L1TSYNC/GRANT/PB28 COL/TDMC2 L1TXD/PB27 CRS/TDMC2 L1RXD/PB26 TXD32/NBL L1TXD3/TDMC2 L1TSYNC/GRANT/PB25 TXD22/NBL L1RXD3 /TDMC2 L1RSYNC/PB24 TXD12/NBL L1RXD2/TDMD2 L1TXD/PB23 TXD02/TXD/NBL L1RXD1/TDMD2 L1RXD/PB22 RXD02 /RXD/NBL L1TXD2/TDMD2 L1TSYNC/GRANT/PB21 RXD12/NBL L1TXD1/TDMD2 L1RSYNC/PB20 RXD22/I2CSDA/PB19 RXD32/I2CSCL/PB18 BRG1O/CLK1/TGATE1/PC31 BRG2O/CLK2/TOUT1/EXT1/PC30 BRG3O/CLK3, TIN2/SCC1 CTS, SCC1 CLSN/PC29 BRG4O, CLK4, TIN1/TOUT2/SCC2 CTS, CLSN/PC28 BRG5O/CLK5/TIMER3,4 TGATE2/PC27 BRG6O/CLK6/TOUT3/TMCLK/PC26 BRG7O/CLK7, TIN4/DACK2/PC25 BRG8O/CLK8, TIN3/TOUT4/DREQ2/PC24 CLK9/DACK1/EXT2/PC23 L1ST1/CLK10/DREQ1/PC22 SMC2 SMTXD/SCC1 CTS, CLSN/MPHY TXADDR0/PC15 L1ST2/SCC1 RENA/MPHY RXADDR0/PC14 L1ST4/SCC2 CTS, CLSN/MPHY TXADDR1/PC13 L1ST3/SCC2 RENA/MPHY RXADDR1/PC12 L1ST1/FCC1 CTS/MPHY TXADDR2, TXCLAV1/PC7 L1ST2/FCC1 CD/MPHY RXADDR2, RXCLAV1/PC6 SMC1 SMTXD/SI2 L1ST3/FCC2 CTS/PC5 SMC1 SMRXD/SI2 L1ST4/FCC2 CD/PC4 SCC1 RXD/DRACK1/DONE1/PD31 SCC1 TXD/DRACK2/DONE2/PD30 SCC1 RTS, TENA/MPHY RXADDR3,MPHY RXCLAV2/PD29 MPHY TXADDR4/MPHY TXCLAV3/BRG1O/SPI SEL/PD19 MPHY RXADDR4/MPHY RXCLAV3/SPICLK/PD18 BRG2O/UTOPIA RXPRTY/SPIMOSI/PD17 UTOPIA TXPRTY/SPIMISO/PD16 SMC1 SMSYN/MPHY TXADDR3/MPHY TXCLAV2/PD7
SMC2 TDMA1
FCC2 SCC2 TDMB2 FCC2 TDMA1 TDMC2 FCC2 TDMA1 TDMD2 FCC2
SCC1 SCC2
SMC2, SCC1, FCC1 SCC1, FCC1 SCC2, FCC1 FCC1 SMC1, FCC2 SCC1 SCC1, FCC1 FCC1, FCC1, SMC1
Notes: HDLC transparent MII, HDLC nibble
CLKOUT DLLIN TEST
A[0-31] TT[0-4] TSIZ[0-3] TBST IRQ1/GBL NC/BADDR[29-31]/IRQ[2-3,5] ABB/IRQ2 AACK ARTRY DBB/IRQ3 D[0-31] D[32-47]/HD[0-15] D[48-51]/HA[0-3] D52/HCS1 D53/HRD/HRW D54/HWR/HDS D55/HTRQ/HREQ D56/HRRQ/HACK D57/HDSP D58/HDDS D59/H8BIT D60/HCS2 D[61-63]/NC NC/DP0/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/EXT_DBG2 IRQ3/DP3/EXT_BR3 IRQ4/DP4/DREQ3/EXT_BG3 IRQ5/DP5/DREQ4/EXT_DBG3 IRQ6/DP6/DACK3 IRQ7/DP7/DACK4 NMI_OUT PSDVAL IRQ7/INT_OUT CS[0-7] BCTL1 BADDR[27-28] BCTL0 PWE[0-7]/PSDDQM[0-7]/PBS[0-7] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 TRST PORESET RSTCONF HRESET SRESET CLKIN MODCK[1-3]/BNKSEL[0-2]/TC[0-2] THERM[1-2] DBRQ/EE0 HPE/EE1 EE[2-3] BTM[0-1]/EE[4-5] SPARE1, SPARE5
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External Signals
Table 3-1. External Signals-SIU Extended Core
Name A[0-31] Data Direction Description
Input/Output Address When MSC8101 external master mode, these pins function address bus. MSC8101 drives address internal masters responds addresses generated external masters. When MSC8101 Internal Master mode, these pins used address lines connected memory devices controlled MSC8101 memory controller. Input/Output Transfer Type master drives these pins during address tenure specify type transaction. Input/Output Transfer Size master drives these pins with value indicating number bytes transferred current transaction. Input/Output Transfer Burst master asserts this indicate that current transaction burst transaction (transfers four quad words). Input Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core.
TT[0-4]
TSIZ[0-3]
TBST
IRQ1
Input/Output Global When master within chip initiates transaction, drives this pin. When external master initiates transaction, should drive this pin. Assertion this indicates that transfer global should snooped caches system. primary (general-purpose) signal connect (NC). Output Burst Addresses 29-31 Outputs memory controller. These pins used external master configuration. They connect directly memory devices controlled MSC8101 memory controller. Interrupt Requests 2-3, External lines that request service routine, internal interrupt controller, from SC140 core.
BADDR[29-31]
IRQ[2-3,5]
Input
Input/Output Request Output output when external arbiter used. MSC8101 asserts this request ownership bus. Input input when internal arbiter used. external master should assert this request ownership from internal arbiter. Input/Output Grant Output output when internal arbiter used. MSC8101 asserts this grant ownership external PowerPC master. Input input when external arbiter used. external arbiter should assert this grant ownership MSC8101.
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External Signals Table 3-1. External Signals-SIU Extended Core (Continued)
Name Data Direction Description
Input/Output Address Busy Output MSC8101 asserts this duration address tenure. Following address acknowledge (AACK) signal, which terminates address tenure, MSC8101 negates fraction cycle then stops driving this pin. MSC8101 does assume PowerPC ownership long senses that Input this asserted external master. Input Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core.
IRQ2
Input/Output Transfer Start Signals beginning address tenure. MSC8101 asserts this signal when internal masters (SC140 core DMA) begins address tenure. When MSC8101 senses this being asserted external master, responds address tenure required (snoop enabled, access internal MSC8101 resources, memory controller support). Input/Output Address Acknowledge slave asserts this signal indicate that identified address tenure. Assertion this signal terminates address tenure. Input Address Retry Assertion this signal indicates that transaction should retried master. MSC8101 asserts this signal enforce data coherency with internal cache prevent deadlock situations.
AACK
ARTRY
Input/Output Data Grant output when internal arbiter used. MSC8101 asserts this output Output grant data ownership external PowerPC master. Input input when external arbiter used. external arbiter should assert this input grant data ownership MSC8101. Input/Output Data Busy Output MSC8101 asserts this output duration data tenure. Following which terminates data tenure, MSC8101 negates fraction cycle then stops driving this pin. Input MSC8101 does assume PowerPC data ownership long senses asserted external master. Input Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core.
IRQ3
D[0-31]
Input/Output Data Most Significant Word write transactions master drives valid data this bus. read transactions slave drives valid data this bus. Host Port Disabled mode, these bits part 64-bit PowerPC data bus. Host Port Enabled mode, these bits used PowerPC 32-bit mode. Input/Output Data Bits 32-47 write transactions master drives valid data this bus. read transactions slave drives valid data this bus. Input/Output Host Data When HDI16 interface enabled, these signals lines 0-15 bidirectional tri-state data bus.
D[32-47]
HD[0-15]
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External Signals Table 3-1. External Signals-SIU Extended Core (Continued)
Name D[48-51] Data Direction Description
Input/Output Data Bits 48-51 write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Input Host Address Lines When HDI16 interface enabled, this address line addresses internal host registers.
HA[0-3]
Input/Output Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Input Host Chip Select When HDI16 interface enabled, this chip-select pin. polarity this programmable.
HCS1
Input/Output Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Input Host Read Strobe When HDI16 programmed interface with double data strobe host bus, this read data strobe input (HRD). polarity data strobe programmable. Host Read Write Select When HDI16 interface enabled Single Strobe mode, this read/write input (HRW).
Input
Input/Output Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Input Host Write Data Strobe When HDI16 programmed interface with double data strobe host bus, this write data strobe input (HWR). polarity data strobe programmable. Host Data Strobe When HDI16 programmed interface with single data strobe host bus, this data strobe input (HDS). polarity data strobe programmable.
Input
Input/Output Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Output Transmit Host Request When HDI16 programmed interface with double host request host bus, this transmit host request output (HTRQ). polarity host request programmable. host request open-drain output. Host Request When HDI16 programmed interface with single host request host bus, this host request output (HREQ). polarity host request programmable. host request programmed driven open-drain output.
HTRQ
HREQ
Output
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External Signals Table 3-1. External Signals-SIU Extended Core (Continued)
Name Data Direction Description
Input/Output Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Output Receive Host Request When HDI16 programmed interface with double host request host bus, this receive host request output (HRRQ). polarity host request programmable. host request open-drain output. Host Acknowledge When HDI16 programmed interface with single host request host bus, this host acknowledge input (HACK). polarity host acknowledge programmable.
HRRQ
HACK
Input
Input/Output Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Input Host Data Strobe Polarity When HDI16 interface enabled, this host data strobe polarity (HDSP).
HDSP
Input/Output Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Input Host Dual Data Strobe When HDI16 interface enabled, this host dual data strobe (HDDS).
HDDS
Input/Output Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Input H8BIT When HDI16 interface enabled, this determines interface 8-bit 16-bit mode.
H8BIT
Input/Output Data write transactions master drives valid data this pin. read transactions slave drives valid data this pin. Input Host Chip Select When HDI16 interface enabled, this chip-select pin. polarity this programmable.
HCS2
D[61-63]
Input/Output Data Bits 61-63 Used only PowerPC-only mode. write transactions master drives valid data this bus. read transactions slave drives valid data this bus. dedicated signal connect (NC). primary (general-purpose) signal connect (NC). Input/Output Data Parity agent that drives data also drives data parity signals. value driven data parity zero should give parity (odd number ones) group signals that includes data parity D[0-7]. Input External PowerPC Request external master asserts this request PowerPC ownership from internal arbiter.
EXT_BR2
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External Signals Table 3-1. External Signals-SIU Extended Core (Continued)
Name IRQ1 Data Direction Input Description Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core.
Input/Output Data Parity agent that drives data also drives data parity signals. value driven data parity should give parity (odd number ones) group signals that includes data parity D[8-15]. Output External Grant MSC8101 asserts this grant PowerPC ownership external PowerPC master. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core.
EXT_BG2
IRQ2
Input
Input/Output Data Parity agent that drives data also drives data parity signals. value driven data parity should give parity (odd number ones) group signals that includes data parity D[16-23]. Output External Data Grant MSC8101 asserts this grant PowerPC data ownership external PowerPC master. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core.
EXT_DBG2
IRQ3
Input
Input/Output Data Parity agent that drives data also drives data parity signals. value driven data parity three should give parity (odd number ones) group signals that includes data parity D[24-31]. Input External PowerPC Request external master asserts this request PowerPC ownership from internal arbiter. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core.
EXT_BR3
IRQ4
Input
Input/Output Data Parity agent that drives data also drives data parity signals. value driven data parity four should give parity (odd number ones) group signals that includes data parity D[32-39]. Input Output Request external peripheral uses this request service. External PowerPC Grant MSC8101 asserts this grant PowerPC ownership external PowerPC master.
DREQ3 EXT_BG3
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External Signals Table 3-1. External Signals-SIU Extended Core (Continued)
Name IRQ5 Data Direction Input Description Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core.
Input/Output Data Parity agent that drives data also drives data parity signals. value driven data parity five should give parity (odd number ones) group signals that includes data parity D[40-47]. Input Output Request external peripheral uses this request service. External Data Grant MSC8101 asserts this grant PowerPC data ownership external PowerPC master. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core.
DREQ4 EXT_DBG3
IRQ6
Input
Input/Output Data Parity agent that drives data also drives data parity signals. value driven data parity should give parity (odd number ones) group signals that includes data parity D[48-55]. Output Acknowledge drives this output acknowledge transaction PowerPC bus. Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core.
DACK3
IRQ7
Input
Input/Output Data Parity master slave that drives data also drives data parity signals. value driven data parity seven should give parity (odd number ones) group signals that includes data parity D[56-63]. Output Acknowledge drives this output acknowledge transaction PowerPC bus.
DACK4
Input/Output Transfer Acknowledge Indicates that data beat valid data bus. single beat transfers, assertion indicates termination transfer. burst transfers, asserted four times indicate transfer four data beats with last assertion indicating termination burst transfer. Input/Output Transfer Error Acknowledge Indicates error. masters within MSC8101 monitor state this pin. MSC8101 internal PowerPC monitor assert this identifies PowerPC transfer that hung. Input Output Non-Maskable Interrupt When external device asserts this line, MSC8101 input asserted. Non-Maskable Interrupt Driven from MSC8101 internal interrupt controller. Assertion this output indicates that non-maskable interrupt, pending MSC8101 internal interrupt controller, waiting handled external host.
NMI_OUT
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External Signals Table 3-1. External Signals-SIU Extended Core (Continued)
Name PSDVAL Data Direction Description
Input/Output Data Valid Indicates that data beat valid data bus. difference between PSDVAL that asserted indicate data transfer terminations while PSDVAL signal asserted with each data beat movement. Thus, when asserted, PSDVAL asserted, when PSDVAL asserted, necessarily asserted. example when SDMA initiates double word (2x64 bits) transfer memory device that 32-bit port size, PSDVAL asserted three times without finally both pins asserted terminate transfer. Input Interrupt Request eight external lines that request service routine, internal interrupt controller, from SC140 core. Interrupt Output Driven from MSC8101 internal interrupt controller. Assertion this output indicates that unmasked interrupt pending MSC8101 internal interrupt controller. Chip Select Enable specific memory devices peripherals connected MSC8101 buses. Buffer Control Controls buffers PowerPC data bus. Usually used with BCTL0. exact function this defined value SIUMCR[BCTLC]. Table 6-8, Registers, page -68, SIUMCR[BCTLC] values. Burst Address 27-28 five outputs memory controller. These pins used external master configuration. They connect directly memory devices controlled MSC8101 memory controller. Address Latch Enable Controls external address latch used external master configuration. Buffer Control Controls buffers PowerPC data bus. exact function this defined value SIUMCR[BCTLC]. Table 6-8, Registers, page -68, SIUMCR[BCTLC] values. Write Enable Outputs PowerPC general-purpose chip-select machine (GPCM). These pins select byte lanes write operations. SDRAM Outputs SDRAM control machine. These pins select specific byte lanes SDRAM devices. Byte Select Outputs user-programmable memory (UPM) memory controller. These pins select specific byte lanes during memory operations. timing these pins programmed UPM. actual driven value depends address size transaction port size accessed device. SDRAM Output from SDRAM controller. This part address when address driven. part command when column address driven. General-Purpose Line general-purpose output lines UPM. values timing this programmed UPM.
IRQ7
INT_OUT
Output
CS[0-7] BCTL1
Output Output
BADDR[27-28]
Output
BCTL0
Output Output
PWE[0-7]
Output
PSDDQM[0-7]
Output
PBS[0-7]
Output
PSDA10
Output
PGPL0
Output
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External Signals Table 3-1. External Signals-SIU Extended Core (Continued)
Name PSDWE Data Direction Output Description SDRAM Write Enable Output from SDRAM controller. This should connect SDRAM input signal. General-Purpose Line general-purpose output lines from UPM. values timing this programmed UPM. Output Enable Output GPCM. Controls output buffer memory devices during read operations. SDRAM Output from SDRAM controller. This should connect SDRAM input signal. General-Purpose Line general-purpose output lines from UPM. values timing this programmed UPM. SDRAM Output from SDRAM controller. This should connect SDRAM input signal. General-Purpose Line general-purpose output lines from UPM. values timing this programmed UPM. GPCM Terminates transactions during GPCM operation. Requires external pull resistor proper operation. Wait Input UPM. external device hold this high force wait until device ready operation continue. General-Purpose Line general-purpose output lines from UPM. values timing this programmed UPM. Parity Byte Select systems which data parity stored separate chip, this output byte-select that chip. SDRAM Address Multiplexer Controls SDRAM address multiplexer when MSC8101 External Master mode. General-Purpose Line general-purpose output lines from UPM. values timing this programmed UPM. Test Mode Select (JTAG) Controls state MSC8101 JTAG/COP controller. Test Data (JTAG) Data input MSC8101 JTAG/COP controller. Test Clock (JTAG) Provides clock input MSC8101 JTAG/COP controller. Test Reset (JTAG) reset input MSC8101 JTAG/COP controller.
PGPL1
Output
Output
PSDRAS
Output
PGPL2
Output
PSDCAS
Output
PGPL3
Output
PGTA
Input
PUPMWAIT
Input
PGPL4
Output
PPBS
Output
PSDAMUX
Output
PGPL5
Output
TRST
Input Input Input Input
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External Signals Table 3-1. External Signals-SIU Extended Core (Continued)
Name PORESET RSTCONF Data Direction Output Input Input Description Test Data (JTAG) Data output from MSC8101 JTAG/COP controller. Power-On Reset When asserted, this input line causes MSC8101 enter power-on reset state. Reset Configuration Used during reset configuration sequence chip. detailed explanation function, Section 5.1.1, Power-On Reset Flow, Section 5.2, Hardware Reset Configuration, MSC8101 Reference Manual.
HRESET
Input/Output Hard Reset When asserted, this open-drain line causes MSC8101 enter hard reset state. Input/Output Soft Reset When asserted, this open-drain line causes MSC8101 enter soft reset state. Input Input Output Clock Primary clock input MSC8101 PLL. Clock Modes Define operating mode internal clock circuits. Bank Select Select SDRAM bank when MSC8101 60x-compatible mode. BNKSELx three BNKSEL signals. Transfer Code Supply information debug purposes each transactions initiated MSC8101. Leave disconnected. Debug Request Determines whether immediately into SC140 Debug mode when PORESET deasserted. Enhanced OnCE (EOnCE) Event After PORESET deasserted, configure input (default) output. Emulation Debug chapter SC140 Core Reference Manual details configure this pin. Input Output Debug request, enable Address Event Detection Channel generate EOnCE events. Detection Address Event Detection Channel Used trigger external debugging equipment. Host Port Enable When this asserted during PORESET, Host port enabled, PowerPC data bits wide, Host must program reset configuration word. EOnCE Event After PORESET deasserted, configure input (default) output. Emulation Debug chapter SC140 Core Reference Manual details configure this pin. Input Output Enable Address Event Detection Channel generate EOnCE events. Debug Acknowledge detection Address Event Detection Channel Used trigger external debugging equipment.
SRESET CLKIN MODCK[1-3] BNKSEL[0-2]
TC[0-2]
Output
THERM[1-2] DBREQ
Input
Input
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External Signals Table 3-1. External Signals-SIU Extended Core (Continued)
Name Data Direction Description EOnCE Event After PORESET deasserted, configure input (default) output. Emulation Debug chapter SC140 Core Reference Manual details configure this pin. Input Output Enable Address Event Detection Channel generate EOnCE events enable Event Counter. Detection Address Event Detection Channel Used trigger external debugging equipment. EOnCE Event After PORESET deasserted, configure input (default) output. Emulation Debug chapter SC140 Core Reference Manual details configure this pin, well information ERCV Register. Input Output BTM[0-1] Input Enable Address Event Detection Channel generate EOnCE events. EOnCE Receive Register (ERCV) read DSP. Used trigger external debugging equipment. Boot Mode Determines MSC8101 boot mode when PORESET deasserted. Emulation Debug chapter SC140 Core Reference Manual details these pins. EOnCE Event After PORESET deasserted, configure input (default) output. Emulation Debug chapter SC140 Core Reference Manual details configure this pin, well information ETRSMT Register. Input Output Enable Address Event Detection Channel generate EOnCE events EOnCE Transmit Register (ETRSMT) written DSP. Used trigger external debugging equipment. EOnCE Event After PORESET deasserted, configure input (default) output. Emulation Debug chapter SC140 Core Reference Manual details configure this pin. Input Output Enable Address Event Detection Channel Detection Address Event Detection Channel Used trigger external debugging equipment. Enhanced OnCE (EOnCE) Event Detection After PORESET deasserted, configure input (default) output: Emulation Debug chapter SC140 Core Reference Manual details configure this pin. Input Output SPARE1, CLKOUT DLL_IN TEST Output Input Input Enable Data Event Detection Channel. Detection Data Event Detection Channel. Used trigger external debugging equipment. Spare Pins Leave disconnected backward compatibility with future revisions this device. CLKOUT clock. DLL_IN synchronization with external device. TEST test purposes. must connect GND.
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External Signals Table 3-1. External Signals-SIU Extended Core (Continued)
Name Power Supply Data Direction Description power supply internal logic. VDDH power supply Buffers. VCCSYN power supply circuitry. GNDSYN special ground circuitry. GNDSYN1 special ground SC140 core circuitry.
VCCSYN1 power supply SC140 core circuitry.
Table 3-2. External Signals-CPM
Name GeneralPurpose PA31 Peripheral Controller: Dedicated FCC1:UTOPIA masterTxEnb FCC1:UTOPIA slave TxEnb FCC1:MII PA30 FCC1:UTOPIA slave TxClav FCC1:UTOPIA master TxClav/UTOPIA master TxClav0 MPHY, direct polling FCC1:RTS FCC1:MII PA29 FCC1:UTOPIA TxSOC FCC1:MII TX_ER PA28 FCC1:UTOPIA master RxEnb FCC1:UTOPIA slave RxEnb FCC1:MII TX_EN PA27 FCC1:UTOPIA RxSOC FCC1:MII RX_DV Data Direction Description
Output Input Input Output Input Input
FCC1: UTOPIA Master Transmit Enable FCC1: UTOPIA Slave Transmit Enable FCC1: Media Independent Interface Collision Detect FCC1: UTOPIA Slave Transmit Cell Available FCC1: UTOPIA Master Transmit Cell Available FCC1: UTOPIA Master Transmit Cell Available Multiple Direct Polling FCC1: Request Send FCC1: Media Independent Interface Carrier Sense FCC1: UTOPIA Transmit Start Cell FCC1: Media Independent Interface Transmit Error FCC1: UTOPIA Master Receive Enable FCC1: UTOPIA Slave Receive Enable FCC1: Media Independent Interface Transmit Enable FCC1: UTOPIA Receive Start Cell FCC1: Media Independent Interface Receive Data Valid
Output Input Output Output Output Input Output Input Input
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External Signals Table 3-2. External Signals-CPM (Continued)
Name GeneralPurpose PA26 Peripheral Controller: Dedicated FCC1:UTOPIA slave RxClav FCC1:UTOPIA master RxClav FCC1:UTOPIA master RxClav0 MPHY, direct polling Data Direction Description
Output Input
FCC1: UTOPIA Slave Receive Cell Available FCC1: UTOPIA Master Receive Cell Available
Input
FCC1: UTOPIA Master Receive Cell Available Direct Polling
FCC1:MII RX_ER PA25 FCC1:UTOPIA TxD0 MSNUM0 PA24 FCC1:UTOPIA TxD1 MSNUM1 PA23 PA22 PA21 FCC1:UTOPIA TxD2 FCC1:UTOPIA TxD3 FCC1:UTOPIA TxD4 FCC1:MII, HDLC nibble TxD3 PA20 FCC1:UTOPIA TxD5 FCC1:MII, HDLC nibble TxD2 PA19 FCC1:UTOPIA TxD6 FCC1:MII, HDLC nibble TxD1 PA18 FCC1:UTOPIA TxD7 FCC1:MII, HDLC nibble TxD0 FCC1:HDLC transparent PA17 FCC1:UTOPIA RxD7 FCC1:MII, HDLC nibble RxD0
Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input
FCC1: Media Independent Interface Receive Error FCC1: UTOPIA Transmit Data Module Serial Number FCC1: UTOPIA Transmit Data Module Serial Number FCC1: UTOPIA Transmit Data FCC1: UTOPIA Transmit Data FCC1: UTOPIA Transmit Data FCC1: Media Independent Interface, HDLC Nibble Transmit Data FCC1: UTOPIA Transmit Data FCC1: Media Independent Interface, HDLC Nibble Transmit Data FCC1: UTOPIA Transmit Data FCC1: Media Independent Interface, HDLC Nibble Transmit Data FCC1: UTOPIA Transmit Data FCC1: Media Independent Interface, HDLC Nibble Transmit Data FCC1: HDLC, Transparent Serial Transmit Data FCC1: UTOPIA Receive Data FCC1: Media Independent Interface, HDLC Nibble Receive Data FCC1: HDLC Transparent Serial Receive Data FCC1: UTOPIA Receive Data FCC1: Media Independent Interface, HDLC Nibble Receive Data
FCC1:HDLC transparent PA16 FCC1:UTOPIA RxD6 FCC1:MII, HDLC nibble RxD1
Input Input Input
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External Signals Table 3-2. External Signals-CPM (Continued)
Name GeneralPurpose PA15 Peripheral Controller: Dedicated FCC1:UTOPIA RxD5 FCC1:MII, HDLC nibble RxD2 PA14 FCC1:UTOPIA RxD4 FCC1:MII, HDLC nibble RxD3 Data Direction Description
Input Input Input Input Input Output Input Output Input Output Input Output Output Inout Input Input Inout Input Input Input Output Input Inout Output Input Inout
FCC1: UTOPIA Receive Data FCC1: Media Independent Interface, HDLC Nibble Receive Data FCC1: UTOPIA Receive Data FCC1: Media Independent Interface, HDLC Nibble Receive Data FCC1: UTOPIA Receive Data Module Serial Number FCC1: UTOPIA Receive Data Module Serial Number FCC1: UTOPIA Receive Data Module Serial Number FCC1: UTOPIA Receive Data Module Serial Number SMC2: Serial Management Transmit Data Time-Division Multiplexing Layer Transmit Data SMC2: Serial Management Receive Data Time-Division Multiplexing Layer Nibble Receive Data Time-Division Multiplexing Layer Serial Receive Data SMC2: Serial Management Synchronization Time-Division Multiplexing Layer Transmit Synchronization/Grant Time-Division Multiplexing Layer Receive Synchronization FCC2: Media Independent Interface Transmit Error SCC2: Receive Data Time-Division Multiplexing Layer Transmit Data SCC2: Transmit Data FCC2: Media Independent Interface Receive Data Valid Time-Division Multiplexing Layer Receive Data
PA13
FCC1:UTOPIA RxD3 MSNUM2
PA12
FCC1:UTOPIA RxD2 MSNUM3
PA11
FCC1:UTOPIA RxD1 MSNUM4
PA10
FCC1:UTOPIA RxD0 MSNUM5
SMC2:SMTXD TDM_A1:L1TXD0
SMC2:SMRXD TDM_A1:nibble L1RXD0 TDM_A1:serial L1RXD
SMC2:SMSYN TDM_A1:L1TSYNC/GRANT
PB31
TDM_A1:L1RSYNC FCC2:MII TX_ER SCC2:RxD TDM_B2:L1TXD
PB30
SCC2:TxD FCC2:MII RX_DV TDM_B2:L1RXD
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External Signals Table 3-2. External Signals-CPM (Continued)
Name GeneralPurpose PB29 Peripheral Controller: Dedicated FCC2:MII TX_EN TDM_B2:L1RSYNC PB28 FCC2:RTS FCC2:MII RX_ER Data Direction Description
Output Input Output Input Output Input Input Inout Input Inout Output
FCC2: Media Independent Interface Transmit Enable Time-Division Multiplexing Layer Receive Synchronization FCC2: Request Send FCC2: Media Independent Interface Receive Error SCC2: Request Send, Transmit Enable Time-Division Multiplexing Layer Transmit Synchronization/Grant FCC2: Media Independent Interface Collision Detect Time-Division Multiplexing Layer Transmit Data FCC2: Media Independent Interface Carrier Sense Input Time-Division Multiplexing Layer Receive Data FCC2: Media Independent Interface, HDLC Nibble Transmit Data Time-Division Multiplexing A1:Nibble Layer Transmit Data Time-Division Multiplexing Layer Transmit Synchronization/Grant FCC2: Media Independent Interface, HDLC Nibble Transmit Data Time-Division Multiplexing A1:Nibble Layer Receive Data Time-Division Multiplexing Layer Receive Synchronization FCC2: Media Independent Interface, HDLC Nibble Transmit Data Time-Division Multiplexing A1:Nibble Layer Receive Data Time-Division Multiplexing Layer Transmit Data FCC2: Media Independent Interface, HDLC Nibble Transmit Data FCC2: HDLC Transparent Serial Transmit Data Time-Division Multiplexing A1:Nibble Layer Receive Data Time-Division Multiplexing Layer Receive Data
SCC2:RTS, TENA TDM_B2:L1TSYNC/GRANT PB27 FCC2:MII TDM_C2:L1TXD PB26 FCC2:MII TDM_C2:L1RXD PB25 FCC2:MII, HDLC nibble TxD3
TDM_A1:nibble L1TXD3 TDM_C2:L1TSYNC/GRANT PB24 FCC2:MII, HDLC nibble TxD2
Output Input Output
TDM_A1:nibble L1RXD3 TDM_C2:L1RSYNC PB23 FCC2:MII, HDLC nibble TxD1
Input Input Output
TDM_A1:nibble L1RXD2 TDM_D2:L1TXD PB22 FCC2:MII, HDLC nibble TxD0
Input Inout Output
HDLC transparent TDM_A1:nibble L1RXD1 TDM_D2:L1RXD
Output Input Inout
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External Signals Table 3-2. External Signals-CPM (Continued)
Name GeneralPurpose PB21 Peripheral Controller: Dedicated FCC2:MII, HDLC nibble RxD0 Data Direction Description
Input
FCC2: Media Independent Interface, HDLC Nibble Receive Data FCC2: HDLC Transparent Serial Receive Data
FCC2:HDLC transparent TDM_A1:nibble L1TXD2
Input
Output TDM_D2:L1TSYNC/GRANT
Time-Division Multiplexing A1:Nibble Layer Transmit Data Time-Division Multiplexing Layer Transmit Synchronization/Grant FCC2: Media Independent Interface, HDLC Nibble Receive Data Time-Division Multiplexing A1:Nibble Layer Transmit Data Time-Division Multiplexing Layer Receive Synchronization FCC2: Media Independent Interface, HDLC Nibble Receive Data I2C: Inter-Integrated Circuit Serial Data FCC2: Media Independent Interface, HDLC Nibble Receive Data I2C: Inter-Integrated Circuit Serial Clock Baud-Rate Generator Output Clock Timer 1/2: Timer Gate Baud-Rate Generator Output Clock Timer Timer Output External Request Line Baud-Rate Generator Output Clock Timer Input SCC1: Clear Send, Collision
Input PB20 FCC2:MII, HDLC nibble RxD1 Input
TDM_A1:nibble L1TXD1 TDM_D2:L1RSYNC PB19 FCC2:MII, HDLC nibble RxD2
Output Input Input
I2C:SDA PB18 FCC2:MII, HDLC nibble RxD3
Inout Input
I2C:SCL PC31 BRG1O CLK1 Timer1/2: TGATE1 PC30 BRG2O CLK2 Timer1:TOUT1 EXT1 PC29 BRG3O CLK3/TIN2
Inout Output Input Input Output Input Output Input Output Input Input
SCC1:CTS, CLSN
Input
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External Signals Table 3-2. External Signals-CPM (Continued)
Name GeneralPurpose PC28 Peripheral Controller: Dedicated BRG4O CLK4/TIN1 Data Direction Description
Output Input Input
Baud-Rate Generator Output Clock Timer Input Timer Timer Output SCC2: Clear Send, Collision Baud-Rate Generator Output Clock Timer 3/4: Timer Gate Baud-Rate Generator Output Clock Timer Timer Output Timer Clock Baud-Rate Generator Output Clock Timer Input DMA: Data Acknowledge Baud-Rate Generator Output Clock Timer Input Timer Timer Output DMA: Data Request Clock DMA: Data Acknowledge External Request Line Serial Interface Layer Strobe Clock DMA: Request
Timer2:TOUT2
Output Input Output Input Input Output Input Output Input Output Input Input
SCC2:CTS, CLSN PC27 BRG5O CLK5 Timer3/4:TGATE2 PC26 BRG6O CLK6 Timer3:TOUT3 TMCLK PC25 BRG7O CLK7/TIN4
DMA:DACK2 PC24 BRG8O CLK8/TIN3
Output Output Input Input
Timer4:TOUT4 DMA:DREQ2 PC23 CLK9 DMA:DACK1 EXT2 PC22 SI1:L1ST1 CLK10 DMA:DREQ1
Output Input Input Output Input Output Input Inout
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External Signals Table 3-2. External Signals-CPM (Continued)
Name GeneralPurpose PC15 Peripheral Controller: Dedicated SMC2:SMTXD SCC1:CTS, CLSN FCC1:MPHY master TxAddr0 FCC1:MPHY slave TxAddr0 Data Direction Description
Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output
SMC2: Serial Management Transmit Data SCC1: Clear Send, Collision FCC1: Multiple Master Transmit Address FCC1: Multiple Slave Transmit Address Serial Interface Layer Strobe SCC1: Carrier Detect, Receive Enable FCC1: Multiple Master Receive Address FCC1: Multiple Slave Receive Address Serial Interface Layer Strobe SCC2: Clear Send, Collision FCC1: Multiple Master Transmit Address FCC1: Multiple Slave Transmit Address Serial Interface Layer Strobe SCC2: Carrier Detect, Request Enable FCC1: Multiple Master Receive Address FCC1: Multiple Slave Receive Address Serial Interface Layer Strobe FCC1: Clear Send FCC1: Multiple Master Transmit Address Multiplexed Polling FCC1: Multiple Slave Transmit Address Multiplexed Polling FCC1: Multiple Master Transmit Cell Available Direct Polling
PC14
SI1:L1ST2 SCC1:CD, RENA FCC1:MPHY master RxAddr0 FCC1:MPHY slave RxAddr0
PC13
SI1:L1ST4 SCC2:CTS, CLSN FCC1:MPHY master TxAddr1 FCC1:MPHY slave TxAddr1
PC12
SI1:L1ST3 SCC2:CD, RENA FCC1:MPHY master RxAddr1 FCC1:MPHY slave RxAddr1
SI2:L1ST1 FCC1:CTS FCC1:MPHY master TxAddr2 multiplexed polling FCC1:MPHY slave TxAddr2 multiplexed polling FCC1:MPHY master TxClav1 direct polling
Input
Input
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External Signals Table 3-2. External Signals-CPM (Continued)
Name GeneralPurpose Peripheral Controller: Dedicated SI2:L1ST2 FCC1:CD FCC1:MPHY master RxAddr2 multiplexed polling FCC1:MPHY slave RxAddr2 multiplexed polling FCC1:MPHY master RxClav1 direct polling SMC1:SMTXD SI2:L1ST3 FCC2:CTS SMC1:SMRXD SI2:L1ST4 FCC2:CD PD31 SCC1:RxD DMA:DRACK1 DMA:DONE1 PD30 SCC1:TxD DMA:DRACK2 DMA:DONE2 PD29 SCC1:RTS, TENA FCC1:MPHY master RxAddr3 multiplexed polling FCC1:MPHY slave RxAddr3 multiplexed polling FCC1:MPHY master RxClav2 direct polling Data Direction Description
Output Input Output
Serial Interface Layer Strobe FCC1: Carrier Detect FCC1: Multiple Master Receive Address Multiplexed Polling FCC1: Multiple Slave Receive Address Multiplexed Polling FCC1: Multiple Master Receive Cell Available Direct Polling SMC1: Serial Management Transmit Data Serial Interface Layer Strobe FCC2: Clear Send SMC1: Serial Management Receive Data Serial Interface Layer Strobe FCC2: Carrier Detect SCC1: Receive Data DMA: Data Request Acknowledge DMA: Done SCC1: Transmit Data DMA: Data Request Acknowledge DMA: Done SCC1: Request Send, Transmit Enable FCC1: Multiple Master Receive Address Multiplexed Polling FCC1: Multiple Slave Receive Address Multiplexed Polling FCC1: Multiple Master Receive Cell Available Direct Polling
Input
Input Output Output Input Input Output Input Input Output Inout Output Output Inout Output Output
Input
Input
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External Signals Table 3-2. External Signals-CPM (Continued)
Name GeneralPurpose PD19 Peripheral Controller: Dedicated FCC1:MPHY master TxAddr4 multiplexed polling FCC1:MPHY slave TxAddr4 multiplexed polling FCC1:MPHY master TxClav3 direct polling Data Direction Description
Output
FCC1: Multiple Master Transmit Address Multiplexed Polling FCC1: Multiple Slave Transmit Address Multiplexed Polling FCC1: Multiple Master Transmit Cell Available Direct Polling Baud Rate Generator Output SPI: Select FCC1: Multiple Master Receive Address Multiplexed Polling FCC1: Multiple Slave Receive Address Multiplexed Polling FCC1: Multiple Master Receive Cell Available Direct Polling SPI: Clock Baud Rate Generator Output FCC1: UTOPIA Receive Parity SPI: Master Output Slave Input FCC1: UTOPIA Transmit Parity SPI: Master Input Slave Output SMC1: Serial Management Synchronization FCC1: Multiple Master Transmit Address Multiplexed Polling FCC1: Multiple Slave Transmit Address Multiplexed Polling FCC1: Multiple Master Transmit Cell Available Direct Polling
Input
Input
BRG1O SPI:SEL PD18 FCC1:MPHY master RxAddr4 multiplexed polling FCC1:MPHY slave RxAddr4 multiplexed polling FCC1:MPHY master RxClav3 direct polling SPI:CLK PD17 BRG2O FCC1:UTOPIA RxPrty SPI:MOSI PD16 FCC1:UTOPIA TxPrty SPI:MISO SMC1:SMSYN FCC1:MPHY master TxAddr3 multiplexed polling FCC1:MPHY slave TxAddr3 multiplexed polling FCC1:MPHY master TxClav2 direct polling
Output Input Output
Input
Input
Inout Output Input Inout Output Inout Input Output
Input
Input
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Dedicated Assignments Port
Dedicated Assignments Port
Table 3-3. Port A-Dedicated Assignment (PPARA
Function PSORA[x] PSORA[x] Default Input FCC1: PDIRA[x] (Output) PDIRA[x] (Input Unless Inout Specified) FCC1: FCC1: Default Input
PDIRA[x] (Output) PDIRA[x] (Input) FCC1: TxEnb UTOPIA slave FCC1: TxClav UTOPIA master FCC1: TxClav0 MPHY, master, direct polling
PA31
FCC1: TxEnb UTOPIA master FCC1: TxClav UTOPIA slave
PA30
PA29 PA28 PA27 PA26
FCC1: TxSOC UTOPIA FCC1: RxEnb UTOPIA master FCC1: RxEnb UTOPIA slave FCC1: RxSOC UTOPIA FCC1: RxClav UTOPIA slave FCC1: RxClav UTOPIA master FCC1: RxClav0 MPHY, master, direct polling
FCC1: TX_ER FCC1: TX_EN FCC1: RX_DV FCC1: RX_ER
PA25 PA24 PA23 PA22 PA21
FCC1: TxD0 UTOPIA FCC1: TxD1 UTOPIA FCC1: TxD2 UTOPIA FCC1: TxD3 UTOPIA FCC1: TxD4 UTOPIA FCC1: TxD3 MII/HDLC nibble FCC1: TxD5 UTOPIA FCC1: TxD2 MII/HDLC nibble
MSNUM01 MSNUM11
PA20
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Dedicated Assignments Port Table 3-3. Port A-Dedicated Assignment (PPARA (Continued)
Function PSORA[x] PDIRA[x] (Output) PDIRA[x] (Input) Default Input PDIRA[x] (Output) PDIRA[x] (Input Unless Inout Specified) Default Input PSORA[x]
PA19
FCC1: TxD6 UTOPIA FCC1: TxD1 MII/HDLC nibble FCC1: TxD7 UTOPIA FCC1: TxD0 MII/HDLC nibble FCC1: HDLC transparent FCC1: RxD7 UTOPIA FCC1: RxD0 MII/HDLC nibble FCC1: HDLC transparent FCC1: RxD6 UTOPIA FCC1: RxD1 MII/HDLC nibble FCC1: RxD5 UTOPIA FCC1: RxD2 MII/HDLC nibble FCC1: RxD4 UTOPIA FCC1: RxD3 MII/HDLC nibble FCC1: RxD3 UTOPIA FCC1: RxD2 UTOPIA FCC1: RxD1 UTOPIA FCC1: RxD0 UTOPIA SMC2: SMTXD
PA18
PA17
PA16
PA15
PA14
PA13 PA12 PA11 PA10
MSNUM21 MSNUM31 MSNUM41 MSNUM51 TDM_A1: L1TXD0 Inout, nibble
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Dedicated Assignments Port Table 3-3. Port A-Dedicated Assignment (PPARA (Continued)
Function PSORA[x] PDIRA[x] (Output) PDIRA[x] (Input) SMC2: SMRXD Default Input PDIRA[x] (Output) PDIRA[x] (Input Unless Inout Specified) TDM_A1: L1RXD0 Inout, nibble TDM_A1: L1RXD Inout, serial TDM_A1: L1TSYNC/GRANT TDM_A1: L1RSYNC Default Input PSORA[x]
SMC2: SMSYN
Notes:
MSNUM[0-4] sub-block code peripheral controller using SDMA; MSNUM[5] indicates which section, transmit receive, active during transfer. SDMA Programming Model information MSC8101 Reference Manual. port signal number.
Table 3-4. Port Dedicated Assignment (PPARB
Function PSORB[x] PDIRB[x] (Output) PB31 PB30 PB29 PB28 FCC2: FCC2: RX_ER FCC2: FCC2: FCC2: TxD3 MII/HDLC nibble FCC2: TxD2 MII/HDLC nibble TDM_A1: L1RXD3 nibble FCC2: TX_ER SCC2: PDIRB[x] (Input) SCC2: FCC2: RX_DV Default Input FCC2: TX_EN SCC2: SCC2: TENA Ethernet PDIRB[x] (Output) PDIRB[x] (Input Unless Inout Specified) TDM_B2: L1TXD Inout TDM_B2: L1RXD Inout TDM_B2: L1RSYNC TDM_B2: L1TSYNC/GRANT TDM_C2: L1TXD Inout TDM_C2: L1RXD Inout TDM_A1: L1TXD3 nibble TDM_C2: L1TSYNC/GRANT TDM_C2: L1RSYNC Default Input PSORB[x]
PB27 PB26 PB25 PB24
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Dedicated Assignments Port Table 3-4. Port Dedicated Assignment (PPARB (Continued)
Function PSORB[x] PDIRB[x] (Output) PB23 PB22 FCC2: TxD1 MII/HDLC nibble FCC2: TxD0 MII/HDLC nibble FCC2: HDLC transparent PDIRB[x] (Input) TDM_A1: L1RXD2 nibble TDM_A1: L1RXD1 nibble Default Input PDIRB[x] (Output) PDIRB[x] (Input Unless Inout Specified) TDM_D2: L1TXD Inout TDM_D2: L1RXD Inout Default Input PSORB[x]
PB21
FCC2: RxD0 MII/HDLC nibble FCC2: HDLC transparent FCC2: RxD1 MII/HDLC nibble FCC2: RxD2 MII/HDLC nibble FCC2: RxD3 MII/HDLC nibble port signal number.
TDM_A1: L1TXD2 nibble
TDM_D2: L1TSYNC/GRANT
PB20 PB19 PB18 Notes:
TDM_A1: L1TXD1 nibble
TDM_D2: L1RSYNC I2C: Inout I2C: Inout
Table 3-5. Port Dedicated Assignment (PPARC
Function PSORC[x] PDIRC[x] (Output) PC31 PC30 PC29 BRG1: BRGO BRG2: BRGO BRG3: BRGO PDIRC[x] (Input) CLK1 CLK2 CLK3/TIN2 Default Input CLK5 CLK6 CLK7 Timer1: TOUT PDIRC[x] (Output) PDIRC[x] (Input Unless Inout Specified) Timer1/2: TGATE1 EXT1 SCC1: CTS1 SCC1: CLSN1 Ethernet Timer2: TOUT SCC2: CTS1 SCC2: CLSN1 Ethernet Timer3/4: TGATE2 Default Input PSORC[x]
PC28
BRG4: BRGO
CLK4/TIN1
CLK8
PC27
BRG5: BRGO
CLK5
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Dedicated Assignments Port Table 3-5. Port Dedicated Assignment (PPARC (Continued)
Function PSORC[x] PDIRC[x] (Output) PC26 PC25 PC24 BRG6: BRGO BRG7: BRGO BRG8: BRGO PDIRC[x] (Input) CLK6 CLK7/TIN4 CLK8/TIN3 CLK9 SI1: L1ST1 Strobe SMC2: SMTXD CLK10 SCC1: SCC1: CLSN Ethernet SCC1: SCC1: RENA Ethernet SCC2: SCC2: CLSN Ethernet SCC2: SCC2: RENA Ethernet FCC1: Default Input CLK3 CLK4 PC29 FCC1: TxAddr0 MPHY, master FCC1: RxAddr0 MPHY, master FCC1: TxAddr1 MPHY, master FCC1: RxAddr1 MPHY, master FCC1: TxAddr2 MPHY, master, multiplexed polling PDIRC[x] (Output) Timer3: TOUT DMA2: DACK2 Timer4: TOUT DMA: DACK1 DMA: DREQ2 EXT2 DMA: DREQ1 FCC1: TxAddr01 MPHY, slave FCC1: RxAddr02 MPHY, slave FCC1: TxAddr12 MPHY, slave FCC1: RxAddr12 MPHY, slave FCC1: TxAddr22 MPHY, slave, multiplexed polling FCC1: TxClav12 MPHY, master, direct polling FCC1: RxAddr22 MPHY, slave, multiplexed polling FCC1: RxClav12 MPHY, master, direct polling FCC2: FCC2: PDIRC[x] (Input Unless Inout Specified) TMCLK Real-time counter Default Input BRGO1 PSORC[x]
PC23 PC22 PC15
PC14
SI1: L1ST2 Strobe SI1: L1ST4 Strobe SI1: L1ST3 Strobe SI2: L1ST1 Strobe
PC13
PC28
PC12
SI2: L1ST2 Strobe
FCC1:
FCC1: RxAddr2 MPHY, master, multiplexed polling
Notes:
SMC1: SMTXD SMC1:
SI2: L1ST3 Strobe SI2: L1ST4 Strobe
Available only when primary option this function used. MPHY Address pins (master mode) come from FCC2, depending CMXUAR programming. Multiplexing Programming model information MSC8101 Reference Manual. port signal number.
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Dedicated Assignments Port
Table 3-6. Port Dedicated Assignment (PPARD
Function PSORD[x] PDIRD[x] (Output) PD31 PD30 SCC1: SCC1: SCC1: TENA Ethernet PDIRD[x] (Input) SCC1: Default Input PDIRD[x] (Output) DMA: DRACK1 DMA: DRACK2 FCC1: RxAddr31 MPHY, master, multiplexed polling PDIRD[x] (Input Unless Inout Specified) DMA: DONE1 Inout DMA: DONE2 Inout FCC1: RxAddr32 MPHY, slave, multiplexed polling FCC1: RxClav2 MPHY, master, direct polling SPI: Default Input PSORD
PD29
PD19
FCC1: TxAddr41 MPHY, master, multiplexed polling
FCC1: TxAddr42 MPHY, slave, multiplexed polling FCC1: TxClav32 MPHY, master, direct polling FCC1: RxAddr42 MPHY, slave, multiplexed polling FCC1: RxClav32 MPHY, master, direct polling FCC1: RxPrty UTOPIA
BRG1: BRGO
PD18
FCC1: RxAddr41 MPHY, master, multiplexed polling
SPI: Inout
PD17 PD16
BRG2: BRGO FCC1: TxPrty UTOPIA
SPI: MOSI Inout SPI: MISO Inout FCC1: TxAddr31 MPHY, master, multiplexed polling FCC1: TxAddr32 MPHY, slave, multiplexed polling FCC1: TxClav22 MPHY, master, direct polling
MOSI
SMC1: SMSYN
Notes:
MPHY address pins (master mode) come from FCC2, depending CMXUAR programming. Multiplexing Programming model information MSC8101 Reference Manual. MPHY address pins (slave mode) come from FCC2, depending CMXUAR programming. Multiplexing Programming model information MSC8101 Reference Manual. port signal number.
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Reset
Table 4-1. Reset Causes
Direction Input Description PORESET initiates power-on reset flow that resets MSC8101s configures various attributes MSC8101, including clock mode.
Reset Causes
Name
Power-on reset (PORESET)
Hard reset (HRESET)
MSC8101 detect external assertion HRESET only occurs while MSC8101 asserting reset. During HRESET, SRESET asserted. HRESET open-drain pin. MSC8101 detect external assertion SRESET only occurs while MSC8101 asserting reset. SRESET open-drain pin. When MSC8101 watchdog count reaches zero, software watchdog reset signalled. enabled software watchdog event then generates internal hard reset sequence. When MSC8101 monitor count reaches zero, monitor hard reset asserted. enabled monitor event then generates internal hard reset sequence. When JTAG logic asserts JTAG soft reset signal, internal soft reset sequence generated.
Soft reset (SRESET)
Software watchdog reset
monitor reset
JTAG reset
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Table 4-2. Reset Actions Each Reset Source
Reset Logic States System Configuration Sampled HRESET Driven Other Internal Logic Reset
Reset Actions Each Reset Source
Reset Source
SRESET Driven
Core Reset
Power-on reset
External hard reset Software watchdog monitor
Reset Actions Each Reset Source
JTAG reset External soft reset
Table 4-3. External Configuration Signals
Description Reset Configuration Master. Reset Configuration Slave. SC140 core starts normal processing mode after reset. SC140 core enters Debug mode immediately after reset. Host port disabled (hardware reset configuration enabled). Host port enabled. MSC8101 boots from external memory. MSC8101 boots from HDI16. Reserved. Reserved. Settings
External Configuration Signals
RSTCONF
Reset Configuration Input line sampled MSC8101 rising edge PORESET.
Hard Reset Configuration Word
EONCE Event Input line sampled after core locks. Holding EE[0] logic exit from reset puts SC140 core into Debug mode.
HPE/EE1
Host Port Enable Input line sampled rising edge PORESET. asserted, Host port enabled, PowerPC data 32-bit wide, Host must program reset configuration word.
BTM[0-1]/ EE[4-5]
Boot Mode Input lines sampled rising edge PORESET, which determine MSC8101 Boot mode.
Hard Reset Configuration Word
Table 4-4. Hard Reset Configuration Word
Reset: IRQ7 SCDIS TCPC ISPS IRPC BC1PC DPPC DLLDIS Type: MODCK_H
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EARB
EXMC
Table 4-4. Hard Reset Configuration Word (Continued)
Hard Reset Configuration Word Descriptions Description External Arbitration External MEMC IRQ7 INT_OUT Selection External PowerPC Mode Boot Port Size SC140 Disabled Internal Space Port Size Interrupt Configuration Data Parity Configuration Non-Maskable Interrupt Handling Initial Internal Space Base Select Enabled 64-bit port 8-bit port IRQ7 INT_OUT None Internal arbitration External arbitration External memory controller Settings
Bits
Name
EARB
EXMC
IRQ7
programming model information MSC8101 Reference Manual. 16-bit port Disabled 32-bit port
SCDIS
ISPS
Reset programming model information MSC8101 Reference Manual. Reset programming model information MSC8101 Reference Manual. Reset programming model information MSC8101 Reference Manual. Serviced SC140 core Routed external serviced external host 0xF000_0000 0xF0F0_0000 0xFF00_0000 0xFFF0_0000 Reserved. 0x00F0_0000 0x0F00_0000 0x0FF0_0000 Reset programming model information MSC8101 Reference Manual. Reset programming model information MSC8101 Reference Manual. Reset programming model information MSC8101 Reference Manual. Reset programming model information MSC8101 Reference Manual. bypass bypass Reset programming model information MSC8101 Reference Manual.
IRPC
10-11 DPPC
13-15
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Busy Disable Mask Master's Request Transfer Code Configuration BC1PC Value Disable MODCK High-order Bits
18-19
22-23 TCPC
24-25 BC1PC
DLLDIS
Hard Reset Configuration Word
28-30 MODCK_H
Table 4-5. Core-Side Registers After Reset
Reset Type Register Name Reset HPCR HTFE HTFNF HRFNE HRFF HCVR HORX HOTX bits empty bits empty empty empty HF[0-3] bits bits Reset Register Data long dash denotes value indeterminate after reset. "Empty" means that data this location invalid (trash).
Host-Port Registers After Reset
Host-Port Registers After Reset
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Notes:
Table 4-6. Host-Side Registers After Reset
Reset Type Register Data Reset HV[0-6] HF[4-7] TRDY TXDE RXDF TX[0-3] empty RX[0-3] empty empty empty HREQ TREQ set; otherwise bits Reset
Register Name
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long dash denotes value indeterminate after reset. "Empty" means that data this location invalid (trash).
Notes:
Host-Port Registers After Reset
Memory Maps
Table 5-1. SC140 Core Internal Memory
SC140 Core Internal Address Mnemonic Name SC140 Core Internal 00000000-0007FFFF 00080000-00EFFDFF DSPRAM Reserved Internal (Ports Leave unchanged future compatibility EOnCE registers 00EFFE00-00EFFEFF EOnCE EOnCE registers bytes 14.5 Size
Table 5-2. QBus Memory Map-Bank0
SC140 Core Internal Address Mnemonic HDI16 Port 0000 0020 0040 0060 0080 00A0 HPCR HCVR HOTX HORX Host Control Register Host Port Control Register Host Status Register Host Command Vector Register Host Transmit Register Host Receive Register EFCOP-Port 0C00 0C20 0C40 0C60 0C80 0CA0 0CC0 0CE0 0D00 0D20 0D40-1BFF FDIR FDOR FKIR FCNT FCTL FACR FDBA FCBA FDCH FSTR Reserved EFCOP Data Input Register EFCOP Data Output Register EFCOP K-Constant Register EFCOP Filter Count Register EFCOP Control Register EFCOP Control Register EFCOP Data Base Address EFCOP Coefficient Base Address EFCOP Decimation/Channel Count Register EFCOP Status Register Leave unchanged future compatibility 32/64 bits 32/64 bits bits bits bits bits bits bits bits bits 3776 bytes bits bits bits bits bits bits Name Size
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Table 5-2. QBus Memory Map-Bank0 (Continued)
SC140 Core Internal Address Mnemonic 1C00 1C08 1C10 1C18 1C20 ELIRA ELIRB ELIRC ELIRD ELIRE ELIRF IPRA IPRB Reserved Edge/Level-Triggered Interrupt Register Edge/Level-Triggered Interrupt Register Edge/Level-Triggered Interrupt Register Edge/Level-Triggered Interrupt Register Edge/Level-Triggered Interrupt Register Edge/Level-Triggered Interrupt Register Interrupt Pending Register Interrupt Pending Register Leave unchanged future compatibility QBus Banks FF00 FF02 FF04 FF06 FF08 FF0a FF0C-FFFF QBUSMR0 QBUSBR0 QBUSMR1 QBUSBR1 QBUSMR2 QBUSBR2 Reserved QBus Mask Register QBus Base Address Register Select Peripheral QBus Mask Register QBus Base Address Register Select Peripheral QBus Mask Register QBus Base Address Register Select PowerPC Leave unchanged future compatibility bits bits bits bits bits bits bytes bits bits bits bits bits bits bits bits 58.04 Name Size
1C28 1C30 1C38 1C48-FEFF
Table 5-3. QBus Memory Map-Bank1
SC140 Core Internal Address Mnemonic Boot 0000-07FF 0800-FFFF BOOTROM Reserved MSC8101 Boot Leave unchanged future compatibility Name Size
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Table 5-4. PowerPC Local Memory
PowerPC Local Address Mnemonic Name Size
SC140 Core Internal Port Bank10 00000-7FFFF DSPRAM Internal RAM, Port HDI16 Port Bank11 0080 00A0 HOTX HORX Host Transmit Register Host Receive Register EFCOP Port Bank11 0C00 0C20 0C20-FFFF FDIR FDOR Reserved EFCOP Data Input Register EFCOP Data Output Register Leave unchanged future compatibility 32/64 bits 32/64 bits 3776 bytes bits bits
Table 5-5. PowerPC Memory
Internal Address Mnemonic Dual-Port 00000-03FFF 04000-07FFF 08000-08FFF 09000-0AFFF 0B000-0BFFF 0C000-0FFFF DPRAM1 Reserved DPRAM2 Reserved DPRAM3 Reserved Dual-Port Leave unchanged future compatibility Dual-Port Leave unchanged future compatibility Dual-Port Leave unchanged future compatibility General 10000 10004 10008 1000E 10010-10023 10024 10028 10029 SIUMCR SYPCR Reserved SWSR Reserved PPC_ACR Reserved Module Configuration Register System Protection Control Register Leave unchanged future compatibility Software Service Register Leave unchanged future compatibility Configuration Register PowerPC Arbiter Configuration Register Leave unchanged future compatibility bits bits bytes bits bytes bits bits bits Name Size
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Table 5-5. PowerPC Memory (Continued)
Internal Address 1002C 10030 10034 10035 10038 1003C Mnemonic PPC_ALRH PPC_ALRL LCL_ACR Reserved LCL_ALRH LCL_ALRL TESCR1 TESCR2 L_TESCR1 L_TESCR2 PDTEA PDTEM Reserved LDTEA LDTEM Reserved PDMTEA PDMTER Reserved LDMTEA LDMTER Reserved Name PowerPC Arbitration Level Register (bus masters 0-7) PowerPC Arbitration Level Register (bus masters 8-15) Local Arbiter Configuration Register Leave unchanged future compatibility Local Arbitration Level Register (bus masters 0-7) Local Arbitration Level Register (bus masters 8-15) PowerPC Transfer Error Status Control Register PowerPC Transfer Error Status Control Register PowerPC Local Transfer Error Status Control Register PowerPC Local Transfer Error Status Control Register PowerPC SDMA Transfer Error Address PowerPC SDMA Transfer Error MSNUM Leave unchanged future compatibility PowerPC Local SDMA Transfer Error Address PowerPC Local SDMA Transfer Error MSNUM Leave unchanged future compatibility PowerPC Transfer Error Address PowerPC Transfer Error RQNUM Leave unchanged future compatibility PowerPC Local Transfer Error Address PowerPC Local Transfer Error RQNUM Leave unchanged future compatibility Memory Controller 10100 10104 10108 1010C 10110 Base Register Bank0 Option Register Bank0 Base Register Bank1 Option Register Bank1 Base Register Bank2 bits bits bits bits bits Size bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bytes
10040 10044 10048 1004C 10050 10054 10055 10058 1005C 1005D-1005F 10060 10064 10065 10068 1006C 1006D-100FF
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Table 5-5. PowerPC Memory (Continued)
Internal Address 10114 10118 1011C 10120 10124 10128 1012C Mnemonic Reserved Reserved Reserved Reserved BR10 OR10 BR11 OR11 Reserved Reserved MAMR MBMR MCMR Reserved MPTPR Reserved Reserved PSDMR Reserved Option Register Bank2 Base Register Bank3 Option Register Bank3 Base Register Bank4 Option Register Bank4 Base Register Bank5 Option Register Bank5 Base Register Bank6 Option Register Bank6 Base Register Bank7 Option Register Bank7 Leave unchanged future compatibility Leave unchanged future compatibility Leave unchanged future compatibility Leave unchanged future compatibility Base Register Bank10 Option Register Bank10 Base Register Bank11 Option Register Bank11 Leave unchanged future compatibility Memory Address Register Leave unchanged future compatibility Machine Mode Register Machine Mode Register Machine Mode Register Leave unchanged future compatibility Memory Refresh Timer Prescaler Leave unchanged future compatibility Memory Data Register Leave unchanged future compatibility PowerPC SDRAM Mode Register Leave unchanged future compatibility Name Size bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bytes bits bits bits bits bits bytes bits bits bits bits bits bits
10130 10134 10138 1013C 10140 10144 10148 1014C 10150 10154 10158 1015C 10160 10168 1016C 10170 10174 10178 1017C 10184 10186 10188 1018C 10190 10194
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Table 5-5. PowerPC Memory (Continued)
Internal Address 10198 10199 1019C 1019D 101A0 101A4 101A8 Mnemonic PURT Reserved PSRT Reserved Reserved Reserved IMMR Reserved Name PowerPC Bus-Assigned Refresh Timer Leave unchanged future compatibility PowerPC Bus-Assigned SDRAM Refresh Timer Leave unchanged future compatibility Leave unchanged future compatibility Leave unchanged future compatibility Internal Memory Register Leave unchanged future compatibility System Integration Timers 10200-1021F 10220 10222 10224 10228 1022C 10230-1023F 10240 10242 10244 10248 1024C-1029F 102AO-106FF Reserved TMCNTSC Reserved TMCNT Reserved TMCNTAL Reserved PISCR Reserved PITC PITR Reserved Reserved Leave unchanged future compatibility Time Counter Status Control Register Leave unchanged future compatibility Time Counter Register Leave unchanged future compatibility Time Counter Alarm Register Leave unchanged future compatibility Periodic Interrupt Status Control Register Leave unchanged future compatibility Periodic Interrupt Count Register Periodic Interrupt Timer Register Leave unchanged future compatibility Leave unchanged future compatibility 10700 10704 10708 1070C 10710 10714 10718 1071C DCHCR0 DCHCR1 DCHCR2 DCHCR3 DCHCR4 DCHCR5 DCHCR6 DCHCR7 Channel Configuration Register Channel Configuration Register Channel Configuration Register Channel Configuration Register Channel Configuration Register Channel Configuration Register Channel Configuration Register Channel Configuration Register bits bits bits bits bits bits bits bits bytes bits bits bits bits bits bytes bits bits bits bits bytes 1120 bytes Size bits bits bits bits bits bits bits bytes
101AC-101FF
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Table 5-5. PowerPC Memory (Continued)
Internal Address 10720 10724 10728 1072C 10730 10734 10738 Mnemonic DCHCR8 DCHCR9 DCHCR10 DCHCR11 DCHCR12 DCHCR13 DCHCR14 DCHCR15 Reserved DIMR DSTR DTEAR Reserved DPCR Reserved DEMR Reserved DCPRAM Name Channel Configuration Register Channel Configuration Register Channel Configuration Register Channel Configuration Register Channel Configuration Register Channel Configuration Register Channel Configuration Register Channel Configuration Register Leave unchanged future compatibility Internal Mask Register Status Register Status Register Leave unchanged future compatibility Configuration Register Leave unchanged future compatibility External Mask Register Leave unchanged future compatibility Channel Parameter Interrupt Controller 10C00 10C02 10C04 10C08 10C0C 10C10 10C14 10C18 10C1C 10C20 10C24 10C28-10C3F SICR Reserved SIVEC SIPNR_H SIPNR_L SIPRR SCPRR_H SCPRR_L SIMR_H SIMR_L SIEXR Reserved Interrupt Configuration Register Leave unchanged future compatibility Interrupt Vector Register Interrupt Pending Register (high) Interrupt Pending Register (low) Interrupt Priority Register Interrupt Priority Register (high) Interrupt Priority Register (low) Interrupt Mask Register (high) Interrupt Mask Register (low) External Interrupt Control Register Leave unchanged future compatibility bits bits bits bits bits bits bits bits bits bits bits bytes Size bits bits bits bits bits bits bits bits bytes bits bits bits bits bits bits bits bytes 1024 bytes
1073C 10740-1077F 10780 10784 10788 10789-1078B 1078C 1078D-1078F 10790 10794-107FF 10800-10BFF
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Table 5-5. PowerPC Memory (Continued)
Internal Address 10C40 10C42 10C44 10C48 10C4C 10C50 10C54 Mnemonic SICR_EXT Reserved SIVEC_EXT SIPNR_H_EXT SIPNR_L_EXT SIPRR_EXT Name Interrupt Configuration Register Leave unchanged future compatibility Interrupt Vector Register Interrupt Pending Register (high) Interrupt Pending Register (low) Interrupt Priority Register Size bits bits bits bits bits bits bits bits bits bits bits bytes
SCPRR_H_EXT Interrupt Priority Register (high) SCPRR_L_EXT SIMR_H_EXT SIMR_L_EXT SIEXR_EXT Reserved Interrupt Priority Register (low) Interrupt Mask Register (high) Interrupt Mask Register (low) External Interrupt Control Register Leave unchanged future compatibility Clocks Reset
10C58 10C5C 10C60 10C64 10C68-10C7F
10C80 10C84 10C88 10C8C 10C90 10C94 10C98-10CFF
SCCR Reserved SCMR Reserved Reserved Reserved
System Clock Control Register Leave unchanged future compatibility System Clock Mode Register Leave unchanged future compatibility Reset Status Register Leave unchanged future compatibility Leave unchanged future compatibility Input/Output Port
bits bits bits bits bits bits bytes
10D00 10D04 10D08 10D0C 10D10 10D14-10D1F 10D20 10D24 10D28 10D2C
PDIRA PPARA PSORA PODRA PDATA Reserved PDIRB PPARB PSORB PODRB
Port Data Direction Register Port Assignment Register Port Special Options Register Port Open-Drain Register Port Data Register Leave unchanged future compatibility Port Data Direction Register Port Assignment Register Port Special Options Register Port Open-Drain Register
bits bits bits bits bits bytes bits bits bits bits
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Table 5-5. PowerPC Memory (Continued)
Internal Address 10D30 10D34-10D3F 10D40 10D44 10D48 10D4C 10D50 Mnemonic PDATB Reserved PDIRC PPARC PSORC PODRC PDATC Reserved PDIRD PPARD PSORD PODRD PDATD Reserved Port Data Register Leave unchanged future compatibility Port Data Direction Register Port Assignment Register Port Special Options Register Port Open-Drain Register Port Data Register Leave unchanged future compatibility Port Data Direction Register Port Assignment Register Port special options register Port Open Drain Register Port Data Register Leave unchanged future compatibility Timers 10D80 10D81 10D84 10D85-10D8F 10D90 10D92 10D94 10D96 10D98 10D9A 10D9C 10D9E 10DA0 10DA2 10DA4 10DA6 TGCR1 Reserved TGCR2 Reserved TMR1 TMR2 TRR1 TRR2 TCR1 TCR2 TCN1 TCN2 TMR3 TMR4 TRR3 TRR4 Timer Timer Global Configuration Register Leave unchanged future compatibility Timer Timer Global Configuration Register Leave unchanged future compatibility Timer Mode Register Timer Mode Register Timer Reference Register Timer Reference Register Timer Capture Register Timer Capture Register Timer Counter Timer Counter Timer Mode Register Timer Mode Register Timer Reference Register Timer Reference Register bits bits bits bytes bits bits bits bits bits bits bits bits bits bits bits bits Name Size bits bytes bits bits bits bits bits bytes bits bits bits bits bits bytes
10D54-10D5F 10D60 10D64 10D68 10D6C 10D70 10D74-10D7F
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Table 5-5. PowerPC Memory (Continued)
Internal Address 10DA8 10DAA 10DAC 10DAE 10DB0 10DB2 10DB4 Mnemonic TCR3 TCR4 TCN3 TCN4 TER1 TER2 TER3 TER4 Reserved Name Timer Capture Register Timer Capture Register Timer Counter Timer Counter Timer Event Register Timer Event Register Timer Event Register Timer Event Register Leave unchanged future compatibility SDMA-General 11018 11019 1101C 1101D 11020-112FF SDSR Reserved SDMR Reserved Reserved SDMA Status Register Leave unchanged future compatibility SDMA Mask Register Leave unchanged future compatibility Reserved FCC1 11300 11304 11308 1130A 1130C 1130E 11310 11314 11318 11319-1131B 1131C 1131D 1131E 1131F GFMR1 FPSMR1 FTODR1 Reserved FDSR1 Reserved FCCE1 FCCM1 FCCS1 Reserved FTIRR1_PHY0 FTIRR1_PHY1 FTIRR1_PHY2 FTIRR1_PHY3 FCC2 FCC1 General Mode Register FCC1 Protocol-Specific Mode Register FCC1 Transmit Demand Register Leave unchanged future compatibility FCC1 Data Synchronization Register Leave unchanged future compatibility FCC1 Event Register FCC1 Mask Register FCC1 Status Register Leave unchanged future compatibility FCC1 Transmit Internal Rate Registers PHY[0-3] bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bytes Size bits bits bits bits bits bits bits bits bytes
10DB6 10DB8
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Table 5-5. PowerPC Memory (Continued)
Internal Address 11320 11324 11328 1132A 1132C 1132E 11330 Mnemonic GFMR2 FPSMR2 FTODR2 Reserved FDSR2 Reserved FCCE2 FCCM2 FCCS2 Reserved FTIRR2_PHY0 FTIRR2_PHY1 FTIRR2_PHY2 FTIRR2_PHY3 FCC3 11340 11344 11348 1134A 1134C 1134E 11350 11354 11358 11359-115EF GFMR3 FPSMR3 FTODR3 Reserved FDSR3 Reserved FCCE3 FCCM3 FCCS3 Reserved FCC3 General Mode Register FCC3 Protocol-Specific Mode Register FCC3 Transmit On-Demand Register Leave unchanged future compatibility FCC3 Data Synchronization Register Leave unchanged future compatibility FCC3 Event Register FCC3 Mask Register FCC3 Status Register Leave unchanged future compatibility BRGs[5-8] 115F0 115F4 115F8 115FC 11600-1185F BRGC5 BRGC6 BRGC7 BRGC8 Reserved BRG5 Configuration Register BRG6 Configuration Register BRG7 Configuration Register BRG8 Configuration Register Leave unchanged future compatibility bits bits bits bits bytes bits bits bits bits bits bits bits bits bits bytes Name FCC2 General Mode Register FCC2 Protocol-Specific Mode Register FCC2 Transmit On-Demand Register Leave unchanged future compatibility FCC2 Data Synchronization Register Leave unchanged future compatibility FCC2 Event Register FCC2 Mask Register FCC2 Status Register Leave unchanged future compatibility FCC2 Transmit Internal Rate Registers PHY[0-3] Size bits bits bits bits bits bits bits bits bits bits bits bits bits bits
11334 11338 11339 1133C 1133D 1133E 1133F
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Table 5-5. PowerPC Memory (Continued)
Internal Address Mnemonic 11860 11862 11864 11866 11868 I2MOD Reserved I2ADD Reserved I2BRG Reserved I2COM Reserved I2CER Reserved I2CMR Reserved Mode Register Leave unchanged future compatibility Address Register Leave unchanged future compatibility Register Leave unchanged future compatibility Command Register Leave unchanged future compatibility Event Register Leave unchanged future compatibility Mask Register Leave unchanged future compatibility Communications Processor 119C0 119C4 119C8 119D6 119D8 119DA 119DC 119DE 119E0 119E4 CPCR RCCR Reserved RTER Reserved RTMR RTSCR Reserved RTSR Reserved Communications Processor Command Register Configuration Register Leave unchanged future compatibility Timers Event Register Leave unchanged future compatibility Timers Mask Register Time-Stamp Timer Control Register Leave unchanged future compatibility Time-Stamp Register Leave unchanged future compatibility BRGs[1-4] 119F0 119F4 119F8 119FC BRGC1 BRGC2 BRGC3 BRGC4 BRG1 Configuration Register BRG2 Configuration Register BRG3 Configuration Register BRG4 Configuration Register SCC1 11A00 GSMR_L1 SCC1 General Mode Register (low) bits bits bits bits bits bits bits bytes bits bits bits bits bits bits bytes bits bits bits bits bits bits bits bits bits bits bits bytes Name Size
1186A 1186C 1186E 11870 11872 11874 11875-119BF
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Table 5-5. PowerPC Memory (Continued)
Internal Address 11A04 11A08 11A0A 11A0C 11A0E 11A10 11A12 Mnemonic GSMR_H1 PSMR1 Reserved TODR1 DSR1 SCCE1 Reserved SCCM1 Reserved SCCS1 Reserved Name SCC1 General Mode Register (high) SCC1 Protocol-Specific Mode Register Leave unchanged future compatibility SCC1 Transmit-on-Demand Register SCC1 Data Synchronization Register SCC1 Event Register Leave unchanged future compatibility SCC1 Mask Register Leave unchanged future compatibility SCC1 Status Register Leave unchanged future compatibility SCC2 11A20 11A24 11A28 11A2A 11A2C 11A2E 11A30 11A32 11A34 11A36 11A37 11A38-11A3F GSMR_L2 GSMR_H2 PSMR2 Reserved TODR2 DSR2 SCCE2 Reserved SCCM2 Reserved SCCS2 Reserved SCC2 General Mode Register (low) SCC2 General Mode Register (high) SCC2 Protocol-Specific Mode Register Leave unchanged future compatibility SCC2 Transmit-on-Demand Register SCC2 Data Synchronization Register SCC2 Event Register Leave unchanged future compatibility SCC2 Mask Register Leave unchanged future compatibility SCC2 Status Register Leave unchanged future compatibility SCC3 11A40 11A44 11A48 11A4A 11A4C 11A4E GSMR_L3 GSMR_H3 PSMR3 Reserved TODR3 DSR3 SCC3 General Mode Register (low) SCC3 General Mode Register (high) SCC3 Protocol-Specific Mode Register Leave unchanged future compatibility SCC3 Transmit-on-Demand Register SCC3 Data Synchronization Register bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bytes Size bits bits bits bits bits bits bits bits bits bits bytes
11A14 11A16 11A17 11A18-11A1F
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Table 5-5. PowerPC Memory (Continued)
Internal Address 11A50 11A52 11A54 11A56 11A57 11A58-11A5F Mnemonic SCCE3 Reserved SCCM3 Reserved SCCS3 Reserved SCC3 Event Register Leave unchanged future compatibility SCC3 Mask Register Leave unchanged future compatibility SCC3 Status Register Leave unchanged future compatibility SCC4 Name Size bits bits bits bits bits bytes
11A60 11A64 11A68 11A6A 11A6C 11A6E 11A70 11A72 11A74 11A76 11A77 11A40-11A7F
GSMR_L4 GSMR_H4 PSMR4 Reserved TODR4 DSR4 SCCE4 Reserved SCCM4 Reserved SCCS4 Reserved
SCC4 General Mode Register (low) SCC4 General Mode Register (high) SCC4 Protocol-Specific Mode Register Leave unchanged future compatibility SCC4 Transmit-on-Demand Register SCC4 Data Synchronization Register SCC4 Event Register Leave unchanged future compatibility SCC4 Mask Register Leave unchanged future compatibility SCC4 Status Register Leave unchanged future compatibility SMC1
bits bits bits bits bits bits bits bits bits bits bits bytes
11A80 11A82 11A84 11A86 11A87 11A8A 11A8B-11A8F
Reserved SMCMR1 Reserved SMCE1 Reserved SMCM1 Reserved
Leave unchanged future compatibility SMC1 Mode Register Leave unchanged future compatibility SMC1 Event Register Leave unchanged future compatibility SMC1 Mask Register Leave unchanged future compatibility SMC2
bits bits bits bits bits bits bytes
11A90 11A92 11A94
Reserved SMCMR2 Reserved
Leave unchanged future compatibility SMC2 Mode Register Leave unchanged future compatibility
bits bits bits
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Table 5-5. PowerPC Memory (Continued)
Internal Address 11A96 11A97 11A9A 11A9B-11A9F Mnemonic SMCE2 Reserved SMCM2 Reserved SMC2 Event Register Leave unchanged future compatibility SMC2 Mask Register Leave unchanged future compatibility 11AA0 11AA2 SPMODE Reserved SPIE Reserved SPIM Reserved SPCOM Reserved Mode Register Leave unchanged future compatibility Event Register Leave unchanged future compatibility Mask Register Leave unchanged future compatibility Command Register Leave unchanged future compatibility 11B00 11B01 11B02 11B03 11B04 11B08 11B0C 11B0D 11B0E 11B10-11B1F CMXSI1CR Reserved CMXSI2CR Reserved CMXFCR CMXSCR CMXSMR Reserved CMXUAR Reserved Clock Route Register Leave unchanged future compatibility Clock Route Register Leave unchanged future compatibility Clock Route Register Clock Route Register Clock Route Register Leave unchanged future compatibility UTOPIA Address Register Leave unchanged future compatibility Registers 11B20 11B22 11B24 11B26 11B28 11B29 SI1AMR Reserved Reserved Reserved SI1GMR Reserved TDMA1 Mode Register Leave unchanged future compatibility Leave unchanged future compatibility Leave unchanged future compatibility Global Mode Register Leave unchanged future compatibility bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bytes bits bits bits bits bits bits bits bytes Name Size bits bits bits bytes
11AA6 11AA7 11AAA 11AAB 11AAD 11AAE-11AFF
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Table 5-5. PowerPC Memory (Continued)
Internal Address 11B2A 11B2B 11B2C 11B2D 11B2E Mnemonic SI1CMDR Reserved SI1STR Reserved SI1RSR Command Register Leave unchanged future compatibility Status Register Leave unchanged future compatibility Shadow Address Register MCC1 Registers 11B30 MCCE1 Reserved MCCM1 Reserved MCCF1 Reserved MCC1 Event Register Leave unchanged future compatibility MCC1 Mask Register Leave unchanged future compatibility MCC1 Configuration Register Leave unchanged future compatibility Registers 11B40 11B42 11B44 11B46 11B48 11B49 11B4A 11B4B 11B4C 11B4D 11B4E Reserved SI2BMR SI2CMR SI2DMR SI2GMR Reserved SI2CMDR Reserved SI2STR Reserved SI2RSR Leave unchanged future compatibility TDMB2 Mode Register TDMC2 Mode Register TDMD2 Mode Register Global Mode Register Leave unchanged future compatibility Command Register Leave unchanged future compatibility Status Register Leave unchanged future compatibility Shadow Address Register MCC2 Registers 11B50 11B52 11B54 11B56 11B58 11B59-11FFF MCCE2 Reserved MCCM2 Reserved MCCF2 Reserved MCC2 Event Register Leave unchanged future compatibility MCC2 Mask Register Leave unchanged future compatibility MCC2 Configuration Register Leave unchanged future compatibility bits bits bits bits bits 1191 bytes bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits bytes Name Size bits bits bits bits bits
11B32 11B34 11B36 11B38 11B39-11B3F
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Table 5-5. PowerPC Memory (Continued)
Internal Address Mnemonic 12000-121FF 12200-123FF 12400-125FF 12600-127FF SI1TxRAM Reserved SI1RxRAM Reserved Transmit Touting Leave unchanged future compatibility Receive Touting Leave unchanged future compatibility bytes bytes bytes bytes Name Size
12800-129FF 12A00-12BFF 12C00-12DFF 12E00-12FFF 13000-137FF 13800-13FFF
SI2TxRAM Reserved SI2RxRAM Reserved Reserved Reserved
Transmit Routing Leave unchanged future compatibility Receive Routing Leave unchanged future compatibility Leave unchanged future compatibility Leave unchanged future compatibility
bytes bytes bytes bytes 2048 bytes 2048 bytes
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Registers
Table 6-1. Register Description Conventions
Meaning resets logic resets logic Convention Meaning Reserved bit. Write zero future compatibility
Convention
Read-only bit. Writing this effect.
Write-only bit.
Standard read/write bit.
Table 6-2. Core Registers Summary
Register Name Address Stack pointer Shadow stack pointer Base address Offset Modifier Modifier control Data Program counter Status Exception mode Start address Loop counter 32-bit 32-bit. Reflects controls exception situations core Description 32-bit, R/W. Contain addresses general-purpose data
Core Registers
Mnemonic
R[0-15]
NSP,
32-bit. Used implicitly PUSH instructions: Normal mode, Exception mode Contain decremented values stack pointers 32-bit, R/W. Used modulo calculations associated with registers with 32-bit, R/W. Contain offset values increment decrement address registers. Also used 32-bit general-purpose storage 32-bit, R/W. Contain value modulus modifier. Also used general-purpose storage 32-bit, R/W. Programs address mode each address, R[0-7] 40-bit. Used perform arithmetic logical operations data operands
B[0-7]
N[0-3]
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M[0-3]
MCTL
D[0-15]
SA[0-3]
Core Registers
LC[0-3]
ADDRESS GENERATION UNIT (AGU) D12.e D13.e D14.e D15.e D11.e D10.e D10.h D11.h D12.h D13.h D14.h D15.h D9.e D9.h D8.e D8.h D8.I D9.I D10.I D11.I D12.I D13.I D14.I D15.I D7.e D7.h D7.I D6.e D6.h D6.I D5.e D5.h D5.I D4.e D4.h D4.I D3.e D3.h D3.I D2.e D2.h D2.I D1.e D1.h D1.I DO.e DO.h DO.I R8/B0 R9/B1 R10/B2 R11/B3 R12/B4 R13/B5 R14/B6 R15/B7 MCTL DATA ARITHMETIC LOGIC UNIT (DALU)
Base Address Registers Offset Modifier Registers
Core Registers
(NSP, ESP)
Address Registers
PROGRAM SEQUENCER UNIT (PSEQ)
Program Counter
Status Register
Exception Mode Register
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Loop Counter Registers Figure 6-1. SC140 Programming Model
Start Address Registers
Table 6-3. Core Registers
Reset: AM[3-0] AM[3-0] Address Modifier (AM[3-0]) Descriptions Mode Descriptions1 AM[3-0] AM[3-0] AM[3-0] Type: 0x10C92
MCTL
Modifier Control Register
AM[3-0]
AM[3-0]
AM[3-0]
Linear addressing
Reverse-carry addressing
used-Modulo addressing
used-Modulo addressing
used-Modulo addressing
used-Modulo addressing
used-Multiple wrap-around modulo addressing
used-Multiple wrap-around modulo addressing
used-Multiple wrap-around modulo addressing
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used-Multiple wrap-around modulo addressing
Notes:
other field combinations reserved should used. Type:
Status Register
Reset
Core Registers
Reset
Table 6-3. Core Registers (Continued)
Descriptions Description Short Loop Flag Loop Flag Loop Flag Loop Flag Loop Flag Interrupt Mask Notes: Overflow Exception Enable Disable Interrupts Exception Mode Viterbi Flags Exceptions Permitted IPL[1-7] IPL[2-7] IPL[3-7] IPL[4-7] IPL[5-7] IPL[6-7] IPL7 IPL0 exception always masked. Overflow exception generation disabled Overflow exception generation enabled, unless EMR[DOVF] Interrupts enabled Interrupts disabled Normal processing mode, active stack pointer Exception processing mode, active stack pointer Appropriate 16-bit portion transferred Appropriate 16-bit portion transferred Exceptions Masked IPL0 IPL[0-1] IPL[0-2] IPL[0-3] IPL[0-4] IPL[0-5] IPL[0-6] IPL[0-7] Hardware loop enabled Hardware loop enabled Hardware loop enabled Hardware loop enabled Active loop length three more execution sets Active loop length execution sets Hardware loop enabled Hardware loop enabled Hardware loop enabled Hardware loop enabled Settings
Bits
Name
Core Registers
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23-21 I[2-0]
11-8 VF[3-0]
Table 6-3. Core Registers (Continued)
Scaling Scaling Mode Reserved Scale Scale down scaling Scaling Mode Equation (D30 D29) (previous) (D31 D30) (previous) (D29 D28) (previous) Undefined
S[1-0]
Rounding Mode Arithmetic Saturation Mode True Carry
Scaling Mode scaling Scale down (1-bit Arithmetic right shift Scale (1-bit Arithmetic left shift Reserved
Rounding
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Convergent rounding selected Two's complement rounding selected Mode selected
Mode selected Condition tested compare test instruction false Condition tested compare test instruction true carry borrow generated Carry generated from last addition, borrow generated from last subtraction
Core Registers
Table 6-3. Core Registers (Continued)
Type: DOVF Descriptions Description General Purpose Flags Endian Memory Non-Maskable Interrupt (NMI) Disable DALU Overflow Illegal Execution Illegal Instruction Little endian configuration service executing endian configuration Service executing Settings NMID ILST ILIN 0x10C92
overflow arithmetic saturation occurred Overflow arithmetic saturation occurred execution rule violated Execution rule violated instruction violation more opcodes received part SC140 instruction
Exception Mode Register
Core Registers
Type
Reset
Type
Reset
Bits
Name
23-17 GP[6-0]
NMID
DOVF
ILST
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ILIN
Table 6-4. QBus Registers
Bank Registers Internal Address Bank Slaves 0xFFFF 0x00F0 0x001C 0xFFFC 0x001F 0xFFFF Reset Value Base Reg. Mask Reg. Bank Size 0x{Base0,FF00} 0x{Base0,FF02} Examples Bank Address Mask Register Values Address Range Match 0x001F0000- 0x001FFFFF 0x001C0000- 0x001FFFFF Null possible match)
Extended Core Registers
Name
Description
QBUSMR0
Mask0 (option) Register
QBUSBR0
Base0 Address Register 0x{Base0,FF04} 0x{Base0,FF06} 0x{Base0,FF08} 0x{Base0,FF0A} Cacheable memory PowerPC 0x0000 0xFFFF 0x00F8 Boot 0xFFFF 0x001F 0xFFFF
Bank registers Peripherals: Host Interface EFCOP
QBUSMR1
Mask1 (option) Register
QBUSBR1
Base1 Address Register
QBUSMR2
Mask2 (option) Register
QBUSBR2
Base2 Address Register
Table 6-5. HDI16 Registers
Reset: Depends reset configuration sequence HDM0 HDM1 HDM2 DBTE DBRE HCIE Type: HTFIE HTEIE HRFIE 0x0000 HREIE 0x0000 DBTE DBRE HCIE HTFIE HTEIE HRFIE HREIE HICR
Host Control Register (HICR
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Reset: Depends reset configuration sequence RREQ HICR
Host Control Register (HICR
Extended Core Registers
Type
Table 6-5. HDI16 Registers (Continued)
Descriptions Description Host Flags ICR/HCR priority DMA/Last Address Mode Host DMA/Last Address Mode Control DMA/last address mode defined HCR; Defined information host mode control values MSC8101 Reference Manual. Values reflected Settings
ICR[HM] Status Transmit Burst Enable Receive Burst Enable Host Command Interrupt Enable Host Transmit Full Interrupt Enable Host Transmit Empty Interrupt Enable Host Receive Full Interrupt Enable Host Receive Empty Interrupt Enable Disabled Disabled Disabled Disabled Disabled Disabled Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Type: HTFNF HTFE HRFF 0x0040 HRFNE Reset: Depends reset configuration sequence Descriptions Description Host Flags Host Transmit FIFO Full Host Transmit FIFO Empty Host Receive FIFO Full Host Receive FIFO Empty Values reflect ICR(HF[0-3]) Full empty full Empty full Empty Full empty Settings
Bits
Name
HF[4-7]
HICR
Extended Core Registers
HDM[0-2]
RREQ (HICR RREQ Status
(HICR
DBTE
DBRE
HCIE
HTFIE
HTEIE
HRFIE
HREIE
Host Status Register
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Bits
Name
HF[0-3]
HTFNF
HTFE
HRFF
HRFNE
Table 6-5. HDI16 Registers (Continued)
Reset: HCVR Descriptions Description Host Command Pending Host Vector Reset: Depends reset configuration sequence HPCR Descriptions Description Host Acknowledge Polarity Host Request Polarity HACK active input Single host request mode: Request signal active Request signal active high HCS1 HCS2 active Settings HACK active high input Double request mode: HTRQ, HRRQ active HDRQ, HRRQ active high HCS1 HCS2 active high HDSP H8BIT Value reflects CVR[HV] Type: 0x0020 Value reflects CVR[HC] Settings Type: 0x0060
HCVR
Host Command Vector Register
Bits
Name
9-12
HPCR HDDS HCSP
Host Port Control Register
Bits
Name
Host Dual Data Strobe Host Data Strobe Polarity Host Enable H8-Bit Mode Host Mode Enable One-Address Host Mode Enable
HCSP
Host Chip-Select Polarity
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Data strobe active HDI16 internal clock frozen HDI16 operates host interface 16-bit mode (default) enabled Disabled
HDDS
HDI16 operates single-strobe mode HDI16 operates dual-strobe mode Data strobe active high
HDSP
H8BIT
8-bit mode enabled Enabled HACK input used transfer acknowledge input Host address used host transfer acknowledge input
Extended Core Registers
Table 6-5. HDI16 Registers (Continued)
Type: 0x0080
Type: 0x00A0 Reset:: Depends reset configuration sequence Reset:: Depends reset configuration sequence Reset:: Depends reset configuration sequence Reset:: Depends reset configuration sequence INIT Descriptions Description Host Flags Force Initialization Host Mode/Host Mode Host Flags HREQ/HTRQ HACK/HRRQ Control (Available only non-DMA [interrupt] mode) Settings Host clear; these bits reflected HSR[HF] bits. Host set, then HDI16 runs INIT command clears INIT bit. information host mode control values MSC8101 Reference Manual. Host clear; these bits reflected HSR[HF] bits. HREQ HACK HTRQ HRRQ HDM0 when read, RREQ when written. Note INIT HDRQ Note TREQ INIT INIT HDRQ Type: TREQ RREQ TREQ RREQ RREQ Type:
HOTX
Host Transmit Data Register
four 64-bit word FIFO. HOTX empty, writing clears HSR[HTFE]. HOTX contains three 64-bit words, writing clears HTFNF.
HORX
Host Receive Data Register
four 64-bit word FIFO. HORX full, reading clears HSR[HRFF]. HORX contains 64-bit word, reading clears HSR[HRFNE].
Host Interface Control Register (DMA HICR
Extended Core Registers
Host Interface Control Register (DMA HICR
Host Interface Control Register (DMA HICR
Type
Host Interface Control Register (DMA HICR
Type
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Notes:
HDM0 when read, TREQ when written.
Bits
Name
HF[0-1]
INIT
9-10 HM/HDM[0-2]
11-12 HF[2-3]
HDRQ
Table 6-5. HDI16 Registers (Continued)
HREQ/HTREQ Control HREQ HRREQ Control Reset: Depends reset configuration sequence Descriptions Description Non-Maskable Interrupt Host Command Host Vector bits Reset: Depends reset configuration sequence Descriptions Description HREQ Status Settings HDRQ cleared: host processor interrupts requested Interrupt requested HDRQ set: host processor interrupts requested (HTRQ HRRQ cleared) Interrupt requested (HTRQ HRRQ set) Reflect state HCR[HF] bits TX[0-3] HORX FIFO empty TTX[0-3] HORX FIFO empty registers empty registers empty written host processor registers full registers full read host processor HREQ Type: TRDY TXDE RXDF Settings Type: RREQ when written; HDM0 when read TREQ when written; HDM0 when read
TREQ/HDM0
RREQ/HDM0
Command Vector Register
Bits
Name
9-15
Interface Status Register
Bits
Name
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Host flags TRDY Status Transmit Data Empty Receive Data Full
HREQ
9-12 HF[4-7]
TRDY
TXDE
Extended Core Registers
RXDF
Table 6-5. HDI16 Registers (Continued)
Type: Type: Type: (RSCFG0) (RSCFG1) (TX0) (TX1) (TX2) (TX3) (RSCFG2) (RSCFG3) (RX0) (RX1) (RX2) (RX3)
Table 6-6. EFCOP Registers
Reset: FCNT (Number coefficients minus Reset: FINFIE FCTL Descriptions Description Data Output Mode Data Input Mode Data Output Empty Interrupt Enable Data Output Full Interrupt Enable Data Input Full Interrupt Enable Data Input Empty Interrupt Enable Coefficients Update Done Interrupt Enable Coefficients Initialization Mode Filter Processing State Initialization Mode Filter Multichannel Mode Settings triggered output buffer empty triggered output buffer full triggered input buffer full triggered input buffer empty Disabled Disabled Disabled Disabled Disabled Disabled Enabled Enabled Enabled Enabled Enabled Enabled EFCOP processing starts after state initialization EFCOP processing starts with state initialization Disabled Enabled FIEIE FUDIE FCIM FPRC FMLC Type: FUPD FAPD 0x0C80 Type: 0x0C60 FONEIE FOFIE
Receive Word Registers [0-3]
Transmit Word Registers [0-3]
Extended Core Registers
RSCF
Reset Configuration Registers [0-3]
FCNT
Filter Count Register
FCTL
EFCOP Control Register
FDOM
FDIM
Bits
Name
FDOM
FDIM
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FONEIE
FOFIE
FINFIE
FIEIE
FUDIE
FCIM
FPRC
FMLC
Table 6-6. EFCOP Registers (Continued)
Filter Operation Mode Mode Real filter Mode Full complex filter Mode Complex filter with alternate real imaginary outputs Mode Magnitude Update mode disabled Disabled filter filter Enabled Update mode enabled
Filter Adaptive Mode Filter Type Filter Enable Reset: FACR Descriptions Description Filter Shared Coefficients Mode Filter Input Scale Filter Rounding Mode Settings Coefficients stored sequentially each channel Same coefficients used each channel Scale both feedback terms input Scale feedback terms only Convergent rounding Two's complement rounding Truncation rounding) Reserved Scaling factor shift) Scaling factor (3-bit arithmetic left shift) Scaling factor (43-bit arithmetic left shift) Reserved Reset: FDBA Reset: FDBA Type: Type: FSCO FISL
FUPD
Filter Update
FADP
EFCOP disabled (individual reset) EFCOP enabled Type: FSCL 0x0CA0
FACR
EFCOP Control Register
Bits
Name
FSCO
FISL
12-13
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Filter Scaling
14-15 FSCL
FDBA
EFCOP Data Base Address
0x0CC0
FCBA
EFCOP Coefficient Base Address
0x0CE0
Extended Core Registers
Table 6-6. EFCOP Registers (Continued)
Reset: FDCM FDCH Descriptions Description Filter Decimation Filter Channels Reset: FSTR Descriptions Description Filter Data Output Buffer Empty Filter Data Output Buffer Full Filter Data Input Buffer Full Filter Data Input Buffer Empty Coefficients Update Done Filter Overflow Filter Saturation FDIR full FDIR empty Session ended FDOR full FDOR empty Settings FDOR empty FDOR full FDIR full FDIR empty Session ended FOBNE FDOBF FIBNF FDIBE 0-63 Number channels process minus Type: FUDN FOVF 0x0D20 FSAT 0-15 Decimation factor minus Settings FCHL Type: 0x0D00
FMAC addition over- underflow over- underflow over- underflow saturation Saturation
FDCH
EFCOP Decimation/Channel Count Register
Extended Core Registers
Bits
Name
FDCM
10-15 FCHL
FSTR
EFCOP Status Register
Bits
Name
FONBE
FDOBF
FIBNF
FDIBE
FUDN
FOVF
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Table 6-7. Registers
Reset: PIL21 PIL22 PED1 PIL10 Reset: PIL60 PIL61 PIL62 PED5 PIL50 PIL51 PIL52 PIL11 PIL12 PIL32 PED2 PIL20 PIL31 PIL72 PED6 PIL71
FSAT
ELIRA Edge/Level-Triggered Interrupt Priority Register
Type: PED0 PIL00 Type: PED4 PIL40 PIL41 PIL01
0x1C00 PIL02 0x1C08 PIL42
PED3
PIL30
ELIRB Edge/Level-Triggered Interrupt Priority Register
PED7
PIL70
Table 6-7. Registers (Continued)
Reset: PIL101 Reset: PIL141 PIL142 PED13 PIL130 PIL131 PIL132 PED12 PIL120 Type: PIL121 PIL102 PED9 PIL91 PED8 PIL80 PIL81 Type: 0x1C10 PIL82 0x1C18 PIL122 0x1C20 PIL160 Type: PIL221 ELIRx Descriptions Description Trigger Mode Input Priority Level Input Level-triggered mode Interrupts disabled (lowest priority) 2/IPL3 Reset: IP11 IP10 Settings Edge-triggered mode (highest priority) Type: 0x1C30 PIL222 PED21 PIL210 PIL211 PIL212 PED20 PIL200 PIL201 PIL161 PIL162 0x1C28 PIL202 PIL112 PED10 PIL100 PIL111
ELIRC Edge/Level-Triggered Interrupt Priority Register
PED11
PIL110
ELIRD Edge/Level-Triggered Interrupt Priority Register PIL152 PED14 PIL140 PIL151
PED15
PIL150
ELIRE Edge/Level-Triggered Interrupt Priority Register PIL192 PED18 PIL180 PIL181 PIL182 PED17 PIL170 PIL171 PIL172 PIL191 PED16
Type:
PED19
PIL190
Reset
ELIRF Edge/Level-Triggered Interrupt Priority Register PIL232 PED22 PIL220 PIL231
PED23
PIL230
Reset
Bits
Name
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IP13 IP12
PEDxx
1-3, PILxxx 5-7, 9-11, 13-15
IPRA
Interrupt Pending Register
Extended Core Registers
IP15
IP14
Table 6-7. Registers (Continued)
IPRA Descriptions Description Status Inputs 15-0 Level-triggered mode: pending pending Reset: IP27 IPRB Descriptions Description Status Inputs 31-24 Status Input 23-16 Level-triggered mode: pending pending pending acknowledged SC140 core Edge-triggered mode: pending acknowledged SC140 core Settings IP26 IP25 IP24 IP23 IP22 IP21 IP20 IP19 IP18 Type: IP17 Settings Edge-triggered mode: pending acknowledged SC140 core 0x1C38 IP16
IP28 IP29
Registers
Bits
Name
0-15 IP[15-0]
IPRB
Interrupt Pending Register
IP31
IP30
Bits
Name
IP[31-24]
8-15 IP[23-16]
Registers
Table 6-8. Registers
Reset: Depends reset configuration sequence EXDD PLDP Descriptions Description External Mode Single MSC8101 mode Settings 60x-compatible mode ISPS Type: LE29 EPAR 0x10024
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Configuration Register
NPQM
Bits
Name
Table 6-8. Registers (Continued)
Address Phase Delay Pipeline Maximum Depth Enable Address Visibility Zero Specifies number address tenure wait states address operations initiated master.
PLDP
Bank select signals driven address lines full address visibility). Bank select signals driven address (during READ WRITE commands SDRAM devices, full address driven address lines). Strict mode (extended transfer mode disabled) Extended transfer mode enabled Extended transfer mode disabled Extended transfer mode enabled parity
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