System Solutions from Toshiba America Electronic Components, Inc.

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

System Solutions from Toshiba America Electronic Components, Inc.

Datasheet Thumbnail

Top Searches for this datasheet

Compact Flash PowerPC405GP Interface Design Guide
System Solutions from
Toshiba America Electronic Components, Inc.
Atsushi Inoue, Staff MTS, File Memory Business Unit Doug Wong, Staff MTS, File Memory Business Unit
Revision December 2002
Prepared File Memory Business Unit TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. Copyright 2002 Toshiba America Electronic Components, Inc. Rights Reserved.
This "Compact Flash PowerPC 405GP Interface Design Guide" information know-how contains constitute exclusive property Toshiba America Electronic Components, Inc. ("TAEC"), reproduced disclosed others without express prior written permission TAEC. permitted reproductions, whole part, shall bear this notice.
information this "Compact Flash PowerPC 405GP Design Guide' believed reliable; however, reader understands agrees that TAEC MAKES WARRANTY WITH RESPECT THIS DESIGN GUIDE, CONTENTS THEIR ACCURACY, EXCLUDES EXPRESS IMPLIED WARRANTIES, INCLUDING WARRANTIES FITNESS PARTICULAR PURPOSE, MERCHANTABILITY, NON-INFRINGEMENT. reader further understands that solely responsible information contained within, including, limited securing necessary intellectual property rights, however denominated. information this "Compact Flash PowerPC 405GP Design Guide" subject change without prior notice, TAEC's sole discretion. trademarks, trade names, product, and/or brand names property their respective holders.
Table Contents
Introduction Discussion Operating Modes Hardware Notes General Information I.O. Signals Timing Setting EBC0_BnCR Setting EBC0_BnAP Read/Write Timing Schematic Software Notes Conclusion References Datasheets Toshiba Website Contact Information Compact Flash Extender Card
This page left intentionally blank.
Introduction CompactFlashcard small, removable, storage card. Invented SanDisk, specifications determined CompactFlash Association (CFA) (http://www.compactflash.org), non-profit corporation that promotes adoption CompactFlash. CompactFlash used such applications portable desktop computers, digital cameras, handheld data collection scanners, PDAs, Pocket PCs, handy terminals, personal communicators, advanced two-way pagers, audio recorders, monitoring devices, set-top boxes, networking equipment. Every embedded system different. This application note describes possible interface between CompactFlash Card IBM's PowerPC405 microprocessor. With minor variations, interface adapted other microprocessors long Compact Flash will removed added while system Discussion Operating Modes CompactFlash card essentially small form factor card version PCMCIA Card Attachment) specification includes True (Integrated Drive Electronics) mode which compatible with ATA/ATAPI-4 specification. such, there distinct interface modes that CompactFlash card use: Card Memory Mode (uses WE#, access memory locations) Card Mode (uses IOWR#, IORD# access locations) True Mode (uses IOWR#, IORD# access locations)
CompactFlash card essentially solid state disk drive. control disk drive, writes task file registers. values into these task file registers control drive (the ANSI committee defines these registers commands used control ATA/IDE drives http://www.t13.org). These task file registers mapped into either memory address space. Card Memory Mode Card memory mode, task file registers mapped into common memory space (REG# When mapped common memory space, task files appear address: 0h-Fh When REG# card's attribute memory accessed. This where card's configuration registers (card information structure, also known metaformat) stored. contains information about type card inserted used configure system recognize different types cards load correct drivers. Card Mode Card mode, task file registers mapped into address space. There address range options: xx0h-xxFh (contiguous
1F0h-1F7h (primary IDE) 170h-177h (secondary IDE)
value card configuration option register (address 200h attribute memory space) determines whether task files mapped common memory space, ranges. default task files common memory space. True Mode True mode, task file registers also mapped into address space. True mode selected (also called SEL#) grounded host power this mode, neither attribute memory card configuration registers accessible. Only accesses task file registers possible: 0h-7h (main task file registers, CE1# (alternate task file register, CE2# Which Mode Choose? three interface methods, which should choose? your system requires insertion removal (i.e. insertion removal card while system powered), then should have PCMCIA controller your system which will access card both card modes. PCMCIA controller will provide glue logic necessary connect host system CompactFlash card. However, want connect your system directly CompactFlash card without using PCMCIA controller glue logic, then True mode will probably prove easier. main disadvantage that insertion removal will possible because probable disruption signals system bus. main reason will easier True mode because only CE1# needs asserted perform read write data register. order read write Card mode, both CE1# CE2# must asserted simultaneously which generally requires some custom glue logic. Table Task Files (True mode) CE2# CE1# Addr. Read (IORD# Write (IOWR# Data Register bit) Data Register bit) Error Register Feature Register Sector Count Register Sector Count Register Sector Number Register Sector Number Register Cylinder Register Cylinder Register Cylinder High Register Cylinder High Register Drive Head Register Drive Head Register Status Register Command Register Alt. Status Register Device Control Register Drive Address Register Reserved
Since most RTOSes (real time operating systems) such VxWorkshave device drivers ATA/IDE drives, software integration effort significantly reduced. Ideally, only task file base address needs modified typical embedded system. Hardware Notes General Information Please refer Section Schematic While PPC405GP's core runs 2.5V, I/Os 3.3V, which compatible with CompactFlash signals that either 3.3V, suitable physical interface PPC405GP's External Peripheral Controller (EBC) generate required timing TOSHIBA CompactFlash card. this application note, PerCS1# PerCS2# used control CS0# CS1#, other combination PerCSn# should work well. base address, bank usage, width each PerCSn# configured programming Peripheral Bank Configuration Registers (EBC0_BnCR), which will described section "3.4 Setting EBC0_BnCR". PerOE# PerWBE1# chosen control CompactFlash's IORD# IOWR#. PerWE# could also used, this defaults PCIINT# after reset. order select PerWE#, necessary configure CPC0_CR1 [PCIPW] which described this application note (refer page 7-14, Figure PPC405GP User's Manual). timing associated each PerCSn# programmed Peripheral Bank Access Parameter Registers (EBC0_BnAP), which will described section "3.5 Setting EBC0_BnAP". this application note connecting CompactFlash's INTRQ used, therefore pulled with resistor. found that polling status register inefficient, interrupt service routine could implemented such PPC405GP's IRQ0. CompactFlash's RESET# line directly connected power-on reset order guarantee reset card every power RESET# tied port pin, software PPC405GP must remember reset card. Otherwise default state port continuously resetting card. mode handle more than CF/hard disk drive. CSEL# tells master drive slave drive. Theoretically, slave master drive chosen. However, example shown this application note, there only drive, CSEL# connected ground make master drive. Therefore driver just needs address master drive. This convention comes from hard disk drive world. cables actually have master connector slave connector. connectors have CSEL# either connected floating. master connector CSEL# connected ground slave connector CSEL# connected ground. cable selection determines whether drive master drive slave drive.
Power 405GP
Signals Table CompactFlash connection (True mode) Description RESET# resets CS0# card select CS1# card select IORD# read strobe IOWR# write strobe A0-A10 Address 0-10 17,16,15,14, 12,11,10, D0-D15 data bits 0-15 2,3,4,5,6, 47,48, 27,28,29,30,31 INTRQ Interrupt request host Enables True Mode SEL# IOIS16# transfer CSEL# IORDY PDIAG# DASP# CD1#, CD2# VS1#, VS2# INPACK# REG# cable select (master/slave) ready Passed diagnostic drive active/slave present card detect Voltage sense input acknowledge Attribute memory enable write enable Comments Connect system power reset Connect PerCS1# Connect PerCS2# Connect PerOE# Connect PerBE1# Connect A0-A2 PerAddr30, ground A3-A10 Connect PerData15-0 Note: Data CompactFlash. Optional interrupt request host Connect ground connected (host assumes transfer) Connect ground (enable card master) connected connected slave drive) connected slave drive) connected (hot insertion supported) connected connected used True mode (connect Vcc) used True mode (connect Vcc)
Power 405GP
Table 405GP Pins Symbol (413-ball) PerCS1# PerCS2# PerWBE1# PerOE# PerAddr28 PerAddr29 PerAddr30 PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15
(456-ball)
Description Chip Select Chip Select Write Byte Enable Output Enable Address bits Address bits Address bits Data (MSB) Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data (LSB)
Power 405GP
Timing order interface CompactFlash, necessary meet read write timing requirements shown Tables Table 4:True Read Access Timing
Parameter Data delay after IORD Data hold following IORD IORD width time Address setup before IORD Address hold following IORD setup before IORD hold following IORD Symbol Td(IORD) Th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) Unit
Table True Write Access Timing
Parameter Data setup before IOWR Data hold following IOWR IORD width time Address setup before IOWR Address hold following IOWR setup before IOWR hold following IOWR symbol Unit tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR)
order meet these timing requirements, EBC0_BnAP programmed.
Power 405GP
Setting EBC0_BnCR Table contains example values EBC0_BnCR described Figure16-16 from PPC405GP User's Manual (page 16-27) configure PerCSn#. PerCS1#, configuration register EBC0_B1CR needs programmed, PerCS2#, configuration register EBC0_B2CR needs programmed. Table EBC0_BnCR Values
EBC0_BnCR: Figure 16-16, Page 16-27 PPC405GP User's Manual Bits Name Value Description 0:11 xxxxxxxxxxx Base Address Select. boot installed, bank starting address register loaded with value 0xFFE, bank size register loaded with value 0b001(2MB). Please make sure that address range CompactFlash card does overlap with boot other chip selects. 12:14 Bank Address. 000: bank. 15:16 Bank Usage. Read/Write 17:18 Width. 16-bit 19:31 Reserved
Power 405GP
Setting EBC0_BnAP Table contains example values EBC0_BnAP described Figure16-17 from PPC405GP User's Manual (page 16-28) generate required timing Compact Flash. example here shows value 266MHz type PPC405GP (PerClk frequency 66.66MHz), should work 200MHz type well because each PerClk frequency 50MHz. course there other EBC_BnAP values that meet timing required Compact Flash. PerCS1#, configuration register EBC0_B1AP needs programmed, PerCS2#, configuration register EBC0_B2AP needs programmed. Table EBC0_BnAP Values (PerClk output frequency=66.66MHz
EBC0_BnAP: Figure 16-17, Page 16-28 PPC405GP User's Manual Bits Name Value Description Burst Mode Enable. Burst Mode Disabled 00010000 Transfer Wait. 00010000 PerClk First Wait (Unused BME=0) Burst Wait (Unused BME=0) 9:11 Reserved 12:13 Chip Select Timing. Number cycles from peripheral address driven PerCSn# low. PerClk 14:15 Output Enable Timing. Numbers cycles from PerCSn# PerOE# low. PerClk. 16:17 18:19 20:22 27:31 Write Byte Enable Timing. BEM=0, number cycles from PerCSn# PerWBEn# active. PerClk Write Byte Enable Timing. BEM=0 RE=0, number cycles PerWBEn# becomes inactive prior PerCSn# inactive. PerClk Transfer Hold. Contains number hold cycles inserted transfer. PerClk. Ready Enable. PerReady disabled Sample Ready. (Unused RE=0) Byte Enable Mode. PerWBEn# only active write cycles. PerWBEn# controlled only WBF. Parity Enable. Disable parity checking. Reserved
Power 405GP
Read Write Timing Figures show expected read/write timing diagrams created programming example values into EBC0_B1AP EBC0_B2AP. Figure Single Read Transfer Read Cycle (PerClk=66.66MHz)
Each PerClk 15ns PerClk
PerAddr 0:31
CSN=2 TWT=16+1 TH=2
PerCS1# PerCS2#
OEN=3
PerOE#
PerData 0:31
Data
Figure Single Write Transfer Write Cycle (PerClk=66.66MHz)
Each PerClk 15ns PerClk
PerAddr 0:31
CSN=2 TWT=16+1 TH=2
PerCS1# PerCS2#
WBN=3 WBF=1
PerWEB0:3#
PerData 0:31
Data
Power 405GP
Schematic (True Mode)
Power Reset RESET PerCS1# PerCS2# PerOE# PerWBE1# PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerData0 PerData15 CS0# CS1# IORD# IOWR# A3-A10 SEL# CSEL INTRQ PPC405GP Compact Flash
Power 405GP
CompactFlash card connections naming signals assumes little-endian data representation. little-endian system, least significant byte multi-byte scalar value assigned lowest byte address value. big-endian system, most significant byte multibyte scalar value assigned lowest byte address value. naming conventions data bits address lines actually unrelated with endianess, also lead confusion. example, least significant address architecture, PowerPC, most significant address. similar difference exists naming data bits: least significant least significant byte processors; PowerPC, most significant most significant byte.
Power Naming Convention Bits Bits (MSB) 9-14 Most Significant Byte Next Byte Bits Bits (MSB) 30-25 22-17 Common Industry Naming Convention Bits 17-22 Next Byte Bits 14-9 Bits 25-30 (LSB) Least Significant Byte Bits (LSB)
wide transfers, PowerPC will transfer data over bits 0-15 while CompactFlash will transfer data over bits 15-0. keep significance correct avoid byte swapping, physical connection should down shown figure above.
Power 405GP
Software Notes Although could write your driver, most real time operating systems like VxWorksalready provide either driver. driver sends appropriate commands CompactFlash. Ideally, additional driver software needs written; however will necessary change base address from primary port (1F0h) value associated with chip selects. example modifications necessary driver header file (idedrv.h) VxWorksis shown below. original unmodified version immediately follows reference.
Host Address address Comments data register register register register register 10,11 register 12,13 register 14,15 register Word access address (host) results word access address 0(CF) Byte access addresses (3,5,7,etc) results byte access addresses 1,2,3,etc byte address necessary transfer byte D7-D0 Alternatively, modify IDEDRV.C word byte locations even addresses: F0300002,F0300004,.F030000E WE1# connected IOWR# (not WE0#) chip enables required connect CS1# CS2# registers Modified memory-mapped specific system Base1 address F0300000. Base2 address F0700000, higher Both address ranges defined bits wide. CompactFlash devices little endian nomenclature. Big-endian host uses D0(MSB)-D7(LSB) MSByte (for even addresses) D8(MSB)-D15(LSB) LSByte (for addresses). Host Comment access necessary data register. word transfers correct, data bits connected MSB-MSB LSB-LSB: byte transfer D7-D0 card, byte addressing necessary. Since card mapped into host address space, least significant address host (A31), connected. address follows: Host Comment used
Power 405GP
#define IDE_DATA 0xF0300000 #define IDE_ERROR 0xF0300003 #define IDE_PRECOMP 0xF0300003 #define IDE_SECCNT 0xF0300005 #define IDE_SECTOR 0xF0300007 #define IDE_CYL_LO 0xF0300009 #define IDE_CYL_HI 0xF030000B #define IDE_SDH 0xF030000D #define IDE_COMMAND 0xF030000F #define IDE_STATUS 0xF030000F //#define IDE_A_STATUS 0x3f6 #define IDE_D_CONTROL 0xF070000D //#define IDE_D_ADDRESS 0x3f7
(RW) register bits) (R)error register bits) (W)write precompensation bits) (RW) sector count bits) (RW) first sector number(8 bits) (RW) cylinder byte bits) (RW) cylinder high byte bits) (RW) sector size/drive/head bits)*/ command register bits) immediate status bits) alternate status bits)-not used IDEDRV.C disk controller control bits) disk controller address bits)-not used IDEDRV.C*/
Modified register addresses(above)
registers #define #define #define #define #define #define #define #define #define #define #define #define #define IDE_DATA IDE_ERROR IDE_PRECOMP IDE_SECCNT IDE_SECTOR IDE_CYL_LO IDE_CYL_HI IDE_SDH IDE_COMMAND IDE_STATUS IDE_A_STATUS IDE_D_CONTROL IDE_D_ADDRESS 0x1f0 0x1f1 0x1f1 0x1f2 0x1f3 0x1f4 0x1f5 0x1f6 0x1f7 0x1f7 0x3f6 0x3f6 0x3f7 (RW) (RW) (RW) (RW) (RW) (RW) data register bits) error register write precompensation sector count first sector number cylinder byte cylinder high byte sector size/drive/head command register immediate status alternate status disk controller control disk controller address
Unmodified register addresses (x86-based system)(above) Software want take advantage CompactFlash's INTRQ (interrupt request) notify PPC405GP processor when CompactFlash ready. Alternatively, poll busy status register determine when CompactFlash ready.
Power 405GP
Conclusion CompactFlash cards widely available solution systems requiring compact, solid state mass storage system. Because they interpret standard disk drive commands, little software development necessary because software drivers devices already exist most operating systems. Many applications such networking require industrial temperature performance. Compact Flash also available from Toshiba industrial grade making very useful systems that require storage operating temperatures degrees hardware interface each system need customized, indicated example presented, chipset already possess capability interface gluelessly CompactFlash. PCMCIA controller present system, will easier interface using True mode (assuming insertion removal requirement).
References Datasheets THNCFxxxxBA/MBAI Series Compact Flash Card datasheet 05/25/2002 THNCFxxxxMA Series Compact Flash Card datasheet 06/24/2002 PowerPC 405GP Embedded Processor Data Sheet PowerPC 405GP Embedded Processor User's Manual Toshiba Website http://www.toshiba.com/taec/ Contact Information Toshiba welcomes your feedback this document. Please send comments ideas TAEC eSupport
Tech.Questions@taec.toshiba.com
Compact Flash Extender Card This allows access pins card. Useful prototyping testing http://www.sycard.com
Power 405GP

System Solutions from Toshiba America Electronic Components, Inc.

Top Searches for this datasheet

Other recent searches