design rule checks DECIMATEis that output rate must greater than times

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design rule checks DECIMATEis that output rate must greater than times

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HSP43220 Design Filters With Output Rates (Passband Transition)
design rule checks DECIMATEis that output rate must greater than times passband transition band. informed user, violation this rule valid design choice. Suppression this rule check DECIMATE possible, design such filter using DECIMATE possible. general solution DECIMATE design filter with output rate that twice desired rate, integer multiple desired rate that >2(pass trans). Outside Design Module decimation rate increase factor needed achieve desired output rate. filter response obtained graphically. Consider filter with passband 70kHz transition band 60kHz. desired output rate 200kHz. DECIMATE requires output rate >260kHz, output rate 400kHz chosen (see Figure below FILTER page increasing decimation factor folding point (fS/2) moved desired output rate obtained. filter response generated graphically. aliasing component represented dotted line (see Figure below).
Notice FILTER stopband attenuation limited 40dB (FIR_CK=CK_IN). Because decimation increased from there more taps available with FIR_CK=20MHz. Using Equation from 43220 Data Sheet, many taps available.
therefore, FILTER which uses taps 96dB stopband. part will course programmed decimation rate FIR_CK 20MHz used. correctly simulate generate PROM files "new filter" *.DAR file must edited. corrected value FDRATE line column entered. correct output rate FIR_CK rate entered next last last line *.DAR file. above procedure works standard Precomp FIR. Remember maximum3- decimation rate
70kHz 130kHz 200kHz
70kHz 200kHz 130kHz
FIGURE
FIGURE
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Intersil Design trademark Intersil Corporation. Copyright Intersil Corporation 2000 DECIMATEis trademark Intersil Corporation.
Tech Brief
DESIGN MODULE
SIMULATOR MODULE HSP43220 FILTER SPECIFICATION
PROM MODULE
FILTER FILE INPUT SAMPLE RATE OUTPUT RATE PASSBAND TRANSITION BAND PASSBAND ATTEN STOPBAND ATTEN
filter1.DDF 20MHz 400MHz 70MHz 60MHz 0.1dB 40dB DESIGN MODE GENERATE REPORT DISPLAY RESPONSE SAVE FREQ RESPONSES SAVE RESPONSE AUTO
ORDER DECIMATION SCALE FACTOR 0.78125 INPUT RATE CLOCK (MIN) ORDER DECIMATION 2MHz 20MHz TYPE STANDARD
FIGURE FILTER DESIGN USING STANDARD TECHNIQUE
DESIGN MODULE
SIMULATOR MODULE HSP43220 FILTER SPECIFICATION
PROM MODULE
FILTER FILE INPUT SAMPLE RATE OUTPUT RATE PASSBAND TRANSITION BAND PASSBAND ATTEN STOPBAND ATTEN
filter2.DDF 20MHz 400MHz 70MHz 60MHz 0.1dB 96dB DESIGN MODE GENERATE REPORT DISPLAY RESPONSE SAVE FREQ RESPONSES SAVE RESPONSE AUTO
ORDER DECIMATION SCALE FACTOR 0.61035 INPUT RATE CLOCK (MIN) ORDER DECIMATION 2MHz 40MHz TYPE STANDARD
FIGURE FILTER DESIGN DISREGARDING CLOCK (MIN)
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design rule checks DECIMATEis that output rate must greater than times

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