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DAC707 DAC708 DAC709

Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS

DAC707 DAC708 DAC709
Microprocessor-Compatible 16-BIT DIGITAL-TO-ANALOG CONVERTERS
FEATURES
DESCRIPTION
8-Bit (DAC708, 709) or 16-Bit (DAC707) Serial Data Low Byte Latch High Byte Latch D / A Latch Reference Circuit 16-Bit D / A Converter Bipolar Offset
Summing Junction (708, 709) 10V Range (708, 709)
Serial (DAC708, 709)
Latch Enables / Mode Select CLEAR WRITE CHIP SELECT
Control Logic
DAC707 or DAC709 Only
DAC707 / 708 / 709 Block Diagram
International Airport Industrial Park · Mailing Address: PO Box 11400, Tucson, AZ 85734 · Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 · Tel: (520) 746-1111 · Twx: 910-952-1111 Internet: http://www.burr-brown.com / · FAXLine: (800) 548-6133 (US / Canada Only) · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132
PDS-557H
SBAS145
SPECIFICATIONS
ELECTRICAL
Unipolar Straight Binary
DAC707 / 708 / 709
ELECTRICAL (CONT)
PACKAGE INFORMATION
PRODUCT DAC707JP DAC707KP DAC707BH DAC707KH DAC707SH DAC708BH DAC708KH DAC708SH DAC709BH DAC709KH DAC709SH PACKAGE 28-Pin Plastic DBL Wide DIP 28-Pin Plastic DBL Wide DIP 28LD Side Brazed Hermetic Dip 28LD Side Brazed Hermetic DIP 28LD Side Brazed Hermetic DIP 24LD Side Brazed Hermetic DIP 24LD Side Brazed Hermetic DIP 24LD Side Brazed Hermetic DIP 24LD Side Brazed Hermetic DIP 24LD Side Brazed Hermetic DIP 24LD Side Brazed Hermetic DIP PACKAGE DRAWING NUMBER(1) 215 215 149 149 149 165 165 165 165 165 165
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
DAC707 / 708 / 709
ORDERING INFORMATION
CONNECTION DIAGRAMS
DAC708 / 709 A2 Register Enable Lines A0 A1 D7 (D15) D6 (D14) D5 (D13) Data Inputs D4 (D12) D3 (D11) D2 (D10) D1 (D9) D0 (D8) / S1 DCOM VDD CS WR CLR -VCC +VCC GA
1 2 3 4 5 6 7 8 9 10 11 12 DAC709 Only Low Byte Latch High Byte Latch D / A Latch
24 23 22 21 16-Bit Reference Circuit Ladder Resistor Network and Current Switches 20 19 18 17 16 15 14 10k 10k 13
+ Control Lines
VDD NOTES: (1) Potentiometer is 10k to 100k . (2) Decoupling capcitors are 0.1µF to 1.0µF. -VCC
270k + Gain Adjust 3.9M
+VCC +
BPO SJ ACOM VOUT R F2
Offset Adjust Connect for bipolar operation. Connect for 10V range. Leave pin 13 open for 20V range.
DAC707 VDD
V OUT V DD DCOM ACOM
Input Latch
28 D0 (LSB) RF 27 D1 26 D2 25 D3 24 D4 23 D5 22 D6 21 D7 16-Bit Ladder Resistor Network and Current Switches 20 D8 19 D9 18 D10 17 D11 16 D12 15 D13 Digital Inputs
Digital Common
Analog Common Offset Adjust
3.9M 270k
Gain Adjust
CLR Control Lines WR A1 Latch Enable Lines A0 (MSB) D15 Digital Inputs NOTES: (1) Potentiometers are 10k to 100k . (2) Decoupling capcitors are 0.1µF to 1.0µF. (3) Bypass, 0.0022µF to 0.01µF. D14
DAC707 / 708 / 709
DESCRIPTION OF PIN FUNCTIONS
Digital common
ACOM SJ
Analog common Summing junction of the internal output op amp for the DAC707. Offset adjust circuit is connected to the summing junction of the output amplifier. Refer to Block Diagram. Gain adjust pin. Refer to Connection Diagram for gain adjust circuit. Positive supply voltage (+15V) Negative supply voltage (-15V) Clear line. Sets the input latch to zero and sets the D / A latch to the input code that gives bipolar zero on the D / A output (Active low) Write control line (Active low) Enable for D / A converter latch (Active low) Enable for input latch (Active low) Data bit 15 (Most Significant Bit)
D7 (D15) D6 (D14)
GA +VCC -VCC CLR
D5 (D13) D4 (D12) D3 (D11) D2 (D10)
Data bit 5 (LB) or data bit 13 (HB) Data bit 4 (LB) or data bit 12 (HB) Data bit 3 (LB) or data bit 11 (HB) Data bit 2 (LB) or data bit 10 (HB)
WR A1 A0 D15 (MSB)
D1 (D9) D0 (D8) / SI DCOM RF2
Data bit 1 (LB) or data bit 9 (HB) Data bit 0 (LB) or data bit 8 (HB). Serial input when serial mode is selected. Digital common Feedback resistor for internal or external operational amplifier. Connect to pin 14 when a 10V output range is desired. Leave open for a 20V output range. Voltage output for DAC709 or feedback resistor for use with an external output op amp for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. Analog common Summing junction of the internal output op amp for the DAC709, or the current output for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. Bipolar offset. Connect to pin 16 when operating in the bipolar mode. Leave open for unipolar mode. Gain adjust pin Positive supply voltage (+15V) Negative supply voltage (-15V) Clear line. Sets the high and low byte input registers to zero and, for bipolar operation, sets the D / A register to the input code that gives bipolar zero on the D / A output. (In the unipolar mode, invert the MSB prior to the D / A.) Write control line Chip select control line Logic supply (+5V)
Data bit 14
VOUT RF1 (DAC708)
D13 D12
Data bit 13 Data bit 12
ACOM SJ (DAC709) IOUT (DAC708)
D11 D10 D9 D8 D7
Data bit 11 Data bit 10 Data bit 9 Data bit 8 Data bit 7
BPO GA +VCC -VCC CLR
D6 D5 D4 D3 D2 D1 D0 (LSB)
Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 (Least Significant Bit)
WR CS VDD No pin No pin No pin No pin
(The DAC708 and DAC709 are in 24-pin packages)
DAC707 / 708 / 709
DISCUSSION OF SPECIFICATIONS
the MSB must be inverted). This code corresponds to zero volts (DAC707 and DAC709) or zero milliamps (DAC708) at the analog output. The maximum change in offset at tMIN or tMAX is referenced to the zero error at +25°C and is divided by the temperature change. This drift is expressed in FSR / °C. SETTLING TIME Settling time of the D / A is the total time required for the analog output to settle within an error band around its final value after a change in digital input. Refer to Figure 1 for typical values for this family of products.
NOTES: (1) MSB must be inverted externally. (2) Assumes MSB is inverted externally.
0.001 0.01 0.1 Settling Time (µs) 1 10
DAC707 / 708 / 709
output. It is defined as a percent of FSR change in the output per percent of change in either the positive supply (+VCC), negative supply (-VCC) or logic supply (VDD) about the nominal power supply voltages (see Figure 2). It is specified for DC or low frequency changes. The typical performance curve in Figure 2 shows the effect of high frequency changes in power supply voltages.
Zero Adjustment For unipolar (USB) configurations, apply the digital input code that produces zero voltage or zero current output and adjust the zero potentiometer for zero output. For bipolar (BTC) configurations, apply the digital input code that produces zero output voltage or current. See Table II for corresponding codes and connection diagrams for zero adjustments circuit connections. Zero calibration should be made before gain calibration. Gain Adjustment Apply the digital input that gives the maximum positive output voltage. Adjust the gain potentiometer for this positive full-scale voltage. See Table II for positive full-scale voltages and the Connection Diagrams for gain adjustment circuit connections.
0.030 0.025 -15V Supply 0.020 0.015 0.010 0.005 0 1 10 100 1k 10k 100k +5V Supply +15V Supply
Range of Gain Adjust + Full Scale 1LSB
Power Supply Ripple Frequency (Hz)
Full Scale Range
FIGURE 2. Power Supply Rejection Versus Power Supply Ripple Frequency.
Analog Output
Gain Adjust Rotates the Line
OPERATING INSTRUCTIONS
Range of Zero Adjust
Digital Input Zero Adjust Translates the Line
FIGURE 4. Relationship of Zero and Gain Adjustments for Unipolar D / A Converters, DAC708 and DAC709.
Range of Gain Adjust
Analog Output
Offset Adjust Translates the Line Range and Offset Adjust
- Full Scale
Digital Input
FIGURE 3. Equivalent Resistances.
FIGURE 5. Relationship of Zero and Gain Adjustments for Bipolar D / A Converters, DAC707 and DAC708 / 709
DAC707 / 708 / 709
NOTE: (1) MSB assumed to be inverted externally.
TABLE II. Digital Input and Analog Output Voltage / Current Relationships. INTERFACE LOGIC AND TIMING DAC708 / 709 The signals CHIP SELECT (CS), WRITE (WR), register enables (A0, A1, and A2) and CLEAR (CLR), provide the control functions for the microprocessor interface. They are all active in the "low" or logic "0" state. CS must be low to access any of the registers. A0 and A1 steer the input 8-bit data byte to the low- or high-byte input latch respectively. A2 gates the contents of the two input latches through to the D / A latch in parallel. The contents are then applied to the input of the D / A converter. When WR goes low, data is strobed into the latch or latches which have been enabled. The serial input mode is activated when both A0 and A1 are logic "0" simultaneously. The D0 (D8) / SI input data line accepts the serial data MSB first. Each bit is clocked in by a WR pulse. Data is strobed through to the D / A latch by A2 going to logic "0" the same as in the parallel input mode. Each of the latches can be made "transparent" by maintaining its enable signal at logic "0". However, as stated above, when both A0 and A1 are logic "0" at the same time, the serial mode is selected. The CLR line resets both input latches to all zeros and sets the D / A latch to 0000H. This is the binary code that gives a null, or zero, at the output of the D / A in the bipolar mode. In the unipolar mode, activating CLR will cause the output to go to one-half of full scale. The maximum clock rate of the latches is 10MHz. The minimum time between write (WR) pulses for successive enables is 20ns. In the serial input mode (DAC708 and DAC709), the maximum rate at which data can be clocked into the input shift register is 10MHz. The timing of the control signals is given in Figure 6. DAC707 The DAC707 interface timing is the same as that described above except instead of two 8-bit separately-enabled input latches, it has a single 16-bit input latch enabled by A0. The
LOGIC TIMING - Parallel or Serial Data Input Over Temperature ns, min ns, max TDW Data valid to end of WR 80 TCW CS valid to end of WR 80 TAW A0, A1, A2 valid to end of WR 80 TWP Write pulse width 80 TDH Data hold after end of WR 0
TIMING DIAGRAM tCW CS tAW A0, A1, A2 tDW D0-D15, SI tDH WR tWP
FIGURE 6. Logic Timing Diagram. D / A latch is enabled by A1. Also, there is no serial-input mode and no CHIP SELECT (CS) line.
INSTALLATION CONSIDERATIONS
Due to the extremely-high accuracy of the D / A converter, system design problems such as grounding and contact resistance become very important. For a 16-bit converter with a +10V full-scale range, 1LSB is 153µV. With a load current of 5mA, series wiring and connector resistance of only 30m will cause the output to be in error by 1LSB. To understand what this means in terms of a system layout, the resistance of typical 1 ounce copper-clad printed circuit board material is approximately 1 / 2m per square. In the example above, a 10 milliinch-wide conductor 60 milliinches long would cause a 1LSB error.
DAC707 / 708 / 709
DAC707 / 709
RF MicroProcessor Interface
In Figures 7 and 8, lead and contact resistances are represented by R1 through R5. As long as the load resistance RL is constant, R2 simply introduces a gain error and can be removed with gain calibration. R3 is part of RL if the output voltage is sensed at ANALOG COMMON.
Sense Output
Alternate Ground Sense Connection R4 1µF 1µF System Ground + + +VCC Analog Common -VCC Digital Common 1µF + VDD VDD Supply
Figures 8 and 9 show two methods of connecting the current output model with an external precision output op amp. By sensing the output voltage at the load resistor (connecting RF to the output of the amplifier at RL) the effect of R1 and R2 is greatly reduced. R1 will cause a gain error but is independent of the value of RL and can be eliminated by initial calibration adjustments. The effect of R2 is negligible because it is inside the feedback loop of the output op amp and is therefore greatly reduced by the loop gain. In many applications it is impractical to sense the output voltage at ANALOG COMMON. Sensing the output voltage at the system ground point is permissible because these converters have separate analog and digital common lines and the analog return current is a near-constant 2mA and varies by only 10µA to 20µA over the entire input code range. R4 can be as large as 3 without adversely affecting the linearity of the D / A converter. The voltage drop across R4 is constant and appears as a zero error that can be nulled with the zero calibration adjustment. Another approach senses the output at the load as shown in Figure 9. In this circuit the output voltage is sensed at the load common and not at the D / A converter common as in the previous circuits. The value of R6 and R7 must be adjusted for maximum common-mode rejection across RL. The effect of R4 is negligible as explained previously. The D / A converter and the wiring to its connectors should be located to provide optimum isolation from sources of RFI and EMI. The key to elimination of RF radiation or pickup is small loop area. Signal leads and their return conductors should be kept close together such that they present a small flux-capture cross section for any external field.
FIGURE 7. DAC707 / 709 Bipolar Output Circuit (Voltage Out).
DAC708 R1 RF1 RF MicroProcessor Interface 10k IOUT R2 RB RL
2.45k
DAC708
Digital Common Analog Common Sense Output R3 Alternate Ground Sense Connection R4 1µF 1µF System Ground + + +VCC Analog Common -VCC Digital Common 1µF + VDD VDD Supply
RF R2 RDAC R6 R7 R5 RL Sense Output
To System Ground
FIGURE 9. Alternate Connection for Ground Sensing at the Load (Current Output Models).
FIGURE 8. DAC708 Bipolar Output Circuit (with External Op Amp).
DAC707 / 708 / 709
BURN-IN SCREENING Burn-in screening is an option available for the DAC707. Burn-in duration is 160 hours at the temperature shown below (or equivalent combination of time and temperature). Product Temp. Range Burn-In Screening DAC707JP-BI 0°C to 70°C 100°C DAC707KP-BI 0°C to 70°C 100°C DAC707KH-BI -25°C to +85°C 125°C DAC707BH-BI -25°C to +85°C 125°C DAC707SH-BI -55°C to +125°C 125°C All units are tested after burn-in to ensure that grade specifications are met.
signal lines need to be isolated. The data is applied to pin 11 in a serial bit stream, MSB first. The WR input is used as a data strobe, clocking in each data bit. A RESET signal is provided for system startup and reset. These three signals are each optically isolated. Once the 16 bits of serial data have been strobed into the input register pair, the data is strobed through to the D / A register by the "carry" signal out of a 4-bit binary synchronous counter that has counted the 16 WR pulses used to clock in the data. The circuit diagram is given in Figure 10. CONNECTING MULTIPLE DAC707s TO A 16-BIT MICROPROCESSOR BUS Figure 11 illustrates the method of connecting multiple DAC707s to a 16-bit microprocessor bus. The circuit shown has two DAC707s and uses only one address line to select either the input register or the D / A register. An external address decoder selects the desired converter.
APPLICATIONS
LOADING THE DAC709 SERIALLY ACROSS AN ISOLATION BARRIER A very useful application of the DAC709 is in achieving low-cost isolation that preserves high accuracy. Using the serial input feature of the input register pair, only three
DAC707 / 708 / 709
74LS161A VDD Carry Out QA ENT QB ENP QC Load QD A B In C CLR CK D
Synchronous Binary Counter 0.001µF No Connection 2.2k
+5V 1 / 4 74LS00
VDD 330
VDD 2.2k TIL117 A 2 A1 A0 CS WR Analog Output
DATA STROBE 1 / 6 7407 VDD 330 VDD 2.2k
CLR DAC708 or DAC709 DO
Serial Input (16-Bit Data Stream) 1 / 6 7407
1 / 4 74LS00
+ 1 / 4 74LS00 VDD 330 VDD 2.2k 10k +
VDD ACOM DCOM -VCC +VCC
RESET 1 / 6 7407 + Power Supply Voltage - Isolated Power Supply VDD
+ 2.2µF
Isolation Barrier DATA STROBE Serial Input A2 Analog Output 1 2 3 4
FIGURE 10. Serial Loading of Electrically Isolated DAC708 / 709.
WR D16 16-Bit Data Bus D0 A0 µP A15 16-Bit Address Bus Base Address Decoder CS1 A1 WR DAC707
VOUT 1
A0 CS2 A1
WR DAC707
VOUT 2
FIGURE 11. Connecting Multiple DAC707s to a 16-Bit Microprocessor.
DAC707 / 708 / 709
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device DAC707JP DAC707JP-BI DAC707KP DAC707KP-7 DAC707KP-BI DAC709KH DAC709KH-2
Status (1) NRND OBSOLETE NRND OBSOLETE OBSOLETE OBSOLETE OBSOLETE
Package Type PDIP PDIP PDIP PDIP PDIP CDIP SB CDIP SB
Package Drawing NTD NTD NTD NTD NTD JDM JDM
Pins Package Eco Plan (2) Qty 28 28 28 28 28 24 24 13 13 TBD TBD TBD TBD TBD TBD TBD
Lead / Ball Finish CU SNPB Call TI CU SNPB Call TI Call TI Call TI Call TI
MSL Peak Temp (3) N / A for Pkg Type Call TI N / A for Pkg Type Call TI Call TI Call TI Call TI
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
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