32-Bit Bus-Watch EDAC Error Detection Correction unit Description

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32-Bit Bus-Watch EDAC Error Detection Correction unit Description

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29C532E
32-Bit Bus-Watch EDAC Error Detection Correction unit
Description
29C532E EDAC very power bus-watch 32-bit Error Detection Correction unit (EDAC). EDAC used high integrity system monitoring correcting data values coming from memory space. Such bus-watch EDAC connected peripheral data watches controls integrity data memory. During processor write cycle, each memory location (32-bit width), EDAC calculated checkword 8-bit width) added. When performing read operation from memory, 29C532E verifies entire checkword data combination. detects correct 100% single-bit errors detects multi-bit errors correct them. errors reported master system allow processor take action required. case single-bit error, Correctable ERRor flag single-bit error complemented (corrected). Then, data substituted corrupted data system data bus. case multi-bit error, Non-Correctable ERRor flag set, data repaired. Note that when multi-bit errors occur, there some patterns which appear possible correctable errors. Therefore, environment produces this type error, EDAC must used detect-only-without-correction configuration. Data syndrome analysis must rapidly done. Because 29C532E latches data, byte 16-bit word write operations possible they take place read-modify-write accesses memory space. When 29C532E uses 7-checkbit, detect errors single 4-bit memory chip. 8-checkbit option gives additional capability detect errors 8-bit memory chip.
Features
32-bit Operation Check Bits) Watch Architecture Fast Error Detection: Fast Error Correction: Corrects Single-Bit Errors Detects Double-Bit Errors Detects Some Multi-Bit Errors Detects Chip Error (x1, Format)
Correctable Non-Correctable Error Flags Very Power CMOS Compatible Single Power Supply High Drive Capability Bus: 12.8 100-Pin Multi-Layer Quad Flatpack
Rev. February, 1997
Preliminary Information
29C532E
Interface
3.1. Block Diagram
SYNCHK CORRECT OLE/CHK
[3.0]
Data-Out LATCH
[7.0]
[31.24] [23.16]
BUFFER
CHECKBIT GENERATOR
Data
[31.0]
[15.8] [7.0]
Data-In LATCH
[31.0] [7.0]
SYNDROME GENERATOR
CONTROL Chk-In LATCH
BUFFER
Checkbit
[7.0] [7.0]
[7.0]
Diagnosis LATCH
[7.0] [31.0]
SYNDROME DECODER
[7.0]
DIAG [1.0] CERR NCERR
Rev. February, 1997
Preliminary Information
29C532E
3.2. Configuration
SYNCHK
VccB DIAG DIAG GndC GndB [31] [30] [29] [28] VccB [27] [26] [25] (n.c) (n.c)
Index Corner
(n.c)
(n.c) GndB (n.c) (n.c) (n.c) (n.c) (n.c) CORRECT VccB GndB [10] (n.c) (n.c) (n.c) (n.c) (n.c) (n.c) (n.c) VccB
29C532E
(Top View)
(n.c) (n.c) (n.c) (n.c) (n.c) (n.c) [24] GndB [23] [22] [21] [20] VccB [19] [18] [17] [16] GndB OLE/CHK VccB CERR NCERR (n.c) (n.c) VccC (n.c) (n.c)
(n.c) [11] [12] [13] [14] GndB [15] VccB GndB (n.c) (n.c)
Rev. February, 1997
Preliminary Information
29C532E
3.3. Description
Name Buses
[31.24] [23.16] [15.8] [7.0] [7.0] Checkbit bus. Output checkbit [7.0] controlled COE. Data bus. Output data [31.24] controlled [3]. Output data [23.16] controlled [2]. Output data [15.8] controlled [1]. Output data [7.0] controlled [0].
Active
Description
Flags
CERR NCERR Correctable ERror. UnCorrectable ERror.
Controls
Data Output Enable [15.8] bus. Data Output Enable [7.0] bus. Checkbit Output Enable [7.0] bus. OLE/CHK CHecKbit enable. Only DIAG (non active): [7.0] [7.0]. [7.0] [7.0]. Output Latch Enable [31.0] internal bus: transparent, latched. Data Output Enable [31.24] bus. Data Output Enable [23.16] bus.
High
Input Latch Enable produce [31.0] [7.0] internal buses respectively from [31.0] [7.0]: transparent, latched. Diagnosis Latch Enable produce [7.0] internal from [7.0] bus: transparent, latched.
High
Rev. February, 1997
Preliminary Information
29C532E
Name Controls
SYNdrome CHecKbit enable. During read mode: [31.24] [7.0], [23.16] [7.0], SYNCHK [15.8] [7.0],
Active
Description
[7.0] [7.0]. [31.0] [31.0]. CORRECT High CORRECTion enable. Only SYNCHK (non active): [31.0] [31.0]. [31.0] [31.0]. Code leNgth equals EDAC uses check bits. EDAC uses check bits. DIAGnosis mode Diagnosis detect correct: [7.0] [7.0]. [7.0] [7.0]. DIAG High DIAGnosis mode Diagnosis generate: [7.0] [7.0]. [7.0] [7.0] [7.0] following OLE/CHK value.
High
DIAG
Power (Buffers)
VccB GndB Buffers supply nominal) Buffers reference
Power (Core)
VccC GndC Core supply nominal) Core reference
buffers have pull-up resistor
Rev. February, 1997
Preliminary Information
29C532E
Checkbit Generation
checkbit generator produces checkbits (whatever value) from incoming data [31.0] according following table.
Table Checkbit generation indicates [31.0] used parity calculation)
[31.0] Parity [7.0] Even
(XOR)
Even
(XOR)
(NXOR)
Even
(XOR)
(NXOR)
Even
(XOR)
Even
(XOR)
(NXOR)
Example create [3], [31.0] 3ORed together.If SRAM devices 4-bit used memory system controlled 29C532E EDAC, only necessary
store bits [31.0] [6.0]).If SRAM devices 8-bit used memory system controlled 29C532E EDAC, bits [31.0] [7.0]) must stored.
Rev. February, 1997
Preliminary Information
29C532E
Syndrome Generation
syndrome generator produces syndrome-bits (whatever value) from incoming data [31.0] associated checkbit [7.0] (via [7.0] [7.0] following DIAG value) according following table.
Table Checkbit generation indicates [x1.0] used parity calculation)
[x1.0] [7.0] Parity
Even
(XOR)
Even
(XOR)
(NXOR)
Even
(XOR)
(NXOR)
Even
(XOR)
Even
(XOR)
(NXOR)
Rev. February, 1997
Preliminary Information
29C532E
Table (continue)
[7.0]
[x1.0] Parity
[7.0] Parity
Even
(XOR)
(XOR)
Even
(XOR)
Even
(XOR)
(NXOR)
Even
(XOR)
Even
(XOR)
Even
(XOR)
(NXOR)
Even
(XOR)
Even
(XOR)
Even
(XOR)
Even
(XOR)
Even
(XOR)
(NXOR)
Even
(XOR)
syndrome SY[x] received checkbit RCB[x] parity calculation [31.0]. Example: create [1], [31.0] NXORed together. Then, result XORed with associated checkbit checkbit byte read same address than data word [31.0]. SRAM devices 4-bit used memory system controlled 29C532E EDAC, only bits [31.0] [6.0]) checked generated syndrome word 7-bit width. SRAM devices 8-bit used memory system controlled 29C532E EDAC, bits [31.0] [7.0]) checked, generated syndrome word 8-bit width.
Syndrome Decoding
syndrome decoder generates error flags CERR (Correctable ERror) NCERR (Non-Correctable ERror). mainly provides corrected data word system correctable error occurs. case single bit-error, using syndrome value, this block decodes which error complements correct data word. This correction only made bits data checkbit word. inputs syndrome decoder are:
bits data coming from system data bus, syndrome coming from syndrome generator, control signal N39. signal controls bits will decoded from entire word.
Rev. February, 1997
Preliminary Information
29C532E
Table 7-bit syndrome word bit-in-error (N39=1)
Syndrome [7.0]
D[4] D[8] D[15] D[14] D[10] D[12] D[13] D[9] D[22] D[19] D[31] D[7] D[30] D[0] D[27] D[23] D[3] D[5] D[6] N.E.D D[24] D[20] D[26] D[1] D[16] D[21] D[25] D[28] D[2] D[18] D[29] D[17] D[11]
Note:
N.E.D
Error Detected, Data bit-in-error, Check bit-in-error Multi-bit-in-error
Rev. February, 1997
Preliminary Information
29C532E
Table 8-bit syndrome word bit-in-error (N39=0)
Syndrome D[4] D[8] D[15] D[10] D[19] D[31] D[13] D[9] D[30] D[14] D[22] D[12] D[7] D[23] D[0] D[27] D[3] D[5] D[6] N.E.D D[20] D[28] D[18] D[24] D[26] D[1] D[16] D[2] D[29] D[21] D[25] D[17] D[11]
[7.0]
Note
N.E.D
Error Detected, Data bit-in-error, Check bit-in-error Multi-bit-in-error
Rev. February, 1997
Preliminary Information
29C532E
7-Bit Syndrome Word
This feature available when driven high level.
7.1. Error
there error read data checkbit, syndrome word "00". EDAC flags inactive.
Error 0x00
7.2. Single Bit-In-Error
When Memory Data word [31.0] C[6.0]) read bit-in-error, 20C532E EDAC develops code (syndrome) which indicates error (each have syndrome value). this case, syndrome decoder sets correctable error flag CERR, NCERR flag remains high level. case single bit-error [31.0], control lines SYNCHK active CORRECT active, Table 7-bit syndrome word single bit-error.
D[31.16] 0x6D 0x5B 0x51 0x4x 0x58 0x34 0x32 0x13 0x68 0x4C 0x31 0x23 0x5D 0x64 0x52 0x46
corrected value (CDO [31.0]) available [31.0] internal syndrome word available [6.0]. corrected value obtains complement bit-in-error. same conditions, single bit-error occurs [6.0], corrected value checkbit available device.
D[15.0]
0x4F
0x2C
0x2A
0x1A
0x60
0x3D
0x3B
0x2F
0x4A
0x26
0x25
0x1F
0x16
0x54
0x45
0x38
C[7.0]
0x40
0x20
0x10
0x08
0x04
0x02
0x01
7.3. Double Bit-In-Error
When Memory Data word [31.0] C[6.0]) read bit-in-error, 20C532E EDAC develops syndrome different 0x00. syndrome value generated double bit-in-error never takes place syndrome value generated single bit-in-error. this case, syndrome decoder sets correctable error flag NCERR CERR flag remains high level. Example data [12] incorrect, syndrome (SY= 0x21), NCERR flag (CERR flag remains high level).
7.4. Triple Bit-In-Error
When Memory Data word [31.0] C[6.0]) read three bit-in-error, 20C532E EDAC develops syndrome different 0x00. syndrome value Rev. February, 1997 generated triple bit-in-error have value, even syndrome value normally generated single
Preliminary Information
29C532E
bit-in-error. NCERR flag CERR flag activated following value generated syndrome. Example data [28], [18] incorrect, syndrome [6], (SY= 0x62), NCERR flag (CERR flag remains high level). Fault example data [24], [12] incorrect, syndrome bits [4.0] (SY= 0x1F). syndrome decoded 29C532E EDAC being correctable error [4]. Then, CERR flag NCERR flag remains high level. correction would cause more errors.
7.5. Multi Bit-In-Error
When Memory Data word [31.0] C[6.0]) read four more bit-in-error, 20C532E EDAC develops controlled syndrome. This syndrome take value, from 0x00 Error Detected) specific syndrome value single bit-in-error Example data read 0x00000000 instead 0xFFFFFFFF, generated syndrome 0x00. Then, error flag actived.
7.6. 4-Bit Wide Memory Error
checkbit code used provide error detection four errors occuring following fields:
[31.28], [27.24], [23.20], [19.16], [15.12], [11.8], [7.4], [3.0], [6.4], [3.0].
29C532E EDAC flag number errors 4-bit wide memory chip. device returns from four bit-in error, CERR NCERR flags generated following error type generated syndrome takes value which never overlaps code single bit-in-error. This restriction triple multi bit-in-error. Example device controlling [23.20] generates error, possible codes different 0x00 those describing single bit-in-error.
error
0x24
0x59
0x4B
0x7D
0x67
0x12
0x15
0x07
0x00
0x7A
0x36
CERR NCERR
0x68
0x4C
0x31
0x23
8-Bit Syndrome Word
This feature available when driven level.
8.1. Error
there error read data checkbit, syndrome word "00". EDAC flags inactive.
Error 0x00
Rev. February, 1997
Preliminary Information
29C532E
8.2. Single Bit-In-Error
When Memory Data word [31.0] C[7.0]) read bit-in-error, 20C532E EDAC develops code (syndrome) which indicates error (each have syndrome value). this case, syndrome decoder sets correctable error flag CERR, NCERR flag remains high level. case single bit-error [31.0], control lines SYNCHK active CORRECT active, Table 8-bit syndrome word single bit-error. corrected value (CDO [31.0]) available [31.0] internal syndrome word available [7.0]. corrected value obtains complement bit-in-error. same conditions, single bit-error occurs [7.0], corrected value checkbit available device.
D[31.16]
0x6D
0x5B
0x51
0x43
0xD8
0xB4
0xB2
0x93
0x68
0xCC
0xB1
0x23
0x5D
0x64
0xD2
0xC6
D[15.0]
0x4F
0x9A
0xE0
0x3D
0x3B
0x2F
0x25
0x1F
0x16
0x54
0xC5
0xB8
0xAC 0x2A
0xCA 0xA6
C[7.0]
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
8.3. Double Bit-In-Error
When Memory Data word [31.0] C[7.0]) read bit-in-error, 20C532E EDAC develops syndrome different 0x00. syndrome value generated double bit-in-error never takes place syndrome value generated single bit-in-error. this case, syndrome decoder sets correctable error flag NCERR CERR flag remains high level. Example: data [24] incorrect, syndrome (SY= 0x85), NCERR flag (CERR flag remains high level).
8.4. Triple Bit-In-Error
When Memory Data word [31.0] C[7.0]) read three bit-in-error, 20C532E EDAC develops syndrome different 0x00. syndrome value generated triple bit-in-error have value, even syndrome value normally generated single bit-in-error. NCERR flag CERR flag activated following value generated syndrome. Example data [25], [20] incorrect, syndrome (SY= 0x37), NCERR flag (CERR flag remains high level). Fault example: data [30], [15] incorrect, syndrome bits (SY= 0xAC). syndrome decoded 29C532E EDAC being correctable error [14]. Then, CERR flag NCERR flag remains high level. correction would cause more errors.
8.5. Multi Bit-In-Error
When Memory Data word [31.0] C[7.0]) read four more bit-in-error, 20C532E EDAC develops controlled syndrome. This syndrome take value, from 0x00 Error Detected) specific syndrome value single bit-in-error Rev. February, 1997 Example: data read 0x00000000 instead 0xFFFFFFFF, generated syndrome 0x00. Then, error flag actived.
Preliminary Information
29C532E
8.6. 4-Bit Wide Memory Error
checkbit code used provide error detection four errors occuring following fields:
[31.28], [27.24], [23.20], [19.16], [15.12], [11.8], [7.4], [3.0], [7.4], [3.0].
29C532E EDAC flag number errors 4-bit wide memory chip. device returns from four bit-in error, CERR NCERR flags generated following error type generated syndrome takes value which never overlaps code single bit-in-error. This restriction triple multi bit-in-error. Example device controlling [7.4] generates error, possible codes different 0x00 those describing single bit-in-error.
error
0x6C
0xEF
0xD5
0x83
0xB9
0x3A
0x49
0x73
0xF1
0x9C
0x56
CERR NCERR
0xCA
0xA6
0x25
0x1F
8.7. 8-Bit Wide Memory Error
checkbit code used provide error detection eight errors occuring following fields:
[31.24], [23.16], [15.8], [7.0], [7.0].
29C532E EDAC flag number errors 8-bit wide memory chip. device returns from eight bit-in error, CERR NCERR flags generated following error type generated syndrome takes value which never overlaps code single bit-in-error. This restriction triple multi bit-in-error.
Rev. February, 1997
Preliminary Information
29C532E
Transactions
9.1. Control
controller guides data flow 29C532E EDAC. This data flow control defines value output buses [31.0] [7.0] checkbit [7.0]:
SYNCHK CORRECT control flow [31.0], OLE/CHK DIAG control flow [7.0], DIAG controls flow [7.0].
Table Data Flow Control
SYNCHK High [31.0] High
CORRECT High
Connected [31.0] [31.0] [7.0] [7.0] [7.0] DIA[7.0]
OLE/CHK [7.0] High
DIAG High
Connected [7.0] [7.0] [7.0]
DIAG [7.0] High
Connected [7.0] [7.0]
Eight signals used supervise transactions
[3.0] control Data Output Buffers, control Checkbit Output Buffer. OLE/CHK controls Data Output Latch, controls Checkbit Data Input Latchs, controls Diagnostic Input Latch.
Rev. February, 1997
Preliminary Information
29C532E
9.2. Memory Write
SYNCHK CORRECT OLE/CHK
[3.0] Data-Out LATCH
[7.0] [31.0]
[31.24] [23.16] [15.8] [7.0] Data BUFFER
CHECKBIT GENERATOR
Data-In LATCH
[31.0] [7.0]
Chk-In LATCH
SYNDROME GENERATOR
CONTROL
Checkbit BUFFER
[7.0] [7.0] [7.0]
[7.0]
Diagnosis LATCH
[31.0] [7.0]
SYNDROME DECODER
DIAG DIAG CERR NCERR
SYNCHK High
CORRECT High
OLE/CHK
[3.] High
DIAG
DIAG
Rev. February, 1997
Preliminary Information
29C532E
9.3. Memory Read Till Error Generation
SYNCHK CORRECT OLE/CHK [3.0] Data-Out LATCH CHECKBIT GENERATOR
[31.24] [23.16] [15.8] [7.0] Data BUFFER
Data-In LATCH
[31.0] [7.0]
Chk-In LATCH
SYNDROME GENERATOR
CONTROL
Checkbit BUFFER
[7.0]
[7.0]
Diagnosis LATCH
SYNDROME DECODER
DIAG DIAG CERR NCERR
SYNCHK High
CORRECT High
OLE/CHK
[3.] High
High
DIAG
DIAG
Rev. February, 1997
Preliminary Information
29C532E
9.4. Memory Read (continue) With Correction Single Bit-in-error
SYNCHK CORRECT OLE/CHK [3.0] Data-Out LATCH
[31.24] [23.16] [15.8] [7.0] Data BUFFER
[31.0]
CHECKBIT GENERATOR
Data-In LATCH
[31.0] [7.0]
Chk-In LATCH
SYNDROME GENERATOR
CONTROL
Checkbit BUFFER
[7.0] [7.0] [7.0]
[7.0]
Diagnosis LATCH
[31.0]
SYNDROME DECODER
DIAG DIAG CERR NCERR
SYNCHK High
CORRECT High
OLE/CHK LM(*)
[3.] High
DIAG
DIAG
when OLE/CHK then [7.0] [7.0] (placed schematic), when OLE/CHK then [7.0] [7.0]
Rev. February, 1997
Preliminary Information
29C532E
9.5. Byte Memory Write Read Modify Write
32-bit Data Memory Checkbit Read
CORRECT OLE/CHK SYNCHK
DIAG [7.0] CHECKBIT GENERATOR SYNDROME GENERATOR SYNDROME DECODER
[31.24]
[23.16]
[15.8]
[7.0]
SYNCHK CORRECT OLE/CHK [3.0] [31.24] [23.16] [15.8] [7.0] CONTROL
[7.0]
DIAG DIAG CERR NCERR
Rev. February, 1997
Preliminary Information
29C532E
Preparing 32-bit Corrected Data
CORRECT OLE/CHK SYNCHK
DIAG [7.0] CHECKBIT GENERATOR SYNDROME GENERATOR SYNDROME DECODER
[31.24]
[23.16]
[15.8]
[7.0]
SYNCHK CORRECT OLE/CHK [3.0] [31.24] [23.16] [15.8] [7.0] CONTROL
[7.0]
DIAG DIAG CERR NCERR
Rev. February, 1997
Preliminary Information
29C532E
8-bit Data Memory Checkbit Write
CORRECT OLE/CHK SYNCHK
DIAG
[31.24] [23.16] [15.8] [7.0]
[7.0]
In-Out
In-Out
In-Out
SYNCHK CORRECT OLE/CHK [3.0] [31.24] [23.16] [15.8] [7.0] CONTROL CHECKBIT GENERATOR
SYNDROME GENERATOR
[7.0]
SYNDROME DECODER
DIAG DIAG CERR NCERR
Rev. February, 1997
Preliminary Information
29C532E
Signal Timing
10.1. Memory Write
tsu1 user word tpd1 tpd16 tpd9
[31.0]
toff generated checkbit
[7.0]
OLE/CHK
(ns) (ns)
toff
Rev. February, 1997
Preliminary Information
29C532E
10.2. Memory Read
[31.0]
memory word
[7.0]
memory word
tpd18 tpd7 tpd3 CERR tpd19 tpd6 tpd4 NCERR valid error flag valid error flag
(ns) (ns)
Rev. February, 1997
Preliminary Information
29C532E
10.3. Memory Read With Correction
CORRECT
tpd11 tpd6 tpd10 tpd2 memory word corrected data
[31.0] [3.0]
tpd1 tpd5 tpd9 tsu1 [7.0] tsu1 tpd3 tpd7 CERR tpd4 tpd8 NCERR checkbit syndrome
OLE/CHK
(ns) (ns)
Rev. February, 1997
Preliminary Information
29C532E
10.4. Memory Byte Write (Read Modify Write)
[2.0] tsu1 tpd2 tpd6 [31.8] memory (corrected) memory
[7.0]
memory tsu2 tsu3 tpd1 tpd1
byte from user
[7.0]
memory tpd16
gen. checkbit
tsu1 OLE/CHK tpd7 tpd3 CERR tpd8 tpd4 NCERR
(ns) (ns)
(ns) (ns)
information contained herein subject change without notice. responsibility assumed Atmel Wireless Microcontrollers using this publication and/or circuits described herein possible infringements patents other rights third parties which result from use.
Rev. February, 1997
Preliminary Information

32-Bit Bus-Watch EDAC Error Detection Correction unit Description

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