Radiation Tolerant Micron Gates MG2RT series micron, array based,

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Radiation Tolerant Micron Gates MG2RT series micron, array based,

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MG2RT
Radiation Tolerant Micron Gates
MG2RT series micron, array based, CMOS product family. Several arrays 700k cells cover system integration needs. MG2RT manufactured using SCMOS3/2RT, micron drawn, metal layers CMOS process, radiation tolerant version SCMOS3/2. MG2RT series base cell architecture provides high routability logic with extremely dense compiled memories RAM, DPRAM FIFO. generated using synthesis tools. instance, largest array capable integrating 128K bits DPRAM with 128K bits over 300,000 random gates. Accurate control clock distribution achieved hardware (Clock Tree Synthesis) software. noise prevention techniques applied array periphery Three more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, swing differential I/Os, contribute improve noise immunity reduce emission level. MG2RT supported advanced software environment based industry standards linking proprietary commercial tools. Cadence, Mentor, Synopsys VHDL reference front tools. Floor planning associated with timing driven layout provides short back cycle. MG2RT family extends Atmel Wireless Microcontrollers offering array based commercial, industrial military circuits. Library allows straight forward migration from MG1RT Gates.
Features
Full Range Matrices 700k Cells Drawn CMOS, Metal Layers, Gates RAM, DPRAM, FIFO Compilers Library Optimised Synthesis, Floor Plan Automatic Test Generation (ATG) Volts Operation (preview: request) High Speed Performances:
max. NAND2 propagation Delay max. min. Toggle Frequency @4.5 @2.7 2.375
High Noise Immunity:
with Slew Rate Control Internal Decoupling Signal Filtering between Periphery Core Application Dependent Supply Routing Several
Programmable available request High System Frequency Skew Control:
max. Clock Generation Clock Tree Synthesis Software
Volts Operation; Single Dual Supply Modes Power Consumption:
µW/Gate/MHz µW/Gate/MHz 0.25 µW/Gate/MHz @2.5
Wide range hermetic ceramic multi-layer packages: plastic packages, call factory. Delivery Form Advanced Support Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management Cadence, Mentor, Vital Synopsys Reference Platforms EDIF VHDL Reference Formats Available Commercial, Industrial, Military Space Quality Grades (SCC, MIL-I-38534, MIL-PRF-38535) Latch immune Total dose better than krads (TM1019.5)
Integrated Power Reset Matrices With full programmable Pads Standard 24mA I/Os Versatile Cell: Input, Output, I/O, Supply, Oscillator CMOS/TTL/PCI Interface Latch-up Protected Selection MQFPs packages pins
Rev. July 2000
MG2RT
List available MG2RT matrix
Type
MG2044E MG2091E MG2140E MG2194E MG2265E MG2360E MG2480E MG2700E
Total Cells
44616 91464 140322 193800 264375 361680 481143 698523
Usable Gates
33000 68000 105000 145000 198000 271000 360000 524000
Maximum
Total Pads
Rev. July 2000
MG2RT
Libraries
MG2RT cell library been designed take full advantage features offered both logic test synthesis tools. Design testability assured full support SCAN, JTAG (IEEE 1149) BIST methodologies. More complex macro functions available VHDL, example I2C, UART, Timer,
Block Generators
Block generators used create customer specific simulation model metallisation pattern regular functions like RAM, DPRAM FIFO. basic cell architecture allows cell DPRAM. main characteristics these generators summarised below.
Function
DPRAM FIFO
Maximum Size (bits)
Typical characteristics (16k bits) bits/word access time (ns)
1-36 1-36 1-36
Used cells
buffer interfacing
Inputs
Input buffers with CMOS thresholds inverting feature versions with without hysteresis. CMOS input buffers incorporate pullup pull down terminators. special purposes, buffer allowing direct input matrix core available.
Fexibility
buffers configured input, output, bi-directional, oscillator supply. level translator located close each buffer.
Outputs
Several kinds CMOS output drivers offered fast buffers with drive noise buffers with drive
Rev. July 2000
MG2RT
Clock generation
Clock generation
Atmel Wireless Microcontrollers offers different types oscillators high frequency crystal oscillator oscillators. devices, mark-space ratio better than 40/60 start-up time less than
Typical
request)
independent devices located upper left lower right corners. Each used following functions Synchronisation internal clock reference system clock. Skew control internal clock transitions synchronous with reference clock. Frequency synthesis frequency dividers used with each PLL. divides reference clock frequency factor other divides internal clock frequency internal clock frequency More details will supplied request.
Frequency (MHz)
Xtal Xtal Xtal Xtal 100M Xtal (2.5V) (@2.5V)
consumption (mA)
(@2.5V)
Rev. July 2000
MG2RT
Power supply noise protection
speed density SCMOS3/2RT technology causes large switching current spikes example either when either high current output buffers switch simultaneously, gates switching within window Sharp edges high currents cause some parasitic elements packaging become significant. this frequency range, package inductance series resistance should taken into account. known that inductor slows down settling time current causes voltage drops power supply lines. These drops affect behaviour circuit itself disturb external application (ground bounce). order improve noise immunity core matrix, several mechanisms have been implemented inside arrays. kinds protection have been added limit buffer switching noise other protect buffers against switching noise coming from matrix.
Buffers switching protection
Three features implemented limit noise generated switching current
power supplies input output buffers separated. rise fall times output buffers controlled internal regulator. design rule concerning number buffers connected same power supply line been imposed.
Matrix switching current protection
This noise disturbance caused large number gates switching simultaneously. allow this without impacting functionality circuit, three features have been added
Decoupling capacitors integrated directly silicon reduce power supply drop. power supply network been implemented matrix. This solution reduces number parasitic elements such inductance resistance constitutes artificial Ground plane. mesh network supplies approximately cells. pass filter been added between matrix input output buffer. This limits transmission noise coming from ground supply matrix external world output buffers.
Rev. July 2000
MG2RT
Power consumption
power consumption MG2RT array three factors leakage (P1), core (P2) (P3) consumption.
Capacitance Power
(VDD VSS)2/2 total output capacitance expressed drain capacitance driver, wiring capacitance gate capacitance inputs. Worst case value µW/gate/MHz
Leakage (Standby) Power Consumption
consumption leakage currents defind (VDD VSS) ICCSB NCELL Where ICCSB leakage current through polarised basic gate NCELL number used cells.
Commutation Power
(VDD VSS) Idsohm Where Idsohm current flowing into driver between supply ground during commutation. Idsohm about Pmos saturation currrent. Worst case value µW/gate/MHz
Core Power Consumption
power consumption switching cells core matrix defind NCELL PGATE CACTIVITY Where NCELL number used cells, data toggling frequency, which equal half clock frequency random data PGATE power consumption cell. PGATE
CACTIVITY
Power Consumption
power consumption I/Os (VDD VSS)2 Fi/2 With equals number buffers running output capacitance. Note signal clock, data with random values, F/4.
fraction total number cells toggling cycle.
Typical Power Consumption Example
Matrix
Used gates Frequency
MG2700E@
MG2700E@3V
MG2700E@2.5V
Standby Power
Iccsb (125°C) (VDD VSS) ICCSB NCELL µW/Gate/MHz 1960 0.58 µW/Gate/MHz 1.25 µW/Gate/MHz
Core Power
Power Consumption Cell Cactivity NCELL PGATE Cactivity
Power
Total Number Buffers Number Outputs Buffers (NI) Output Capacitance (VDD VSS)2 Fi/2
Total Power
2.59 0.81 0.55
Rev. July 2000
MG2RT
Packaging
Atmel Wireless Microcontrollers offers wide range packaging options which listed below
Pins min/max
16/64
Package Type
DQFP** PLCCJ** PQFP** PLASTIC TQFP** VQFP** SSOP** PSO** PBGA** MLCC* MQFP* MPGA
Lead spacing (mils)
25.6 31.5 31.5 19.7 39.4 31.5 19.7 19.7 25.6 25.6
Dimension (mils)
546x782 1102 1260 209x244 153x194 705x295 1500 2000 1150 787x551 1889 1500 2000
CERAMIC
Recommended space. When plastic, call factory; this customer decision plastic packages environmental conditions which beyond those which they have been developed.
Rev. July 2000
MG2RT
Design flows tools
Design Flows modes
generic design flow MG2RT array sketched here beside. down design methodology proposed which starts with high level system description refined successive design steps. each step, structural verification performed which includes following tasks MG2RT Design Flow
System Specifications
Simulation
Gate level logic simulation comparison with high level simulation results. Design test rule check. Power consumption analysis. Timing analysis (only after floor plan).
Logic synthesis
Floor Plan Bonding diagram
main design stages
System specification, preferably VHDL form. Functional description level. Logic synthesis. Floor planning bonding diagram generation. Test/Scan insertion, and/or fault simulation. Physical cell placement, JTAG insertion clock tree synthesis. Routing
Scan insertion Fault Simulation
Placement
JTAG insertion Clock Tree Synthesis
meet various requirements designers, several interface levels between customer Atmel Wireless Microcontrollers possible. each possible design modes review meeting required data transfer from user Atmel Wireless Microcontrollers. cases final routing verifications performed Atmel Wireless Microcontrollers. design acceptance formalised design review which authorises Atmel Wireless Microcontrollers proceed with sample manufacturing.
Routing
Backannotated Simulation
Sign-off
Samples Manufacturing Test
Rev. July 2000
MG2RT
Design tool design kits (DK)
basic content design described table below. interface formats from Atmel Wireless Microcontrollers rely IEEE industry standard VHDL functional descriptions VHDL EDIF netlists Tabular, .CAP simulation results (VITAL format) backannotation physical floor plan information design supported several commercial tools listed below. Design Support Cadence Mentor Synopsys Vital
Design Description
Design Tool library
Design manual libraries VHDL library blocks Synthesis library Gate level simulation library Design rules analyser Power consumption analyser Floor plan library Timing analyser library Package bonding software Scan path JTAG insertion fault simulation library refer "Design kits cross reference tables" ATD-TS-WF-R0181 MISS STAR COMET
Atmel Software Name
Third Party Tools
Rev. July 2000
MG2RT
Operating characteristics
Absolute Maximum Ratings
Ambient temperature under bias (TA) Military +125°C Junction temperature 20°C Storage temperature +150°C TTL/CMOS Supply voltage -0.5 voltage -0.5 Stresses above those listed cause permanent damage device. Explosure absolute maximum rating conditions extended period affect device reliability.
Characteristics
Specified
Symbol
Parameter
Input voltage CMOS input input Input HIGH voltage CMOS input input Output voltage Output high voltage CMOS Schmitt trigger positive threshold CMOS input input Schmitt trigger negative threshold CMOS input input CMOS hysteresis 25oC/5 hysteresis 25oC/5 Input leakage pull up/down Pull Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP Leakage current cell Operating current cell
Unit
Conditions
-12, -12,
+/-1 +/-1 +/-5 -120 +/-5 0.39 10.0 0.53
Delta
µA/MHz BOUT12 VOUT 4.5V VOUT
ICCSB ICCOP
According buffer: Bout12, Bout6, Bout3, 4.5V
Rev. July 2000
MG2RT
Characteristics
Specified
Symbol
Parameter
Input voltage LVCMOS input LVTTL input Input HIGH voltage LVCMOS input LVTTL input Output voltage Output HIGH voltage Schmitt trigger positive threshold LVCMOS input LVTTL input Schmitt trigger negative threshold LVCMOS input LVTTL input CMOS hysteresis 25oC/5 hysteresis 25oC/5 Input leakage pull up/down Pull Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP Leakage current cell Operating current cell
0.7VDD
0.3VDD
Unit
Conditions
+/-1 +/-1
Delta
µA/MHz BOUT12 VOUT VOUT
ICCSB ICCOP
According buffer: Bout12, Bout6, Bout3
Rev. July 2000
MG2RT
Characteristics
Specified +2.5 (Preview)
Symbol
Parameter
Input voltage LVCMOS input Input HIGH voltage LVCMOS input Output voltage LVTTL Output HIGH voltage LVTTL Schmitt trigger positive threshold LVCMOS input LVTTL input Schmitt trigger negative threshold LVCMOS input LVTTL input Input leakage pull up/down Pull Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP Leakage current cell Operating current cell
0.7VDD
0.3VDD
Unit
Conditions
0.95 0.85 +/-1 µA/MHz BOUT12 VOUT VOUT
+/-1
ICCSB ICCOP
According buffer: Bout12, Bout6, Bout3
Rev. July 2000
MG2RT
Characteristics
25°C, Process typical (all values
Buffer
BOUT12
Description
Output buffer with drive
Load
60pf
Transition
Tplh Tphl 2.53 2.76 4.63 4.86 2.97 4.36 4.73 4.89 2.64 2.79 3.01 4.42
3.91 3.64 7.22 6.36 4.48 6.24 7.35 6.44 4.07 3.72 4.61 6.34
2.5V(*)
5.08 4.73 9.39 8.27 5.82 8.11 9.56 8.37 5.29 4.84 8.24
BOUT3
Output buffer with drive
60pf
Tplh Tphl
BOUTQ
noise output buffer with drive
60pf
Tplh Tphl
B3STA3
3-state output buffer with drive
60pf
Tplh Tphl
B3STA12
3-state output buffer with drive
60pf
Tplh Tphl
B3STAQ
noise 3-state output buffer with drive
60pf
Tplh Tphl
Preview
Cell
BINCMOS
Description
CMOS input buffer
Load
Transition
Tplh Tphl 0.77 0.75 0.52 0.42 0.73 0.66 0.68 0.33 -0.12 0.76 0.58 0.65 0.37 0.68 0.42
1.14 1.06 1.31 0.53 1.11 1.21 1.02 0.44 -0.24 0.81 1.08 0.45 1.14 0.54
2.5V(*)
1.48 1.38 1.43 1.04 0.69 1.44 1.17 1.57 1.33 0.57 -0.31 1.43 1.05 0.59 1.48
BINTTL
input buffer
Tplh Tphl
Inverter
Tplh Tphl
NAND2
input NAND
Tplh Tphl
FDFF
flip-flop,
Tplh Tphl
BUF4X
High drive internal buffer
Tplh Tphl
NOR2
2-Input gate
Tplh Tphl
OAI22
4-input INVERT gate
Tplh Tphl
Rev. July 2000
MG2RT
Cell
OSFF
Description
flip-flop with scan input,
Load
Transition
Tplh Tphl 0.83 1.00 0.56 -0.34
1.23 1.38 -0.6
2.5V(*)
1.04 -0.78
Preview
Rev. July 2000

Radiation Tolerant Micron Gates MG2RT series micron, array based,

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