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29C516E

16­Bit Flow­Through EDAC Error Detection And Correction unit

29C516E
16-Bit Flow-Through EDAC Error Detection And Correction unit
1. Introduction
2. Features
Very Low Power CMOS 16-Bit operation with 6 or 8 Check Bits Fast Error Detection : 31 ns (max.) Fast Error Correction : 32 ns (max.) Corrects all Single-Bit Errors Detects all Double-Bit Errors Detects some Multi-Bit Errors Detects Chip Errors (x1, x4 & x8 RAM Format)
MATRA MHS Rev. D (09 Dec. 97)
29C516E
3. Interface
3.1. Functional Diagram
Figure 1.Functional Diagram
CORRECT SYNCHK MEM1 EN1 RD / WR1
CHECK BIT GENERATOR
I / O BUFFER
MC0.7
U1D0.15 U2 / U1 TRANS U2D0.15
16 I / O BUFFER 16
CONTROLLER
16 16 I / O BUFFER 16
29C516E
RD / WR2 EN2 MEM2
I / O BUFFER
MD0.15
CERR NCERR N22
SYNDROME DECODER
SYNDROME GENERATOR
3.2. Block Diagram
Figure 2.Block Diagram
VCC CORRECT SYNCHK N22 U1 / U2 TRANS U1D0.15 MC0.7 EN1 MEM1 RD / WR1 MD0.15 U2D0.15 EN2 MEM2 RD / WR2 GND
29C516E
CERR NCERR
MATRA MHS Rev. D (09 Dec. 97)
29C516E
3.3. Pin Configuration for multilayer quad Flat-pack (flat or L leaded)
Figure 3.Pin Configuration
index corner nc nc MEM2 Gnd U2D15 U2D14 U2D13 U2D12 Vcc U2D11 U2D10 U2D9 U2D8 Gnd U2D7 U2D6 U2D5 U2D4 Vcc U2D3 U2D2 U2D1 U2D0 Gnd NCERR CERR N22 U1D15 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Vcc RD / WR2 CORRECT SYNCHK TRANS U2 / U1 EN2 Gnd Gnd MC7 MC6 MC5 MC4 Vcc MC3 MC2 MC1 MC0 nc nc
MQFPF100 or MQFPL100
(Top view)
nc nc Gnd MD15 MD14 MD13 MD12 Vcc MD11 MD10 MD9 MD8 Gnd MD7 MD6 MD5 MD4 Vcc MD3 MD2 MD1 MD0 Gnd MEM1 EN1 RD / WR1 Vcc U1D0 nc nc
MATRA MHS Rev. D (09 Dec. 97)
nc Vcc U1D14 U1D13 U1D12 Gnd U1D11 U1D10 U1D9 U1D8 Vcc U1D7 U1D6 U1D5 U1D4 Gnd U1D3 U1D2 U1D1 nc
29C516E
3.4. Pin Description
Table 1:
Name Pin Description I / O Active Description
Buses U1D0.15 U2D0.15 D0.15 C0.7 Error Flags CERR NCERR 26 25 O O Low Low Correctable Error Uncorrectable Error 53, 49.47, 45.42, 40.37, 35.33, 28 23.20, 18.15, 13.10, 8.5 59.62, 64.67, 69.72, 74.77 83.86, 88.91 I / O I / O I / O I / O High High High High User 1 Data Bus User 2 Data Bus Memory Data Bus Memory Check-bit Bus
General Control Signals CORRECT SYNCHK N22 TRANS 98 97 27 96 I I I I High Low High H / L When active, the EDAC is in CORRECT mode. If low, the EDAC is in DETECT mode. Selects the Syndrome bits (high byte) and the Check-bits (low byte) to be driven on the selected User Data Bus. When active, the EDAC uses 6 check-bits. If low, the EDAC uses 8 check-bits in memory read. Selects the Data path to be used. If high, the EDAC access the memory, if low, the EDAC access the transfer buffer. Selects who is the master of User 1 and User 2. The master is responsible for applying RD / WRx, MEMx, and ENx signals in a correct way.
User 1 Control Signals RD / WRT EN1 MEM1 55 56 57 I I I H / L Low Low User 1 Read / Write signal User 1 Output Enable User 1 Memory Select
User 1 Control Signals RD / WR2 EN2 MEM2 Power (Buffers) VCCB GNDB Power (Core) VCCC GNDC 100 93 I I - - Core supply (5 V nominal) Core 0 V reference 9, 19, 32, 41, 54, 63, 73, 87 4, 14, 24, 36, 46, 58, 68, 78, 92 I I - - Buffers supply (5 V nominal) Buffers 0 V nominal reference 99 94 3 I I I H / L Low Low User 2 Read / Write signal User 2 Output Enable User 2 Memory Select
Pull-up buffers
MATRA MHS Rev. D (09 Dec. 97)
29C516E
4. Check-Bit Generation
The Check-bit Generator produces 8 check-bits (whatever N22 value) from the incoming User Data Word UxD0.15 according the Table 2. Example: to create check-bit 0, bit 13, 12, 8, 7, 6, 5, 4 and 0 of the Data Word are XORed together. If memory devices 8-bit wide are used, 24 bits (MD0.15 & MC0.7) are stored to give error detection. But if memory devices 1-bit or 4-bit wide are used, 22 bits (MD0.15 & MC0.5) are stored to give error detection.
Table 2: Check Bit Generation (indicates a bit of UxD bus used in the XOR / NXOR)
Even(XOR) Even(XOR) Even(XOR) Odd(NXOR)
5. Syndrome Generation
The syndrome Generator produces 8 syndrome-bits (whatever N22 value) from the incoming Memory Data Word MD0.15 and the associated Check-bits MC0.7 (or MC0.5) according the Table 3. Syndrome-bit SYx is the XOR of the generated Check-bit MCx with the generation of Chek-bit on MD.. Example: to create syndrome-bit 3, first the bit 14, 13, 10, 4, 3, 2, 1 and 0 of the Data Word (MD14, 13, 10, 4, 3, 2, 1, 0) are NXORed. Then, the result is XORed with the associated Check-bit (MC3) of the Check-byte read in the same time as Data Word is checked. If the memory uses x8 devices, then the bits should be physically divided as follows: MC0.7, MD0.7 and MD8.15 . For x4 organization, the bits should be divided MC0.2+MC6, MC3.5+MC7, MD0.3, MD4.7, MD8.11 and MD12.15.
Table 3: Syndrome Bit Generation (indicates a bit of MD and MC buses used in the XOR / NXOR)
EVEN(XOR) EVEN(XOR)
EVEN(XOR) ODD(NXOR) x
MATRA MHS Rev. D (09 Dec. 97)
29C516E
6. Syndrome Decoding
The syndrome decoder generates the error flags CERR (Correctable ERRor) and NCERR (Non-Correctable ERRor). If a correctable error occurs, the 29C516E EDAC provides corrected data to the user. The inputs are the 8 syndrome bits from the syndrome generator, the 16 data bits from the memory and the control signal N22. N22 signal controls if 22 or 24 bits shall be decode from the entire memory word.
Note :
MATRA MHS Rev. D (09 Dec. 97)
29C516E
Syndrome Bit SY .
Note :
7. The 6-Bit Syndrome Word
This feature is available when the N22 pin is driven at a high level.
7.1. No Errors
7.2. Single Bit-Error
A single bit-error in a Memory Data word read (MD.) causes three syndrome bits to be set to one. The code formed indicates which bit of the Memory Data word is incorrect. For example, if MD2 were incorrect, the syndrome byte would have bits 2, 3 and 4 set to one. The syndrome decoder of 29C516E EDAC decodes the information in the syndrome byte and only sets low the error flag CERR. In correct mode (CORRECT pin active), it inverts (and hence corrects) the relevant bit in error of the Memory MATRA MHS Rev. D (09 Dec. 97) Data word and provides the expected Data word for the EDAC controller. If there is an error in the Memory Check-bit (MC.), only one bit of the syndrome is set to one. In this case, the syndrome decoder sets low the correctable error flag CERR, but NCERR does not change. It does not correct the Check-bit because these bits are not used by the system.
29C516E
Table 6: Single Bit-Error
MD. SY(hexa) 15 34h 14 2Ah 13 29h 12 25h 11 32h 10 1Ah 9 16h 8 13h 7 31h 6 23h 5 15h 4 0Bh 3 2Ch 2 1Ch 1 0Eh 0 0Dh
MC. SY(hexa)
7.3. Double-Bit Error
7.4. Triple-Bit Error
Triple-Bit Error When three errors are detected, an error flag is set low as warning to the system. But the generated syndrome can have the listed value of single-bit error. The device must be in detect mode to prevent false correction occurring. Example: If MD0, MD14 and MC1 are corrupted, the syndrome value is "25h ". This is decoded by the 29C516E EDAC as being a correctable error on MD12. The CERR flag is set low and correction would take place if the device is in correct mode. This would cause more errors.
7.5. 4-bit Wide Memory Error
The 6 check-bit code can be used to provide error detection for up to 4 errors occurring in the following groups: MD15.12, MD11.8, MD7.4, MD3.0, MC5.3 and MC2.0. The 29C516E EDAC can flag any number of errors in 4-bit wide memory chip. A special attention must be taken, multi-bit error ( 3) located into the defined groups can provide the syndrome byte of a single-bit error. Example: If MD3, MD2, MD1 and MD0 are in error, the syndrome code is "33 h "
8. The 8-Bit Syndrome Word
This feature is available when the N22 pin is driven at a low level.
8.1. No Errors
8.2. Single Bit-Error
Single Bit-Error A single bit-error in a Memory Data word read (MD.) causes three syndrome bits to be set to one. The code formed indicates which bit of the Memory Data word is incorrect. For example, if MD10 were incorrect, the syndrome byte would have bits 1, 3 and 4 set to one. The syndrome decoder of 29C516E EDAC decodes the information in the syndrome byte and only sets low the error flag CERR. In correct mode (CORRECT pin active), it inverts (and hence corrects) the relevant bit in error of the Memory 8 Data word and provides the expected Data word for the EDAC controller. If there is an error in the Memory Check-bit (MC.), only one bit of the syndrome is set to one. In this case, the syndrome decoder sets low the correctable error flag CERR, but NCERR does not change. It does not correct the Check-bit because these bits are not used by the system.
MATRA MHS Rev. D (09 Dec. 97)
29C516E
Table 7: Single Bit Error
MD. SY(hexa) 15 34h 14 2Ah 13 29h 12 25h 11 32h 10 1Ah 9 16h 8 13h 7 31h 6 23h 5 15h 4 0Bh 3 2Ch 2 1Ch 1 0Eh 0 0Dh
MC. SY(hexa)
8.3. Double-Bit Error
8.4. Triple-Bit Error
When three errors are detected, an error flag is set low as warning to the system. But the generated syndrome can have the listed value of single-bit error. The device must be in detect mode to prevent false correction occurrence. Example: If MD0, MD9 and MC0 are corrupted, the syndrome value is "1Ah ". This is decoded by the 29C516E EDAC as being a correctable error on MD10. The CERR flag is set low and correction would take place if the device is in correct mode. This would cause more errors.
8.5. 4-bit Wide Memory Error
The 8 check-bit code can be used to provide error detection for up to 4 errors occur in the following groups: MD15.12, MD11.8, MD7.4, MD3.0, MC7.4 and MC3.0. The 29C516E EDAC can flag any number of errors in 4-bit wide memory chip. A special attention must be taken, multi-bit error ( 3) located into the defined groups can provide the syndrome byte of a single-bit error. Example: If MD11, MD10, MD9 and MD8 are in error, the syndrome code is "AD h ".
8.6. 8-bit Wide Memory Error
The 8 check-bit code can be used to provide error detection for up to 8 errors occurring in the following groups: MD15.8, MD7.0 and MC7.0. The 29C516E EDAC can flag any number of errors in 8-bit wide memory chip. A special attention must be taken, multi-bit error ( 3) located into the defined groups can provide the syndrome byte of a single-bit error. Example: If MD13, MD12, MD10 and MD9 are in error, the syndrome code is "40h ". (In 6 check-bit coding, the syndrome code should have been "00h ", the "No Error Detected" value.) Note that the syndrome code "40 h " is also the code for MC6 in error.
9. Transactions
Transactions Three types of transactions may be done:
9.1. Memory Read
The TRANS pin is driven at a high level to select the access to the memory. The external arbiter drives the U2 / U1 pin and dispatches the commands RD / WRx, MEMx and ENx. All transaction managed by the master user can be listened by the second user.
MATRA MHS Rev. D (09 Dec. 97)
29C516E
Table 8:
CORRECT SYNCHK RD / WR1 RD / WR2 TRANS NCERR MEM1 MEM2 CERR U2 / U1
Function
9.2. Memory Write
The TRANS pin is driven at a high level to select the access to the memory. The external arbiter drives the U2 / U1 pin and dispatches the commands RD / WRx, Table 9:
RD / WR1 TRANS RD / WR2 MEM1 MEM2
MEMx and ENx. All transaction managed by the master user can be listened by the second user.
Function
MATRA MHS Rev. D (09 Dec. 97)
29C516E
9.3. User to User Transfer
The TRANS pin is driven at a low level to select this mode. The external arbiter drives the U2 / U1 pin and Table 10:
RD / WR1 TRANS RD / WR2 MEM2 MEM1
dispatches the unidirectional commands RD / WRx, MEMx and ENx.
Function
MATRA MHS Rev. D (09 Dec. 97)
29C516E
10. Signal Timing
10.1. Memory Write
Figure 4.Memory Write Timing Diagram
U2 / U1 N22 t13 t20 t22 t22 t22 t20 MD0.15 t14 t20 t22 t22 t22 t20 MC0.7 UD20.15
1.5TRANS 1.5 1.5
t2 Memory Data Word
t19 t23 t23 t23
2.5 Generated Check-bits
t21 t23 t23 t23
RD / WR2 EN2 MEM2 Propagation Delays t2 13 ns Output Enable / Disable Times t19 23 ns t3 26 ns t20 22 ns t13 18 ns t21 22 ns t14 30 ns t22 19 ns ( : Max Value ) ( : Max Value )
Figure 5.Transfer Write Timing Diagram
U2 / U1 t13 t20 t12 t22 t22 t22 t18 UD20.15 UD10.15 TRANS RD / WR1 EN1 MEM1 Propagation Delays t1 14 ns Output Enable / Disable Times t18 23 ns t12 20 ns t19 23 ns t13 18 ns t20 22 ns t21 22 ns t22 19 ns t23 19 ns ( : Max Value ) ( : Max Value ) t21 t23 t23 t23 t19
MATRA MHS Rev. D (09 Dec. 97)
29C516E
10.2. Memory Read
Figure 6.Memory Read Timing Diagram
t8 t5 t16 CERR t9 t6 t17 NCERR N22 MD0.15 MC0.7 CORRECT t22 t22 t22 t18 Memory Data Word Memory Check-bits t15 t4 t7 t10 Corrected Data Valid Error Flag Valid Error Flag
UD10.15 TRANS RD / WR2 EN2 MEM2 Propagation Delays
t5 33 ns t10 19 ns t22 19 ns
t6 34 ns t15 24 ns
t7 32 ns t16 24 ns
t8 31 ns t17 24 ns
( : Max Value )
Output Enable / Disable Times
t18 23 ns
( : Max Value )
MATRA MHS Rev. D (09 Dec. 97)
29C516E
10.3. Transfer Read
Figure 7.Transfer Read Timing Diagram
t13 t20 t12 t22 t22 t22 t18
t21 t23 t23 t23 t19
UD20.15 UD10.15 TRANS RD / WR2 EN2 MEM2 Propagation Delays
t12 20 ns t19 23 ns
t13 18 ns t20 22 ns
( : Max Value )
Output Enable / Disable Times
t18 23 ns
t21 22 ns
t22 19 ns
t23 19 ns
( : Max Value )
11. Electrical Characteristics
11.1. Absolute Maximum Ratings
Table 11:
Parameter Value
Supply voltage, Vcc Input voltage range Input current per power pin Input current per signal pin Continuous output current, one pin Soldering lead temperature 1.6 mm from case for max 10 s Storage temperature Maximum package power dissipation
MATRA MHS Rev. D (09 Dec. 97)
29C516E
11.2. Operating Conditions
Table 12:
Parameter Min. Typ Max Unit
Supply voltage, Vcc Operating temperature range
11.3. Static Electrical Characteristics
Table 13:
Parameter Condition Min. Typ Max Unit
VIH VIL VOH1 VOL1 VOH2 VOL2 IIL IILP IIH IIHP IOZ IOZLP IOZHP CI CIO ICCSB
High level input voltage Low level input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage Low level input current Low level input current, (Pull-up Input) High level input current High level input current, (Pull-down Input) Output leakage current Output leakage current, (Pull-up Input) Output leakage current, (Pull-down Input) Input pin capacitance I / O pin capacitance Standby supply current
Vcc-0.1
MATRA MHS Rev. D (09 Dec. 97)
29C516E
12. Ordering information
Temperature Range Package M FR - Device 29C516E - Speed 31 Flow SB
31ns M: 5V version M: Military S: Space KR: MQFPF100 FR: MQFPL100 EDAC16 rad tolerant Blank: TEMIC Military flow / 883: Mil STD 883 class B or S SB: ESA / SCC 9000 level B SC: ESA / SCC 9000 level C P883: MIL-STD-883 + PIND Test Hxxx: Customer specification
The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and / or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
MATRA MHS Rev. D (09 Dec. 97)