M5M5256DFP,VP,RV -10VLL-I,-12VLL-I,-15VLL-I, -10VXL-I,-12VXL-I,-15VXL-

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M5M5256DFP,VP,RV -10VLL-I,-12VLL-I,-15VLL-I, -10VXL-I,-12VXL-I,-15VXL-

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'97.4.7
M5M5256DFP,VP,RV -10VLL-I,-12VLL-I,-15VLL-I, -10VXL-I,-12VXL-I,-15VXL-I
262144-BIT (32768-WORD 8-BIT) CMOS STATIC
DESCRIPTION
M5M5256DFP,VP,RV 262,144-bit CMOS static RAMs organized 32,768-words 8-bits which fabricated using high-performance polysilicon CMOS technology. resistive load NMOS cells CMOS periphery results high density power static RAM. Stand-by current small enough battery back-up application. ideal memory systems which require simple interface. Especially M5M5256DVP,RV packaged 28-pin thin small outline package.Two types devices available, M5M5256DVP(normal lead bend type package), M5M5256DRV(reverse lead bend type package). Using both types devices, becomes very easy design printed circuit board.
CONFIGURATION (TOP VIEW)
M5M5256DFP
FEATURE
Type Access Power supply current time Active Stand-by (max) (max) (max) 100ns 120ns 150ns 100ns 120ns 150ns 20mA
(Vcc=3.6V)
Outline 28P2W-C (DFP) 28Vcc DQ415
M5M5256DFP,VP,RV-10VLL M5M5256DFP,VP,RV-12VLL M5M5256DFP,VP,RV-15VLL M5M5256DFP,VP,RV-10VXL M5M5256DFP,VP,RV-12VXL M5M5256DFP,VP,RV-15VXL
24µA
(Vcc=3.6V)
4.8µA
(Vcc=3.6V)
0.05µA
(Vcc=3.0V, Typical)
M5M5256DVP
+2.7~3.6V power supply clocks, refresh +2.0V power supply compatible inputs outputs outputs OR-tie capability prevents data contention Data backup capability stand-by
Outline 28P2C-A (DVP)
PACKAGE
M5M5256DFP M5M5256DVP,RV 28pin 13.4 TSOP
APPLICATION
Small capacity memory units
M5M5256DRV
Outline 28P2C-B (DRV)
MITSUBISHI ELECTRIC
'97.4.7
M5M5256DFP,VP,RV -10VLL-I,-12VLL-I,-15VLL-I, -10VXL-I,-12VXL-I,-15VXL-I
262144-BIT (32768-WORD 8-BIT) CMOS STATIC
FUNCTION
operation mode M5M5256DP,KP,FP,VP,RV determined combination device control inputs /OE. Each mode summarized function table. write cycle executed whenever level overlaps with level address must before write cycle must stable during entire cycle. data latched into cell trailing edge whichever occurs first, requiring set-up hold time relative these edge maintained. output enable directly controls output stage. Setting high level,the output stage high-impedance state, data contention problem write cycle eliminated. read cycle executed setting high level level while active state. When setting high level, chip non-selectable mode which both reading writing disabled. this mode, output stage high-impedance state, allowing OR-tie with other chips memory expansion power supply current reduced stand-by current which specified Icc3 Icc4, memory data held power supply, enabling battery back-up operation during power failure power-down operation non-selected mode.
FUNCTION TABLE
Mode selection Write Read High-impedance DOUT High-impedance Stand-by Active Active Active
BLOCK DIAGRAM
ADDRESS INPUT
ADDRESS INPUT BUFFER DECODER 32768 WORD SENSE ANPLIFIER OUTPUT BUFFER 8BIT
DATA
(512 ROWS COLUMNS)
WRITE CONTROL INPUT CHIP SELECT INPUT
DATA INPUT BUFFER COLUMN DECODER ADDRESS INPUT BUFFER
CLOCK GENERATOR
(3V) (0V)
OUTPUT ENABLE INPUT
MITSUBISHI ELECTRIC
'97.4.7
M5M5256DFP,VP,RV -10VLL-I,-12VLL-I,-15VLL-I, -10VXL-I,-12VXL-I,-15VXL-I
262144-BIT (32768-WORD 8-BIT) CMOS STATIC
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Topr Tstg Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect Ta=25°C Ratings -0.3*~4.6 -0.3*~Vcc+0.3
(Max 4.6)
Unit
0~Vcc -40~85 -65~150
-3.0V case Pulse width 30ns
ELECTRICAL CHARACTERISTICS
Symbol VOH1 VOH2 Parameter High-level input voltage Low-level input voltage High-level output voltage IOH=-0.5mA
(Ta=-40~85°C, Vcc=2.7~3.6V, unless otherwise noted)
Test conditions
Limits -0.3*
-0.5
+0.3
Unit
High-level output voltage IOH=-0.05mA Low-level output voltage Input current Output current off-state Active supply current
(AC, level
IOL=1mA VI=0~Vcc /S=VIH /OE=VIH, VI/O=0~Vcc Min. /S0.2V, cycle Other inputs<0.2V >Vcc-0.2V 1MHz Output-open Min. cycle /S=VIL, other inputs=VIH Output-open Min. cycle /SVcc-0.2V, other inputs=0~Vcc /S=VIH,other inputs=0~Vcc Min. cycle 1MHz -VLL -VXL 0.05
Icc1
0.33
Icc2
Active supply current
(AC, level
Icc3 Icc4
Stand-by current Stand-by current
-3.0V case Pulse width 30ns
CAPACITANCE
Symbol
(Ta=-40~85°C, Vcc=2.7~3.6V, unless otherwise noted)
Parameter Input capacitance Output capacitance
Test conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
Limits
Unit
Note Direction current flowing into positive mark). Typical value 25°C. periodically sampled 100% tested.
MITSUBISHI ELECTRIC
'97.4.7
M5M5256DFP,VP,RV -10VLL-I,-12VLL-I,-15VLL-I, -10VXL-I,-12VXL-I,-15VXL-I
262144-BIT (32768-WORD 8-BIT) CMOS STATIC
ELECTRICAL CHARACTERISTICS MEASUREMENT CONDITIONS
-40~85°C, Vcc=2.7~3.6V, unless otherwise noted
Input pulse Input rise fall Reference Output (-10VLL,-10VXL CL=50pF (-12VLL,-12VXL CL=100pF (-15VLL,-15VXL CL=5pF (for ten,tdis) Transition measured ±500mV from steady state voltage. (for ten,tdis)
1TTL
(Including scope JIG)
Fig.1 Output load
READ CYCLE
Symbol ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after high Output disable time after high Output enable time after Output enable time after Data valid time after address Limits -10VLL, -12VLL, -15VLL, Unit
WRITE CYCLE
Limits -10VLL, -12VLL, Write cycle time tw(W) Write pulse width tsu(A) Address setup time tsu(A-WH) Address setup time with respect high tsu(S) Chip select setup time tsu(D) Data setup time th(D) Data hold time trec(W) Write recovery time tdis(W) Output disable time from tdis(OE) Output disable time from high ten(W) Output enable time from high ten(OE) Output enable time from Symbol Parameter -15VLL, Unit
MITSUBISHI ELECTRIC
'97.4.7
M5M5256DFP,VP,RV -10VLL-I,-12VLL-I,-15VLL-I, -10VXL-I,-12VXL-I,-15VXL-I
262144-BIT (32768-WORD 8-BIT) CMOS STATIC
TIMING DIAGRAMS Read cycle
A0~14 ta(A)
(Note
(OE) (OE)
tdis
(Note
(Note
tdis (OE)
(Note
DQ1~8
level
DATA VALID
Write cycle control mode)
A0~14
(Note (Note
(A-WH) tdis tdis (OE) DQ1~8
(Note
trec
ten(OE)
DATA STABLE (Note
MITSUBISHI ELECTRIC
'97.4.7
M5M5256DFP,VP,RV -10VLL-I,-12VLL-I,-15VLL-I, -10VXL-I,-12VXL-I,-15VXL-I
262144-BIT (32768-WORD 8-BIT) CMOS STATIC
Write cycle control mode)
A0~14
(Note
trec
(Note
(Note
(Note
DQ1~8
DATA STABLE
Note Hatching indicates state "don't care". Writing executed overlap low. goes simultaneously with prior outputs remain high impedance state. Don't apply inverted phase signal externally when output mode. ten, tdis periodically sampled 100% tested.
MITSUBISHI ELECTRIC
'97.4.7
M5M5256DFP,VP,RV -10VLL-I,-12VLL-I,-15VLL-I, -10VXL-I,-12VXL-I,-15VXL-I
262144-BIT (32768-WORD 8-BIT) CMOS STATIC
POWER DOWN CHARACTERISTICS ELECTRICAL CHARACTERISTICS
Symbol
(PD) (/S) (PD)
-40~85°C, Vcc=2.7~3.6V, unless otherwise noted)
Parameter
Power down supply voltage Chip select input Power down supply current
Test conditions
-VLL -VXL
Limits
Unit
3V,/SVcc-0.2V, Other inputs=0~Vcc
(Note
0.05
(Note
Note7: (PD) case 25°C Note8: (PD) 0.2uA case 25°C
TIMING REQUIREMENTS -40~85°C, Vcc=2.7~3.6V, unless otherwise noted
Symbol (PD) trec (PD) Parameter
Power down time Power down recovery time
Test conditions
Limits
Unit
POWER DOWN CHARACTERISTICS control mode
(PD)
2.0V 2.7V 2.7V
trec (PD)
2.0V
/SVcc-0.2V
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M5M5256DFP,VP,RV -10VLL-I,-12VLL-I,-15VLL-I, -10VXL-I,-12VXL-I,-15VXL-

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