1048576-BIT(131072-WORD 8-BIT)CMOS STATIC M5M5V108CFP,VP,RV,KV,KR

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1048576-BIT(131072-WORD 8-BIT)CMOS STATIC M5M5V108CFP,VP,RV,KV,KR

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M5M5V108CFP,VP,RV,KV,KR -70HI, -10HI, -70XI, -10XI
1048576-BIT(131072-WORD 8-BIT)CMOS STATIC
M5M5V108CFP,VP,RV,KV,KR 1048576-bit CMOS static organized 131072 word 8-bit which fabricated using high-performance quadruple-polysilicon double metal CMOS technology. thin film transistor (TFT) load cells CMOS periphery result high density power static RAM. They standby current operation current ideal battery back-up application. M5M5V108CVP,RV,KV,KR packaged 32-pin thin small outline package which high reliability high density surface mount device(SMD). types devices available. M5M5V108CVP,KV(normal lead bend type package), M5M5V108CRV,KR(reverse lead bend type package).Using both types devices, becomes very easy design printed circuit board.
CONFIGURATION (TOP VIEW)
ADDRESS INPUTS
FEATURES
Type name
M5M5V108CFP,VP,RV,KV,KR-70HI Access time (max)
Power supply current
DATA INPUTS/ OUTPUTS
Active stand-by (1MHz) (max) (max)
ADDRESS INPUT CHIP SELECT INPUT WRITE INPUT CONTROL ADDRESS INPUTS OUTPUT ENABLE INPUT ADDRESS INPUT CHIP INPUTSELECT DATA INPUTS/ OUTPUTS
Outline 32P2M-A
70ns M5M5V108CFP,VP,RV,KV,KR-10HI 100ns 2.7~3.6V M5M5V108CFP,VP,RV,KV,KR-70XI 70ns M5M5V108CFP,VP,RV,KV,KR-10XI 100ns
24µA 9.6µA
stand-by current 0.1µA (typ.) Directly compatible inputs outputs Easy memory expansion power down S1,S2 Data hold power supply Three-state outputs capability prevents data contention Common data Package M5M5V108CFP 32pin 525mil M5M5V108CVP,RV 32pin TSOP M5M5V108CKV,KR 32pin 13.4 TSOP
M5M5V108CVP,KV
APPLICATION
Small capacity memory units
Outline 32P3H-E(VP), 32P3K-B(KV)
M5M5V108CRV,KR
Outline 32P3H-F(RV), 32P3K-C(KR)
CONNECTION
MITSUBISHI ELECTRIC
M5M5V108CFP,VP,RV,KV,KR -70HI, -10HI, -70XI, -10XI
1048576-BIT(131072-WORD 8-BIT)CMOS STATIC
FUNCTION
operation mode M5M5V108C series determined combination device control inputs S1,S2,W Each mode summarized function table. write cycle executed whenever level overlaps with level high level address must before write cycle must stable during entire cycle. data latched into cell trailing edge W,S1 whichever occurs first,requiring set-up hold time relative these edge maintained. output enable input directly controls output stage. Setting high level, output stage high-impedance state, data contention problem write cycle eliminated. read cycle executed setting high level level while active state(S1=L,S2=H). When setting high level level, chip non-selectable mode which both reading writing disabled. this mode, output stage high- impedance state, allowing OR-tie with other chips memory expansion power supply current reduced stand-by current which specified ICC4, memory data held power supply, enabling battery back-up operation during power failure power-down operation nonselected mode.
FUNCTION TABLE
Mode selection High-impedance selection High-impedance Write Dout Read High-impedance Stand-by Stand-by Active Active Active
BLOCK DIAGRAM
DATA INPUTS/ OUTPUTS
131072 WORDS BITS ROWS X128 COLUMNS 16BLOCKS
ADDRESS INPUTS WRITE CONTROL INPUT CHIP SELECT INPUTS
CLOCK GENERATOR
OUTPUT ENABLE INPUT (0V)
numbers inside dotted line show those TSOP
MITSUBISHI ELECTRIC
M5M5V108CFP,VP,RV,KV,KR -70HI, -10HI, -70XI, -10XI
1048576-BIT(131072-WORD 8-BIT)CMOS STATIC
ABSOLUTE MAXIMUM RATINGS
Symbol Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature With respect Ta=25°C Conditions Ratings 0.3*~4.6 0.3*~Vcc (Max 4.6) 0~Vcc 40~85 65~150 Unit
-3.0V case Pulse width 30ns
ELECTRICAL CHARACTERISTICS (Ta=- 40~85°C, Vcc=2.7~3.6V, unless otherwise noted)
Symbol VOH1 VOH2 ICC1 ICC2 Parameter High-level input voltage Low-level input voltage High-level output voltage High-level output voltage Low-level output voltage Input current Output current off-state Active supply current Active supply current Test conditions Limits IOH= 0.5mA IOH= 0.05mA IOL= VI=0~Vcc S1=VIH S2=VIL OE=VIH VI/O=0~VCC S1=VIL,S2=VIH, other inputs=VIH Output-open(duty 100%) 70ns 100ns 1MHz ~25°C ~40°C ~70°C ~85°C ~25°C ~40°C ~70°C ~85°C ICC4 Stand-by current S1=VIH S2=VIL, other inputs=0~VCC -0.3* 0.33 Unit
ICC3
Stand-by current
0.2V other inputs=0~VCC VCC-0.2V, VCC-0.2V other inputs=0~VCC
-3.0V case Pulse width 30ns
CAPACITANCE (Ta=- 40~85°C, unless otherwise noted)
Symbol Parameter Input capacitance Output capacitance Test conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz Limits Unit
Note Direction current flowing into positive mark). Typical value 25°C
MITSUBISHI ELECTRIC
M5M5V108CFP,VP,RV,KV,KR -70HI, -10HI, -70XI, -10XI
1048576-BIT(131072-WORD 8-BIT)CMOS STATIC
ELECTRICAL CHARACTERISTICS (Ta=- 40~85°C, unless otherwise noted MEASUREMENT CONDITIONS
2.7~3.6V Input pulse level VIH=2.2V,VIL=0.4V Input rise fall time Reference level VOH=VOL=1.5V Output loads Fig.1, CL=30pF CL=5pF (for ten,tdis) Transition measured 500mV from steady state voltage. (for ten,tdis)
including scope 1TTL
Fig.1 Output load
READ CYCLE
Limits Symbol ta(A) ta(S1) ta(S2) ta(OE) tdis(S1) tdis(S2) tdis(OE) ten(S1) ten(S2) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select access time Chip select access time Output enable access time Output disable time after high Output disable time after Output disable time after high Output enable time after Output enable time after high Output enable time after Data valid time after address -70HI,-70XI -10HI,-10XI Unit
WRITE CYCLE
Symbol tw(W) tsu(A) tsu(A-WH) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Parameter Write cycle time Write pulse width Address setup time Address setup time with respect Chip select setup time Chip select setup time Data setup time Data hold time Write recovery time Output disable time from Output disable time from high Output enable time from high Output enable time from Limits -70HI,-70XI -10HI,-10XI Unit
MITSUBISHI ELECTRIC
M5M5V108CFP,VP,RV,KV,KR -70HI, -10HI, -70XI, -10XI
1048576-BIT(131072-WORD 8-BIT)CMOS STATIC
TIMING DIAGRAMS Read cycle
A0~16 ta(A)
(S1)
(Note (Note
tdis (S1)
(Note
(S2) (OE) (OE) tdis (S2)
(Note
(Note
tdis (OE) (S1) (S2)
(Note
DQ1~8
level
DATA VALID
Write cycle control mode)
A0~16
(S1)
(Note (Note
(Note
(S2)
(Note
(A-WH)
trec
tdis tdis (OE) DQ1~8 DATA STABLE
ten(OE)
MITSUBISHI ELECTRIC
M5M5V108CFP,VP,RV,KV,KR -70HI, -10HI, -70XI, -10XI
1048576-BIT(131072-WORD 8-BIT)CMOS STATIC
Write cycle control mode)
A0~16
(S1)
trec
(Note (Note (Note
(Note (Note (Note
DATA STABLE
DQ1~8
Write cycle control mode)
A0~16
(Note (Note
(S2)
trec
(Note
(Note
(Note (Note
DATA STABLE
DQ1~8
Note Hatching indicates state "don't care". Writing executed while high overlaps low. When falling edge simultaneously prior falling edge rising edge outputs maintained high impedance state. Don't apply inverted phase signal externally when output mode.
MITSUBISHI ELECTRIC
M5M5V108CFP,VP,RV,KV,KR -70HI, -10HI, -70XI, -10XI
1048576-BIT(131072-WORD 8-BIT)CMOS STATIC
POWER DOWN CHARACTERISTICS ELECTRICAL CHARACTERISTICS (Ta=- 40~85°C, unless otherwise noted)
Symbol (PD) (S1) (S2) Parameter Power down supply voltage Chip select input Chip select input 2.7VVcc(PD) Vcc(PD)<2.7V ~25°C ~40°C 0.2V, other inputs 0~3V VCC-0.2V, VCC-0.2V other inputs 0~3V ~70°C ~85°C ~25°C ~40°C ~70°C ~85°C Test conditions Limits
Vcc(PD)
Unit
(PD)
Power down supply current
TIMING REQUIREMENTS (Ta=- 40~85°C, unless otherwise noted
Symbol (PD) trec (PD) Parameter Power down time Power down recovery time Test conditions Limits Unit
POWER DOWN CHARACTERISTICS control mode
(PD) 2.7V 2.7V (PD)
2.2V 0.2V
2.2V
control mode
2.7V 2.7V (PD)
(PD)
0.2V 0.2V
0.2V
MITSUBISHI ELECTRIC

1048576-BIT(131072-WORD 8-BIT)CMOS STATIC M5M5V108CFP,VP,RV,KV,KR

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