Cautions Keep safety first your circuit designs! Renesas Technolo
|
|
|
Top Searches for this datasheet
Cautions
Keep safety first your circuit designs! Renesas Technology Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap. Notes regarding these materials These materials intended reference assist customers selection Renesas Technology Corporation product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Renesas Technology Corporation third party. Renesas Technology Corporation assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts, programs, algorithms, circuit application examples contained these materials. information contained these materials, including product data, diagrams, charts, programs algorithms represents information products time publication these materials, subject change Renesas Technology Corporation without notice product improvements other reasons. therefore recommended that customers contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor latest product information before purchasing product listed herein. information described here contain technical inaccuracies typographical errors. Renesas Technology Corporation assumes responsibility damage, liability, other loss rising from these inaccuracies errors. Please also attention information published Renesas Technology Corporation various means, including Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). When using information contained these materials, including product data, diagrams, charts, programs, algorithms, please sure evaluate information total system before making final decision applicability information products. Renesas Technology Corporation assumes responsibility damage, liability other loss resulting from information contained herein. Renesas Technology Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Renesas Technology Corporation necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. Please contact Renesas Technology Corporation further details these materials products contained therein.
Hitachi Microcomputer Development Environment System
SuperH RISC engine Simulator/Debugger
SPARC: Solaris, HP9000 Series
User's Manual
ADE-702-203 Rev. 9/20/99 Hitachi, Ltd. HS0700SDCS3SE
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
SuperH RISC engine Simulator/Debugger (referred this manual simulator/debugger) software tool that simulates SuperH RISC engine series microcomputers support software development host computer. This manual describes simulator/debugger overview usage. Carefully read this manual before using simulator/debugger. C/C++ compiler, assembler, inter-module optimizer, librarian related this simulator/debugger, read following manuals. SuperH RISC engine C/C++ Compiler User's Manual SuperH RISC engine Assembler User's Manual Linkage Editor, Librarian, Object Converter User's Manual details each SuperH RISC engine series microprocessors, refer appropriate hardware programming manuals. This manual explains overview debugger operate detailed operation, initiate simulator/debugger read on-line manual. assumed that commands input from workstation after shell initiated. When using another shell, refer host system other related manuals. following symbols used this manual: contents within specified. Parameters enclosed with omitted.
{A|B}: Either selected. (SP): Indicates more blank spaces. Press space key.
(RET): Press return key. Input: bold italic face indicates input user. shell prompt.
Rev. 1.0, 09/99, page
Rev. 1.0, 09/99, page
Contents
Section Overview.1
Operating Environment Features Simulation Range Notes.3
Section Simulator/Debugger Functions
2.10 2.11 2.12 2.13 Simulator/Debugger Memory Management Endian Pipeline Reset Processing.5 Memory Management Unit (MMU).6 Cache.6 State Controller (BSC) Direct Memory Access Controller (DMAC) Exception Processing Control Registers.9 Trace.10 Standard File Processing Break Conditions.12 Floating-Point Data
Section Operation.17
3.10 3.11 3.12 Setting Path Environment Variables Start-up Windows.21 Loading Load Module Displaying Source File Setting Breakpoints Specifying Symbolic Debugging Addresses.29 Executing Program Displaying Variable Contents.31 Analyzing Execution Performance.33 Analyzing Stack Status.35 Quit
Section Simulator/Debugger Commands.37
ASSEMBLE BREAK_CLEAR BREAK_ENABLE.43
Rev. 1.0, 09/99, page
4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46
BREAKACCESS BREAKACCESS_DISPLAY.45 BREAKDATA BREAKDATA_DISPLAY.47 BREAKPOINT.48 BREAKPOINT_DISPLAY BREAKREGISTER BREAKREGISTER_DISPLAY.52 BREAKSEQUENCE.53 BREAKSEQUENCE_DISPLAY.54 COMPARE.55 DATA_SEARCH DISASSEMBLE.57 DISPLAY_CHARACTERS.58 EXEC_MODE.59 FILE_LOAD FILE_SAVE GO_RANGE GO_RESET GO_TILL HELP.69 LOAD_STATUS.70 LOG_ENABLE LOG_STOP MAP_CLEAR MAP_DISPLAY MAP_SET MEMORY_DISPLAY MEMORY_EDIT.80 MEMORY_FILL.82 MEMORY_MOVE PERFORMANCE_ANALYSIS.84 PERFORMANCE_ANALYSIS_CLEAR.85 PERFORMANCE_ANALYSIS_DISPLAY PERFORMANCE_ANALYSIS_ENABLE QUIT RADIX REGISTER.91 RESET.99 ROUND_MODE .100 SAVE_STATUS .101
Rev. 1.0, 09/99, page
4.47 4.48 4.49 4.50 4.51 4.52 4.53 4.54 4.55 4.56 4.57 4.58 4.59 4.60 4.61 4.62 4.63 4.64 4.65
STACK_ANALYSIS .102 STACK_ANALYSIS_DISPLAY .103 STATUS.105 STEP.107 STEP_G.108 STEP_INTO .110 STEP_INTO_G .112 (Only SH-3/SH-3E/SH-4 Series).114 TLB_DUMP (Only SH-3/SH-3E/SH-4 Series) .117 TLB_FLUSH (Only SH-3/SH-3E/SH-4 Series) .119 TLB_SEARCH (Only SH-3/SH-3E/SH-4 Series) .120 TRACE.121 TRACE_CONDITION.127 TRACE_CLEAR.128 TRAP_ADDRESS.129 TRAP_ADDRESS_DISPLAY.145 TRAP_ADDRESS_ENABLE .146 .<register> .147 Limitations .150
Section Message List .153
Information Messages .153 Error Messages .154
Section Windows Dialog Boxes.163 Section Create Information File .165
Functions Information File Creating Program (CIA) .165 Invoking CIA.165 Usage Procedures Selection Menus .166 Sample Sessions .169 Limitations.173
Rev. 1.0, 09/99, page
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 3.10 Figure 3.11 Figure 3.12 Figure Window Base Window.21 Subwindow Help Window Error Window Manual Window Example Load Module Selection Example Source File Selection.27 Example Setting Breakpoint.28 Example Input Execution Window.30 Example Variable Content Display Example Performance Display Example Stack Trace Display Example Input Quit Window.36 Usage Procedure .166
Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Memory Types.5 Memory Types SH-4 Series Processing When Break Condition Satisfied.12 Simulation Errors.13 Register States Simulation Error Stop Simulator/Debugger Command List Vector Table System Call Functions .130 Special Value Expressions Single-Precision .151 Special Value Expressions Double-Precision.151 Information messages .153 Error Messages .154 Menu Function .163 Limitations .173
Rev. 1.0, 09/99, page
Section Overview
This simulator/debugger provides simulation debugging function SuperH RISC engine series microcomputers support simulation SH-1, SH-2, SH-3, SH-4, SH-2E, SH-3E SH-DSP series. simulator/debugger Ver. promotes efficient debugging programs written language addition those written assembly language. This simulator/debugger operates together with user interface software that runs workstation.
Operating Environment
This simulator/debugger supports following machine environments host system. Machine with SPARC* (hereinafter referred SPARC) Operating system (OS): Solaris version* (OSF/Motif* Window system: Memory capacity: Disk capacity:
OSF/Motif Mbytes more (differs depending system operating status) Mbytes more (including free space required performing operations)
HP9000 series 700* (hereinafter referred HP9000) Operating system (OS): HP-UX 10.2* Window system: Memory capacity: Disk capacity: Software configuration simulator/debugger configured follows: Installer: cas_install Interface software: csdsh, dbgif Simulator/debugger: sdsh12, sdshdsp, sdsh3e, sdsh2e, sdsh4 information file creation program: ciash, ciashdsp, ciash4 Notes: SPARC workstation administrated SPARC International, Inc., based architecture developed Microsystems, Inc. (United States). Solaris trademark Microsystems, Inc. (United States). OSF/Motif trademark Open Software Foundation, Inc. (United States). HP9000 Series trademark Hewlett-Packard Company. (United States). HP-UX trademark Hewlett-Packard Company. (United States).
Rev. 1.0, 09/99, page
OSF/Motif Mbytes more (differs depending system operating status) Mbytes more (including free space required performing operations)
Features
Since simulator/debugger runs host computer, software debugging start without using actual SuperH RISC engine user system, thus reducing overall system development time. simulator/debugger performs pipeline simulation calculate number instruction execution cycles program, thus enabling performance evaluation without using actual SuperH RISC engine user system. simulator/debugger offers following features functions that enable efficient program testing debugging. ability handle SuperH RISC engine CPUs Functions trace instructions subroutines Functions stop continue execution when error occurs during user program execution Function-unit performance measurement comprehensive break functions Functions define modify memory areas
Simulation Range
simulator/debugger supports following SuperH RISC engine microcomputer functions. execution instructions (pipeline simulation) Exception processing Registers address areas (only SH-3, SH-3E, SH-4 series) Cache (only SH-3, SH-3E, SH-4 series) DMAC (only SH-4 series) (only SH-4 series) simulator/debugger does support following SuperH RISC engine microcomputer functions. Programs that these functions must debugged with SuperH RISC engine emulator. Timer Serial communication interface port Interrupt controller (INTC) (only SH-2E, SH-3E, SH-4 series)
Rev. 1.0, 09/99, page
Notes
When loads host computer large, such when many processes operating, simulator/debugger cannot initiated even when memory capacity specified above available. When using Window System* terminal, must which window system host computer operate. Terminating subwindow display Subwindow display, such Dump window display, cannot terminated clicking Close Cancel button. Click STOP button base window then Close Cancel button close subwindow. Terminating simulator/debugger simulator/debugger cannot terminated during debugger command processing. Click STOP button base window abort processing then terminate simulator/debugger. Re-initiating simulator/debugger simulator/debugger operates with processes: csdsh dbgif. Selecting Quit window menu forcibly terminates only csdsh process, dbgif remain. this case, integrated development manager cannot re-initiated. Terminate dbgif following way: Example: Check dbgif process remains while integrated development manager operating: -e|grep dbgif(RET) pts/4 1:32 dbgif dbgif process remains, forcibly terminate with kill command: %kill <PID>(RET) <PID>: process number displayed beginning command execution result (689 above example) following error message output when integrated development manager initiated SPARC, with environment variable LD_LIBRARY_PATH name directory which dynamic link library (libXt) stored. <Error message> ld.so.x: csdsh: fatal: libXt.so.x: can't open file: error=2 When environment variable LD_LIBRARY_PATH been specified %setenv LD_LIBRARY_PATH <directory that stores library>(RET) When environment variable LD_LIBRARY_PATH been specified %setenv LD_LIBRARY_PATH <directory specified before>:<directory that stores library>(RET) Notes: Window System product designed Massachusetts Institute Technology.
Rev. 1.0, 09/99, page
Rev. 1.0, 09/99, page
Section Simulator/Debugger Functions
This section describes SuperH RISC engine simulator/debugger Ver. Note that endian, MMU, cache, control registers used only SH-3, SH-3E, SH-4 series, DMAC used only SH-4 series.
Simulator/Debugger Memory Management
Memory Specification memory specified calculate number memory access cycles during simulation. simulator/debugger supports memory types shown table 2.1. Table Memory Types
User Program Execution Enabled Enabled Enabled Disabled
Memory Type Internal area (X-ROM, Y-ROM) Internal area (X-RAM, Y-RAM) External area Internal area
memory specified information file. create information file, refer section Create Information File. Memory resource allocation memory resource automatically allocated loading user program. area defined program, however, allocated. this case, allocate memory resource using MAP_SET command. SH-4 memory management width area size memory NORMAL memory must specified information file. Other settings must specified register.
Endian
SH-3, SH-3E, SH-4 series, little endian well endian specified data allocation format memory; user program created little endian format also simulated debugged. endian selected option when simulator/debugger started. details option, refer section 3.2, Start-up.
Pipeline Reset Processing
simulator/debugger, which simulates pipeline, resets pipeline when:
Rev. 1.0, 09/99, page
program counter (PC) modified after instruction simulation stops before restarts. command which execution start address been specified executed. Initialization performed program loaded. Memory data being currently fetched decoded rewritten. When pipeline reset, data already fetched decoded cleared, data fetched decoded from current addition, number executed instructions number instruction execution cycles cleared zero.
Memory Management Unit (MMU)
SH3, SH3E, SH-4 series, simulator/debugger simulates operations such operations, address translation, MMU-related exceptions (TLB miss, protection exception, invalid exception, initial page write). user program using address translation simulated debugged. addition, MMU-related exception handler routines simulated debugged. well during user program execution, translates virtual addresses into physical addresses during address display input dialog boxes windows. Therefore, dialog boxes windows, memory accessed with virtual addresses used user program. operations depend type.
Cache
SH-3, SH-3E, SH-4 series, simulator/debugger simulates operations cache. Cache operations during user program execution monitored. simulator/debugger, cache ratio displayed with STATUS command. Checking Displaying Cache Ratio: simulator/debugger displays cache ratio percentage with STATUS command. cache ratio obtained dividing cache count cache access count (the cache count cache miss count). Initializing Cache Ratio: displayed cache ratio reset zero when simulator/debugger initiated, pipeline reset, register value modified. Note: simulator/debugger does change high-order three bits address stored cache address array zeros. When loading memory area which cache been mapped selecting [File Load] menu, turn MMUCR disable MMU.
Rev. 1.0, 09/99, page
State Controller (BSC)
SH-4 series, simulator/debugger functions specifying modifying memory BSC; user program using debugged. Table lists memory types that specified SH-4 series. Table
Address H'00000000 H'03FFFFFF (area H'04000000 H'07FFFFFF (area H'08000000 H'0BFFFFFF (area H'0C000000 H'0FFFFFFF (area H'10000000 H'13FFFFFF (area H'14000000 H'17FFFFFF (area H'18000000 H'1BFFFFFF (area H'1C000000 H'1FFFFFFF (area H'7C000000 H'7C001FFF H'E0000000 H'FFFFFFFF
Memory Types SH-4 Series
Specifiable Memory Types Normal memory, burst ROM, Normal memory, byte control SRAM, Normal memory, DRAM, SDRAM, Normal memory, DRAM, SDRAM, Normal memory, byte control SRAM, Normal memory, burst ROM, Normal memory, burst ROM, Cannot specified Internal (cannot changed) (cannot changed)
high-order three bits addresses areas table must ignored; H'00000000 H'20000000 both area simulator/debugger does support PCMCIA.
Direct Memory Access Controller (DMAC)
SH-4 series, simulator/debugger simulates 4-channel DMAC operations; user program using DMAC debugged.
Exception Processing
simulator/debugger detects generation exceptions corresponding TRAPA instructions, general illegal instructions, slot illegal instructions, address errors. addition, SH-3, SH-3E, SH-4 series, simulator/debugger simulates MMU-related exception processing (TLB miss, protection exception, invalid exception, initial page write). SH-2E, SH-3E, SH-4 series, simulator/debugger also simulates exception processing. This also enables simulation when exception occurs. Exception processing simulated follows according execution mode selected EXEC_MODE command.
Rev. 1.0, 09/99, page
SH-1, SH-2, SH-2E, SH-DSP Series: When (continue)] selected (continue mode): Detects exception during instruction execution. Saves stack area. Reads start address from vector address corresponding vector number. Starts instruction execution from start address. start address simulator/debugger stops exception processing, displays that exception processing error occurred, enters command input wait state. When (stop)] selected (stop mode): Executes steps above, then stops. SH-3 SH-3E Series: When (continue)] selected (continue mode): Detects exception during instruction execution. Saves SSR, respectively. Sets bit, bit, Sets exception code control registers EXPEVT. necessary, appropriate values other control registers. Sets vector address corresponding exception cause. exception detected when reset vector address H'A0000000 regardless exception cause.) Starts instruction execution from address When (stop)] selected (stop mode): Executes steps above, then stops. SH-4 Series: When (continue)] selected (continue mode): Detects exception during instruction execution. Saves SSR, respectively. Sets bit, bit, Sets (FPU disable) reset. Sets exception code control register EXPEVT. necessary, appropriate values other control registers. Sets vector address corresponding exception cause. exception detected when reset vector address H'A0000000 regardless exception cause.) Starts instruction execution from address When (stop)] selected (stop mode): Executes steps above, then stops.
Rev. 1.0, 09/99, page
Control Registers
SH-3, SH-3E, SH-4 series, simulator/debugger supports memory-mapped control registers that used exception processing, control, cache control. addition, SH-4 series, simulator/debugger supports control registers that used control DMAC control. Therefore, user program using exception processing, control, cache control simulated debugged. PTEH: PTEL: TTB: TEA: MMUCR: Page table entry high register Page table entry register Translation table base register exception address register control register
Exception processing
TRA: TRAPA exception register EXPEVT: Exception event register INTEVT: Interrupt event register
Cache
CCR: Cache control register QACR0 QACR1*: Queue address control registers BCR1 BCR2*: WCR1 WCR3*: MCR*: RTCSR*: RTCNT*: RTCOR*: RFCR*: SAR0 SAR3*: DAR0 DAR3*: DMATCR0 DMATCR3*: CHCR0 CHCR3*: DMAOR*: control registers Wait state control registers Individual memory control register Refresh timer control/status register Refresh timer/counter Refresh time constant register Refresh count register source address registers destination address registers transfer count registers channel control registers operation register
DMAC
Note: registers marked with supported only SH-4 series. simulator/debugger does support PCMCIA interface synchronous DRAM mode register.
Rev. 1.0, 09/99, page
2.10
Trace
simulator/debugger writes execution results into trace buffer, which hold results 1024 instructions. trace information acquisition conditions specified TRACE_CONDITION command. acquired trace information displayed Trace window. trace information displayed Trace window depends target follows. SH-1, SH-2, SH-2E, SH-DSP Series: C/C++ assembly-language source programs Total number instruction execution cycles Instruction address Pipeline execution status Instruction mnemonic Data access information (destination accessed data) SH-3 SH-3E Series: C/C++ assembly-language source programs Total number instruction execution cycles Data address Data data Instruction code Instruction number Instruction mnemonic Instruction number that fetched Instruction number that decoded Instruction number that executed Instruction number that accessed memory Instruction number that wrote back data Data access information (destination accessed data) SH-4 Series: C/C++ assembly-language source programs Total number instruction execution cycles (CPU internal clock) Program counter address Instruction number that fetched Number instruction that been executed (E), accessed memory (A), wrote back data pipeline simulation Number instruction that been executed (E), accessed memory (A), wrote back data pipeline simulation
Rev. 1.0, 09/99, page
Number instruction that been executed (E), accessed memory (A), wrote back data pipeline simulation Number instruction that been executed (E), accessed memory (A), wrote back data pipeline simulation Instruction number assigned instruction executed Memory address, instruction code, mnemonic instruction executed. Data access information (destination accessed data)
2.11
Standard File Processing
simulator/debugger supports standard file processing enable input output between user program standard devices (console keyboard). supported processing follows: One-byte input output through standard input/output device One-line input output through standard input/output device Opens closes file Inputs outputs byte from file Inputs outputs line from file Checks file (EOF) Moves and/or acquires current address file pointer TRAP_ADDRESS command used enable this function. Write subroutine branch instruction (BSR, BSRF) specific address input output user program. After initiating simulator/debugger, specify address using TRAP_ADDRESS command execute program. During executing instruction user program, simulator/debugger executes processing using contents parameters after detecting subroutine call instruction (BSR, BSRF) specified address. After completing processing, simulation restarts from instruction following subroutine call instruction. details, refer section 4.61, TRAP_ADDRESS. Note: When JSR, BSR, BSRF instruction used system call instruction, instruction following system call instruction executed normal instruction, slot instruction. Therefore, instruction placed immediately after system call instruction (JSR, BSR, BSRF) must that produces different results depending whether executed normal instruction slot instruction.
Rev. 1.0, 09/99, page
2.12
Break Conditions
simulator/debugger provides following conditions interrupting simulation user program during execution. Break satisfaction break command condition Break detection error during execution user program Break trace buffer overflow Break execution SLEEP instruction Break [Stop] button Break Satisfaction Break Command Condition There five break commands follows: BREAKPOINT: Break based address instruction executed BREAKACCESS: Break based access range memory BREAKDATA: Break based value data written memory BREAKREGISTER: Break based value data written register BREAKSEQUENCE: Break based specified execution sequence When break condition satisfied during user program execution, instruction breakpoint executed before break depending type break, listed table 2.3. Table
Command BREAKPOINT BREAKACCESS BREAKDATA BREAKREGISTER BREAKSEQUENCE
Processing When Break Condition Satisfied
Instruction When Break Condition Satisfied executed Executed Executed Executed executed
BREAKPOINT BREAK_SEQUENCE, breakpoint specified address other than beginning instruction, break condition will detected. When break condition satisfied during user program execution, break condition satisfaction message displayed execution stops.
Rev. 1.0, 09/99, page
Break Detection Error During Execution User Program simulator/debugger detects simulation errors, that program errors that cannot detected exception generation functions. EXEC_MODE command specifies whether stop continue simulation when such error occurs. Table lists error messages, error causes, action simulator/debugger continue mode. Table Simulation Errors
Error Cause Processing Continue Mode
Error Message Memory Access Error
Access memory area that memory write, nothing written; been allocated memory read, bits read Write memory area having write protect attribute Read from memory area having read disable attribute Access memory area where memory does exist Zero division executed DIV1 instruction Operates similar actual device operation
Illegal Operation Illegal Operation
Shift more than bits executed Operates similar actual device PSHA instruction operation Shift more than bits executed PSHL instruction Invalid instruction code multiple entries address translation Always stops Undefined
Invalid Instruction Code Multiple
When simulation error occurs stop mode, simulator/debugger returns command wait state after stopping instruction execution displaying error message. Table lists states program counter (PC) status register (SR) simulation error stop.
Rev. 1.0, 09/99, page
Table
Register States Simulation Error Stop
Value Unchanged
Error Message Value Memory Access When instruction read: Error SH-DSP third instruction address before instruction that caused error. SH-1, SH-2, SH-3, SH-3E, SH-2E, SH-4 instruction address before instruction that caused error. slot address error occurs when branch destination read. When instruction executed: instruction address following instruction that caused error. Illegal Operation instruction address following instruction that caused error. Illegal Operation second instruction address following instruction that caused error.
Invalid second instruction address following instruction that caused Instruction Code error. Multiple address instruction that caused error.
following procedure when debugging programs which include instructions that generate simulation errors. First execute program stop mode confirm that there errors except those intended locations. After confirming above, execute program continue mode. Note: error occurs stop mode simulation continued after changing simulator mode continue mode, simulation performed correctly. When restarting simulation, always restore register contents (general, control, system registers) memory contents state prior occurrence error. Break Trace Buffer Full With break mode specified TRACE_CONDITION command, simulator/debugger stops execution when trace buffer becomes full during instruction execution, displaying following message.
Trace buffer full
Rev. 1.0, 09/99, page
Break Execution SLEEP Instruction When SLEEP instruction executed during instruction execution, simulator/debugger stops execution. following message displayed when execution stopped.
Sleep
Note: When restarting execution, change value instruction address restart location. Break [Stop] Button Ctrl Keys Users forcibly terminate execution pressing [Stop] button Ctrl keys during instruction execution. following message displayed when execution terminated.
User break
Execution resumed with STEP command.
2.13
Floating-Point Data
Floating-point numbers displayed input following real-number data, which makes floating-point data processing easier. Data when [Break Data] [Break Register] menu opened Data Dump window Register value Registers window Input value Registers window floating-point data format conforms ANSI standard. When floating-point data converted from decimal binary, rounding mode following selected ROUND_MODE command. mode (Round Nearest) mode (Round Zero: default) denormalized number specified binary-to-decimal decimal-to-binary conversion, converted zero mode, converted left denormalized number mode. overflow occurs decimal-to- binary conversion, maximum floating point number specified mode infinity specified mode.
Rev. 1.0, 09/99, page
Rev. 1.0, 09/99, page
Section Operation
This section explains start interface software check simulator/debugger operation. This section assumes that user knows operate window system host computer.
Setting Path Environment Variables
Manually path environment variables when using installer them shell script. Setting Path: directory interface software (csdsh) current path specification. %setpath=($path<interface software directory path>)(RET) Setting Environment Variables: interface software uses following environment variables. HS_CA_HOM Specifies directory interface software definition files. %setenvHS_CA_HOM<definition file directory path> (RET) HS_CA_DEF Specifies summary file interface software definition files. %setenvHS_CA_DEF<summary file name> (RET) HS_CA_INT Specifies setup file automatically determine initial settings during interface software initiation. Specify setup file current directory referring setup file sample definition file directory. Refer section 3.2, Start-up, details setup file contents. %setenvHS_CA_INT<setup file name> (RET) HS_CA_SIM Specifies type automatically determine interface software. Specify SH1, SH2, SH3, SH4, SH2E, SH3E, SH-DSP type. %setenvHS_CA_SIM<CPU type> (RET)
Rev. 1.0, 09/99, page
Start-up
Interface software start-up interface software command format follows: csdsh[<setup file name>](RET) After start-up, following message appears.
SERIES CYCLE-ACCURATE SIMULATOR/DEBUGGER Vn.m Copyright Hitachi,Ltd.1998 Copyright Hitachi ULSI System Co.,Ltd.1998 Licensed Material Hitachi,Ltd.
Setup file Used specifying simulator, backup file replay file used. editor create setup file. When setup file specified start-up, setup window shown figure appears, which each item explained below needs entered. Each item specified setup file setup window follows: Simulator specifications simulator specifying format follows (see below parameter start-up): <simulator/debugger name>[<parameter start-up>] SH-1/SH-2 series: sdsh12[-cpu=<CPU information file name>](RET) SH-2E series: sdsh2e[-cpu=<CPU information file name>](RET) SH-DSP series: sdshdsp[-cpu=<CPU information file name>](RET) SH-3/SH-3E series: sdsh3e[-cpu=<CPU information file SH-4 series: sdsh4[-cpu=<CPU information file
Rev. 1.0, 09/99, page
Description: command name simulator/debugger program registered host computer. When this option specified, simulator/debugger reads information from specified file memory map. ".cpu" assumed when file format specified. Specifies endian type (for SH-3, SH-3E, SH-4 series only) big: endian little: Little endian Backup file specifications (omissible) backup file, which created when quitting simulator/debugger, used save window position size well settings window. specifying backup file start-up, settings previous quitting restored. backup file specified follows: BAK<backup file name> Replay file specifications (omissible) replay file, which created using recording function simulator/debugger, used save operation simulator/debugger (inputs simulator/debugger commands clicks buttons). specifying replay file start-up, default settings other operation required debugging automatically executed. replay file specified follows: REP<replay file name> Example setup file example specifying backup replay files using SH-3 simulator/debugger follows:
file sdsh3e backup recover
Rev. 1.0, 09/99, page
window Displays items specified setup file. When setup file specified with environment variable HS_CA_INT, contents setup file displayed. When setup file specified command line, interface software started with contents setup file specified command line, this window will displayed.
Figure Window
Rev. 1.0, 09/99, page
Windows
Base window interface software displays base window after setup. Operation executed this window follows: source file display, program execution, source level debugging such break point setting, release, symbol content display, subwindow selection, simulator/debugger command input.
Figure Base Window
Rev. 1.0, 09/99, page
Menu menu following items (refer section Windows Dialog Boxes, details): File: Selects subwindow file-related operation (e.g. loading saving). View: Selects subwindow display-related operation such registers, symbols disassembly. Execute: Selects subwindow execution-related operation. Break: Selects subwindow break-related operation. Trace: Selects subwindow trace-related operation. Help: Selects subwindow having help function. Source file name Displays name source file displayed source area with absolute path name. Source area Displays source file contents user load module. Mark "PC->" shows line where execution stopped (value program counter). display source file contents updated execution stop. Mark "BP->" shows line where breakpoint set. Command button Available command buttons follows: Step Into When function call exists source line indicated program counter, executes first line called function. Step Executes line indicated program counter. function call exists source line, execution stops after executing whole function. Step When program counter indicates line function, executes function stops when returning calling function. Continue Starts execution from address indicated program counter. Executes line selected source area (clicked line) Reset Executes Reset command debugger. Stop Forcibly stops running debugger command.
Rev. 1.0, 09/99, page
Sets breakpoint line selected source area (clicked line), displaying "BP->" mark. breakpoint cannot selected line corresponding address found), address searched direction smaller line number breakpoint. Clear Clears breakpoint line selected source area (clicked line), clearing "BP->" mark. Help Outputs these descriptions help window. Down Changes display ratio vertical direction) source command areas. Reduces source area expands command area. Down: Expands source area reduces command area. Note: load module which been optimally compiled, "PC->" mark source area move intended source file during program execution using Step, Step Into, Step Out, Continue button. Command area Used directly input simulator/debugger commands display results command execution. available commands, refer section Simulator/Debugger Commands.
Rev. 1.0, 09/99, page
Subwindow help window subwindow opened pulling menu button base window down selecting menu item ("Menu Item."). Each subwindow also Help button open help window displaying functions.
Figure Subwindow Help Window
Rev. 1.0, 09/99, page
Error window manual window When error occurs, error window opened display error messages. Using Manual button error window, manual window explaining error messages opened. When there several messages, select want view error window then press Manual button.
Figure Error Window Manual Window
Rev. 1.0, 09/99, page
Loading Load Module
File Load window load load module. Input file name output inter-module optimizer press CA&DEBUGGER button, which automatically triggers simulator/debugger allocate load module memory. When source file been moved from directory where source file stored when load module output inter-module optimizer, enter path source file directory Path Name File Load window, enter path current source file directory Path Name.
Figure Example Load Module Selection
Rev. 1.0, 09/99, page
Displaying Source File
source file displayed file display changed following procedure. After loading completed, open Source Files window Function Name window. Select Source Files Function Name display press Base Window Display button.
Figure Example Source File Selection
Rev. 1.0, 09/99, page
Setting Breakpoints
breakpoint specifying source line source area pressing button. clear breakpoint, specify source line press Clear button.
Figure Example Setting Breakpoint
Rev. 1.0, 09/99, page
Specifying Symbolic Debugging Addresses
Addresses symbolically input using line numbers, function names variable names instead numeric values (see figure 3.8). This section explains specify symbols. <unit name> character string excluding ".<suffix>" from object module file name output compiler assembler. When <unit name> <file name> include special characters (other characters than alphanumerics, double quotation mark omitted. Line number <unit name>]% <file name> #<line number> Specify <unit name> when specified source file included several units. Function name <unit name>] |<function name> Specify <unit name> when specified function name used several units internal function. Variable name variable names, variable constant names language label names assembly language specified. names, values assumed addresses. When specifying structure union member language, input format <structure name. member name>. Externally defined variable !<variable name> Variable inside unit <unit name>" !<variable name> Variable name inside function <unit name>"] |<function name>!<variable name> Specify <unit name> when specified function name used several units internal function.
Rev. 1.0, 09/99, page
Executing Program
Programs executed specifying program counter (PC) stack pointer (SP) register window command area pressing command button (Step Into, Step, Step Out, Continue, To). Execution also started specifying execution start address window.
Figure Example Input Execution Window
Rev. 1.0, 09/99, page
Displaying Variable Contents
contents variables displayed following procedure. Select variable name source area. figure 3.9, variable selected.) Open Symbol Value window using View menu, acquiring variable name. Press button Symbol Value window.
Rev. 1.0, 09/99, page
Figure Example Variable Content Display
Rev. 1.0, 09/99, page
3.10
Analyzing Execution Performance
Execution performance analyzed following procedure. Open Performance Analysis window using View menu. Input function name analyze Function Name Delete Index column press button. Press Start button start analysis. Press Display button display analysis results. Press Graph button display results graph.
Rev. 1.0, 09/99, page
Figure 3.10 Example Performance Display
Rev. 1.0, 09/99, page
3.11
Analyzing Stack Status
stack status analyzed following procedure. Open Stack Analysis window using View menu. Press Start button start analyzing stack status. Press Display button display analysis results. Press Graph button display results graph.
Figure 3.11 Example Stack Trace Display
Rev. 1.0, 09/99, page
3.12
Quit
Quit window displayed selecting Quit button File menu operation stopped pressing Quit button Quit window. After selecting "Window" backup selection, interface software window position size setting information window saved. default setting file name save setting information "HS_CA.BAK".
Figure 3.12 Example Input Quit Window
Rev. 1.0, 09/99, page
Section Simulator/Debugger Commands
Table shows simulator/debugger commands available command line. Table
Simulator/Debugger Command List
Abbr. Function Assembles line line Clears breakpoints Enables disables breakpoints Sets break conditions based access memory range Displays break conditions based access memory range Sets break condition based value memory data Displays break conditions based value memory data Sets breakpoints based address instruction execution Displays breakpoints based address instruction execution Sets break conditions based value data register Displays break conditions based value data register Sets breakpoints with execution sequence specified Displays breakpoints with execution sequence specified Compares memory contents Searches data Disassembles displays memory contents Displays character string Switches execution mode Loads file Saves memory data file Executes instructions continuously
Command ASSEMBLE BREAK_CLEAR BREAK_ENABLE BREAKACCESS BREAKACCESS_DISPLAY BREAKDATA BREAKDATA_DISPLAY BREAKPOINT BREAKPOINT_DISPLAY BREAKREGISTER BREAKREGISTER_DISPLAY BREAKSEQUENCE BREAKSEQUENCE_DISPLAY COMPARE DATA_SEARCH DISASSEMBLE DISPLAY_CHARACTERS EXEC_MODE FILE_LOAD FILE_SAVE
Rev. 1.0, 09/99, page
Table
Simulator/Debugger Command List (cont)
Abbr. Function Executes instructions continuously (with range specified) Executes user program from vector address Executes instructions continuously (with stop address specified) Displays command names input formats Restores simulator/debugger memory register status Starts creating execution history file Enables/disables execution history file creation Stops creating execution history file Clears memory areas Displays memory areas Sets memory areas Displays memory contents Modifies memory contents Initializes memory areas Moves memory blocks Sets execution performance analysis Clears execution performance analysis Displays execution performance analysis results Enables/disables resets execution performance analysis Exits simulator/debugger Sets radix Displays registers Resets simulator/debugger Specifies displays floating-point rounding mode Saves current simulator/debugger status file
Command GO_RANGE GO_RESET GO_TILL HELP LOAD_STATUS LOG_ENABLE LOG_STOP MAP_CLEAR MAP_DISPLAY MAP_SET MEMORY_DISPLAY MEMORY_EDIT MEMORY_FILL MEMORY_MOVE PERFORMANCE_ANALYSIS PERFORMANCE_ANALYSIS_CLEAR
PERFORMANCE_ANALYSIS_DISPLAY PERFORMANCE_ANALYSIS_ENABLE QUIT RADIX REGISTER RESET ROUND_MODE SAVE_STATUS
Rev. 1.0, 09/99, page
Table
Simulator/Debugger Command List (cont)
Abbr. Function TLBF Enables/disables resets stack analysis Displays stack analysis results Displays simulator/debugger status Performs step execution (executes subroutine step) Specifies step execution address range executing subroutine step Performs step execution Specifies step execution range Modifies contents Flushes contents Displays trace buffer Sets trace condition, starts stops trace Clears trace buffer Sets system call start address Displays system call start address Enables/disables system call start address Changes contents registers
Command STACK_ANALYSIS STACK_ANALYSIS_DISPLAY STATUS STEP STEP_G STEP_INTO STEP_INTO_G TLB_DUMP TLB_FLUSH TLB_SEARCH TRACE TRACE_CONDITION TRACE_CLEAR TRAP_ADDRESS TRAP_ADDRESS_DISPLAY TRAP_ADDRESS_ENABLE .<register>
TLBD Displays contents TLBS Searches contents
Rev. 1.0, 09/99, page
This section explains command format.
Format Parameter Function Description Note Example
numbered items above format described below. Command name. Command abbreviation. Command function. Input format command. Description command parameters options. Command function. Description command usage. Notes command usage. Usage examples.
Rev. 1.0, 09/99, page
ASSEMBLE
Assembles line line
ASSEMBLE
Format ASSEMBLE<start address> (RET) Parameter <start address> Indicates address store results assembly. Function This command converts assembly language notations input interactive mode machine language line units stores results starting indicated start address. assemble mode, entering terminates command, entering moves position backward byte, pressing Enter moves position forward byte. descriptions assembly language, refer SuperH RISC engine Cross Assembler User's Manual. Example interactively input assembly language notation, convert them machine language, store them starting address H'400:
ASSEMBLE (RET) 00000400: (RET) 00000401: (RET) 00000402: #H'02E,R1(RET) 00000402 #H'02E,R1 00000404: R1,R2(RET) 00000404 R1,R2 00000406: ^(RET) 00000405: .(RET)
Rev. 1.0, 09/99, page
BREAK_CLEAR
Clears breakpoints
BREAK_CLEAR
Format BREAK_CLEAR[<index>](RET) Parameter <index> Specifies break number (break number checked breakpoint display). Unless specified, breakpoints cleared. Function Clears breakpoint having specified break number. breakpoints following commands cleared. BREAKACCESS, BREAKDATA, BREAKPOINT, BREAKREGISTER, BREAKSEQUENCE Example clear first breakpoint:
BREAK_CLEAR (RET)
Rev. 1.0, 09/99, page
BREAK_ENABLE
Enables disables breakpoints
BREAK_ENABLE
Format BREAK_ENABLE{E|D}[<index>](RET) Parameters Enable/disable {E|D} (enable): Enables break conditions. (disable): Disables break conditions. <index> Specifies break number (break number checked breakpoint display). Unless specified, breakpoints enabled disabled. Function Enables disables breakpoints having specified break numbers. breakpoints following commands enabled disabled. BREAKACCESS, BREAKDATA, BREAKPOINT, BREAKREGISTER, BREAKSEQUENCE Examples disable first breakpoint:
BREAK_ENABLE (RET)
enable breakpoints:
BREAK_ENABLE (RET)
Rev. 1.0, 09/99, page
BREAKACCESS
Sets break conditions based access memory range
BREAKACCESS
Format BREAKACCESS<start address>[<end address>][{R|W|RW}](RET) Parameters <start address>[<end address>] Specifies start address range memory which simulator/ debugger will stop accessed user program. When address specified, range consists only specified address. Access type {R|W|RW} (read): Breaks read from specified memory. (write): Breaks write specified memory. (read/write): Breaks either read from write specified memory (default). Function Sets break conditions based access memory. Execution stops when specified memory range been accessed. memory ranges specified. Note that breakpoints automatically enabled when breakpoint set. Example breakpoint that execution stops when range from address H'1000 address H'1100 been read written:
BREAKACCESS 1000 1100 (RET)
Rev. 1.0, 09/99, page
BREAKACCESS_DISPLAY
Displays break conditions based access memory range
BREAKACCESS_DISPLAY
Format BREAKACCESS_DISPLAY (RET) Function Displays break conditions based access memory following format: <INDEX>: Break <E/D>: Enable/disable <START>: Start address <END>: address <ATTR>: Access type Example display current settings (address displayed hexadecimal):
BREAKACCESS_DISPLAY(RET) <INDEX> <E/D> <START> <END> <ATTR>
00001000 00001100
Rev. 1.0, 09/99, page
BREAKDATA
Sets break condition based value memory data
BREAKDATA
Format BREAKDATA<break Parameters <break address> Specifies address whose contents checked during execution. <data> Specifies break condition data. <size> Data size {B|W|L|D|S} (byte): Byte data (word): Word data (long): Long-word data (default) (double float): Double-precision floating-point data (single float): Single-precision floating-point data <option> Data equal/not equal {EQ|NE} (equal): Breaks when data equal. (default) (not equal): Breaks when data equal. Function This command sets breakpoint based data written memory. Program execution stops when break condition satisfied. eight breakpoints set. Note that breakpoints automatically enabled when breakpoint set. Examples breakpoint that execution stops when word-size data with value written address H'2000:
BREAKDATA 2000 10;W (RET)
breakpoint that execution stops when address H'AF00 changed byte-size data with value other than
BREAKDATA 0AF00 20;B (RET)
Rev. 1.0, 09/99, page
BREAKDATA_DISPLAY
Displays break conditions based value memory data
BREAKDATA_DISPLAY
Format BREAKDATA_DISPLAY(RET) Function Displays breakpoints based value memory data following format: <INDEX>: Break <E/D>: Enable/disable <ADDRESS>: Break address <DATA>: Written data data size <EQ/NE>: Data equal/not equal Example display currently breakpoints (note that addresses, data displayed hexadecimal):
BREAKDATA_DISPLAY (RET) <INDEX> <E/D> <ADDRESS> 0000FF00 0000AF00 00000100 00000020 00000010 <DATA> 0010:W 20:B 00000100:L 1.235678e-12:S 1.2345678901234567e-123:D <EQ/NE>
Rev. 1.0, 09/99, page
BREAKPOINT
Sets breakpoints based address instruction execution
BREAKPOINT
Format BREAKPOINT<instruction address>[<count>](RET) Parameters <instruction address> Specifies address breakpoint. <count> Specifies count fetchings instructions specified address (H'1 H'3FFF). count automatically unless specified. Function Specifies breakpoints based address instruction execution. Program execution stops break address when break conditions satisfied. instruction break address executed. breakpoints set. Note that breakpoints automatically enabled when breakpoint set. Notes breakpoint address other than first byte instruction, break will detected. count passes reset when program execution stops. Example breakpoint that execution stops when attempting execute instruction address H'2000 eighth time:
BREAKPOINT 2000 (RET)
Rev. 1.0, 09/99, page
BREAKPOINT_DISPLAY
Displays breakpoints based address instruction execution
BREAKPOINT_DISPLAY
Format BREAKPOINT_DISPLAY(RET) Function Displays breakpoints based address instruction execution following format: <INDEX>: Break <E/D>: Enable/disable <ADDRESS>: Breakpoint address <COUNT>: Count fetchings instructions specified address Example display current settings (address counts displayed hexadecimal):
BREAKPOINT_DISPLAY(RET) <INDEX> <E/D> <ADDRESS> <COUNT> 00002000
Rev. 1.0, 09/99, page
4.10
BREAKREGISTER
Sets break conditions based value data register
BREAKREGISTER
Format Parameters <register> Specifies register which break set. <data> Specifies data value break condition. When value specified, break occurs when specified register written. <size> Data size {B|W|L|S|D} When size specified, register size used. When floating-point value specified data, size must omitted. (byte): Byte data (word): Word data (long): Long-word data (single Float): Single-precision floating-point data (double Float): Double-precision floating-point data (only SH-4) <options> Data equal/not equal {EQ|NE} (equal): Breaks when data equal. (default) (not equal): Breaks when data equal. Function This command sets break conditions based data written registers. specified instead R15. command sets break condition that execution stops when specified register accessed. Note that breakpoints automatically enabled when breakpoint set. eight breakpoints set. Examples breakpoint that execution stops when register written:
BREAKREGISTER (RET)
breakpoint that execution stops when contents register becomes
BREAKREGISTER FF;B (RET)
Rev. 1.0, 09/99, page
breakpoint that execution stops when register written value other than
BREAKREGISTER FF;B (RET)
breakpoint that execution stops when contents register becomes 1.0E-5:
BREAKREGISTER 1.0E-5;S (RET)
Rev. 1.0, 09/99, page
4.11
BREAKREGISTER_DISPLAY
Displays break conditions based value data register
BREAKREGISTER_DISPLAY
Format BREAKREGISTER_DISPLAY(RET) Function Displays break conditions based value data register following format: <INDEX>: Break <E/D>: Enable/disable <REGISTER>: Register name <DATA>: Written data data size <EQ/NE>: Data equal/not equal Example display currently breakpoints (displayed floating-point format when data size hexadecimal other data):
BREAKRESISTER_DISPLAY(RET) <INDEX> <E/D> <REGISTER> <DATA> 1.000000e-5 000000FF 000000FF -<EQ/NE>
Rev. 1.0, 09/99, page
4.12
BREAKSEQUENCE
Sets breakpoints with execution sequence specified
BREAKSEQUENCE
Format BREAKSEQUENCE<instruction address1>[<instruction address2>. <instruction address8>] (RET) Parameter <instruction address> Specifies address(es) sequential breakpoint Function This command sets breakpoints with execution sequence specified. Execution stops last specified address when instructions specified addresses have been executed specified order. Note that sequence eight addresses specified. Notes breakpoint address other than first byte instruction, break will detected. execution sequence status reset when instruction execution stops. Example sequential breakpoints addresses H'2000, H'2100 H'3000:
BREAKSEQUENCE 2000 2100 3000 (RET)
Break will occur when addresses H'2000, H'2100, H'3000 executed. Note that passing address defined passing least once. Thus, breakpoint sequence reset when address executed more than once.
Rev. 1.0, 09/99, page
4.13
BREAKSEQUENCE_DISPLAY
Displays breakpoints with execution sequence specified
BREAKSEQUENCE_DISPLAY
Format BREAKSEQUENCE_DISPLAY(RET) Function Displays following information breakpoints with execution sequence specified: <INDEX>: Break <E/D>: Enable/disable BREAK POINT xxxxxxxx: Instruction address BREAK POINT xxxxxxxx: Instruction address Example display currently sequential breakpoint:
BREAKSEQUENCE_DISPLAY(RET) <INDEX> <E/D> BREAK POINT 00002000 BREAK POINT 00002100 BREAK POINT 00002200
Rev. 1.0, 09/99, page
4.14
COMPARE
Compares memory contents
COMPARE
Format COMPARE<start address><end address> <comparison memory start address>(RET) Parameters <Start address> Specifies start address source data. <End address> Specifies address source data. <Comparison memory start address> Specifies start comparison data memory area. Function Compares specified range memory (the source data) with comparison data byte units. When data that does match found, those data items their addresses displayed. Example compare H'500 bytes data starting address H'1000 with H'500 bytes data starting address H'2000, display addresses values source data comparison data when data which does match found:
COMPARE 1000 14FF 2000(RET) SOURCE DATA 00001005 000014FE COMPARED DATA 00002005 000024FE
Rev. 1.0, 09/99, page
4.15
DATA_SEARCH
Searches data
DATA_SEARCH
Format DATA_SEARCH<start address><end address><data>[;<size>](RET) Parameters <start address> Specifies search start address. <end address> Specifies search address. <data> Specifies data searched. <size> Size data {B|W|L|D|S} (byte): Searches byte data (default). (word): Searches word data. (long): Searches long-word data. (double float): Double-precision floating-point data (single float): Single-precision floating-point data Function This command searches specified data specified memory range. Note When searching word data, start address must word boundary (multiple two). When searching single-precision floating-point, double-precision floating-point, long-word data, start address must long-word boundary (multiple four). Example search value 005E from address H'1000 address H'14FF:
DATA_SEARCH 1000 14FF 005E;W (RET) ADDRESS 00001004 00001100 000011A8
Rev. 1.0, 09/99, page
4.16
DISASSEMBLE
Disassembles displays memory contents
DISASSEMBLE
Format DISASSEMBLE<start address>[<instruction count>](RET) Parameters <start address> Specifies start address disassembly. <instruction count> Specifies count instructions disassembled (default max. 65535). Function Disassembles displays range specified start address instruction count. Displays instruction start address, mnemonic instruction operand. invalid instruction displayed with hexadecimal instruction code. Example disassemble display four instructions starting address H'400:
DISASSEMBLE (RET) 00000400 00000402 00000404 00000406 STS.L MOV.L PR,@-R15 #H'C8,R15 #H'00,R3 R3,@(H'08:4, R15)
Rev. 1.0, 09/99, page
4.17
DISPLAY_CHARACTERS
Displays character string
DISPLAY_CHARACTERS
Format DISPLAY_CHARACTERS<character string>(RET) Parameter <character string> Specifies character string. Function Displays characters following space behind command name. Example display SIMULATOR screen:
DISPLAY_CHARACTERS SIMULATOR (RET) SIMULATOR
Rev. 1.0, 09/99, page
4.18
EXEC_MODE
Switches execution mode
EXEC_MODE
EXEC_MODE{S|C}(RET) Format Set: Display: EXEC_MODE(RET) Parameter Execution mode specifier {S|C} (stop): this mode, execution stopped when simulator/debugger detects abnormality (simulation error) user program. (continue): this mode, simulation errors ignored execution continues when simulator/debugger detects abnormality (simulation error) user program. simulator/debugger execution mode when first invoked. Function This command selects whether execution will continue stop when abnormality detected during execution user program. When execution mode specifier omitted, current setting execution mode displayed. Refer section 2.12 (2), Break detection error during execution user program, more information abnormalities which occur while executing user program. Description Set: Stop mode recommended early stages debugging, with continue mode being useful later stages. Display: Stop displayed stop mode, Continue continue mode.
Examples execution mode continue mode:
EXEC_MODE (RET)
display current execution mode:
EXEC_MODE (RET) Continue
Rev. 1.0, 09/99, page
4.19
FILE_LOAD
Loads file
FILE_LOAD
Format FILE_LOAD<file name>[{SYS|ELF|STY}](RET) Parameters <file name> Specifies name file loaded. extension added follows file format specified, ".abs" added file extension format specified: SYS: .abs ELF: .abs STY: .mot File format specifications {SYS|ELF|STY} (SYSROF): Loads SYSROF file (default). (ELF): Loads file. (STYPE): Loads STYPE file (Motorola record type only). Function Loads user program. Although memory required loading allocated FILE_LOAD command SYSROF files, memory allocated STYPE files. Description Reset simulator/debugger before loading user program (for SYSROF only). default settings after loading user program follows: Memory area: area user program allocated (for SYSROF only). SYSROF: entry address specified user program, that address. Otherwise, start address code section that appeared first. STYPE: entry address specified user program, that address. Otherwise, start address load module. ELF: start address section that appeared first. last address internal internal area exists, Other registers flags set.
Rev. 1.0, 09/99, page
Examples load SYSROF-type user program "test1.abs":
FILE_LOAD test1.abs (RET)
load STYPE file "test2.mot":
FILE_LOAD test2.mot (RET)
Rev. 1.0, 09/99, page
4.20
FILE_SAVE
Saves memory data file
FILE_SAVE
Format FILE_SAVE<file name><start address><end address>(RET) <file name> Specifies file name saved. <start address> Specifies start address memory data saved. <end address> Specifies address memory data saved. Function Stores memory area file. Data saved Motorola record format. When file name which already exists specified, data overwritten. When extension specified file name, ".mot" added. Example save memory data from address H'2000 address H'2FFF file "sample.mot":
FILE_SAVE sample.mot 2000 2FFF (RET)
Rev. 1.0, 09/99, page
4.21
Executes instructions continuously
Format GO[<start address>][;D](RET) Parameters <start address> Specifies address from which program execution starts. When omitted, execution starts from address specified program counter. Break disable (disable breaks): Breakpoints specified with break commands temporarily disabled. Function This command executes user program continuously starting specified start address. When specified, break temporarily disabled during command execution enabled again when execution stops. When execution stops, executed instruction count decimal), current register values, disassembled display last instruction executed, termination message displayed. After specifying start address, pipeline reset execution start. Example execute user program from address H'1000 address H'101E (for SH-1):
1000(RET) Exec Instructions PC=00001020 SR=00000000:-IIII- SP=05000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 0000FFFF 00000000 00000000 01000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000010 00000000 0000FFFF 00000000 00000000 05000000 0000101E #H'00,R3
+++5001 breakpoint
Rev. 1.0, 09/99, page
4.22
GO_RANGE
Executes instructions continuously (with range specified)
GO_RANGE
Format GO_RANGE<start address><break address>[;D](RET) Parameters <start address> Specifies address from which program execution starts. <break address> Specifies address which program execution stops. Break disable (disable breaks): Breakpoints specified with break commands temporarily disabled. Function This command executes user program continuously starting specified start address stops execution specified break address. instruction break address executed. When specified, break temporarily disabled during command execution enabled again when execution stops. When execution stops, executed instruction count decimal), current register values, disassembled display last instruction executed, termination message displayed. After specifying start address, pipeline reset execution start. Note break address specified point that first byte instruction, break will detected.
Rev. 1.0, 09/99, page
Example execute user program from address H'1000 address H'1020 SH-3(the instruction address H'1020 executed):
GO_RANGE 1000 1020(RET) Exec Instructions PC=00001020 SR=700000F0:-MRB-1111 SP=00001FEC GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000003 00000002 000001E4 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000001 000001EC 00001FEC R0_BANK-R3_BANK 00000000 00000000 00000000 00000000 R4_BANK-R7_BANK 00000000 00000000 00000000 00000000 SSR=00000000 SPC=00000000 PTEH=00000000 PTEL=00000000 TTB=00000000 TEA=00000000 MMUCR=00000000 EXPEVT=00000000 INTEVT=00000000 TRA=00000000 CCR=00000000 0000101E #H'00,R3
+++5001 breakpoint
Rev. 1.0, 09/99, page
4.23
GO_RESET
Executes user program from vector address
GO_RESET
Format GO_RESET(RET) Function Executes user program starting from address specified reset vector. When execution stops, executed instruction count decimal), current register values, disassembled display last instruction executed, termination message displayed. Description SH-1/SH-2/SH-DSP/SH-2E series: Before execution, reset exception processing vector table must memory. Save initial values table. Table
Register
Vector Table
Vector Vector Table Address Saved H'00000000 H'00000003 H'00000004 H'00000007
SH-3/SH-3E/SH-4 series: reset vector address fixed H'A0000000.
Rev. 1.0, 09/99, page
Example start power-on reset execution from reset vector (for SH-3):
GO_RESET Exec Instructions PC=A0000018 SR=700000F0:-MRB-1111- SP=7F001000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 7F001000 R0_BANK-R3_BANK 00000000 00000000 00000000 00000000 R4_BANK-R7_BANK 00000000 00000000 00000000 00000000 SSR=00000000 SPC=00000000 PTEH=00000000 PTEL=00000000 TTB=00000000 TEA=00000000 MMUCR=00000000 EXPEVT=00000000 INTEVT=00000000 TRA=00000000 CCR=00000000 A0000016
+++5001 breakpoint
Rev. 1.0, 09/99, page
4.24
GO_TILL
GO_TILL
Executes instructions continuously (with stop address specified)
Format GO_TILL<break address 1>[<break address 2><break address <break address 10>][;D](RET) Parameters <break address> Specifies address which user program execution stops. points) Break disable (disable breaks): Breakpoints specified with break commands temporarily disabled. Function This command executes user program continuously starting address specified program counter, stops execution specified break address. instruction break address executed. break addresses specified. When specified, break temporarily disabled during command execution enabled again when execution stops. When execution stops, executed instruction count decimal), current register values, disassembled display last instruction executed, termination message displayed. Note break address specified point that first byte instruction, break will detected. Example continuously execute user program from address specified current program counter address H'1000, H'1010 H'1020 SH-1:
GO_TILL 1000 1010 1020(RET) Exec Instructions PC=00001020 SR=00000000:- SP=05000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 0000FFFF 00000000 00000000 01000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000010 00000000 0000FFFF 00000000 00000000 05000000 0000101E #H'00,R3
+++5001 breakpoint
Rev. 1.0, 09/99, page
4.25
HELP
HELP
Displays command name input format
Format HELP[<command name>](RET) Parameter <command name> Specifies name command display help message. Function Displays help message specified command. When command name omitted, list commands displayed.
Examples display list commands:
HELP(RET) .<register> ASsemble Break_Enable BreakAccess_Display BreakData_Display BreakPoint_Display Trace Trace_Condition Trap_address_Display Break_Clear BreakAccess BreakData BreakPoint BreakRegister Trace_cLear Trap_Address Trap_address_Enable
display syntax HELP command:
:HELP HELP(RET) HE|HELP[<command name>]
Rev. 1.0, 09/99, page
4.26
LOAD_STATUS
Restores simulator/debugger memory register status
LOAD_STATUS
Format LOAD_STATUS[<file name>](RET) Parameter <file name> Specifies name file which simulator/debugger memory register status saved. When file name omitted, file sdsh.sav assumed. When file extension omitted, extension .sav supplied default. Function states memory registers restored point when corresponding SAVE_STATUS command executed. Reloads load module which been loaded SAVE_STATUS command execution. Example load memory register status saved file "test1.sav":
LOAD_STATUS test1.sav(RET)
Rev. 1.0, 09/99, page
4.27
Starts creating execution history file
Format LOG<file name>[A](RET) <file name> Specifies file name which execution history output. Append mode specification (append): Adds execution history specified file. When this option omitted, execution history saved from start specified file. Function Starts outputting execution history file. specified file already exists, file deleted create file. When restart specified without stopping after start, file which receiving outputs closed then output specified file resumes. Note When error occurs during processing system call, data written output file. Examples start writing sample.log file which command inputs display data written:
sample.log (RET)
execution history sample.log:
sample.log (RET)
Rev. 1.0, 09/99, page
4.28
LOG_ENABLE
Enables/disables execution history file creation
LOG_ENABLE
Format LOG_ENABLE{E|D}(RET) Parameter Terminates resumes outputting execution history file {E|D} (enable): Resumes outputting file. (disable): Terminates outputting file. Function Outputting file terminates when option (disable) specified resumes when (enable) specified. Note When error occurs during processing system call, data written output file. Examples terminate writing file:
LOG_ENABLE (RET)
resume writing file:
LOG_ENABLE (RET)
Rev. 1.0, 09/99, page
4.29
LOG_STOP
Stops creating execution history file
LOG_STOP
Format LOG_STOP(RET) Function Stops creating execution history file. Note When error occurs during processing system call, data written output file. Example stop writing file:
LOG_STOP (RET)
Rev. 1.0, 09/99, page
4.30
MAP_CLEAR
Clears memory areas
MAP_CLEAR
Format MAP_CLEAR<start address><end address>(RET) Parameters <start address> Specifies start address memory area. <end address> Specifies address memory area. Function Clears memory areas allocated MAP_SET command. Example clear address H'301F from address H'3000 which already been specified:
MAP_CLEAR 3000 301F (RET)
Rev. 1.0, 09/99, page
4.31
MAP_DISPLAY
Displays memory areas
MAP_DISPLAY
Format MAP_DISPLAY[M](RET) Parameter Memory information display (map): Specifies memory information display information file. Functions memory information displayed following format. Memory information display <START>: Start address <END>: address <ATTR>: Access type read, write, read/write) <SECT_NAME>: Section name Memory information display information file <KIND>: Memory type (I/O: internal I/O, RAM: internal RAM, ROM: internal ROM, EXT: external area) <START>: Start address <END>: address <STATE>: Memory access state count displayed SH-4) <BUS>: Memory data width Examples display current memory allocation state:
MAP_DISPLAY (RET) <START> <END> <ATTR> SECT1 <SECT_NAME>
00000000-000003FF 00002000-000020EF 00003000-0000301F
Rev. 1.0, 09/99, page
display memory information information file:
MAP_DISPLAY (RET) <KIND> <START> <END> <STATE> 00000001 00000001 00000001 00000001 <BUS> 00000032 00000032 00000032 00000032
00000000-7EFFFFFF 7F000000-7F000FFF 7F001000-DFFFFFFF E0000000-FFFFFFFF
Rev. 1.0, 09/99, page
4.32
MAP_SET
Sets memory areas
MAP_SET
Format MAP_SET<start address>[<end address>][{R|W|RW}](RET) Parameters <start address> Specifies start address memory area. <end address> Specifies address memory area. start address assumed unless specified. Access type {R|W|RW} (read): Specifies memory area read-only. (write): Specifies memory area write-only. (read/write): Specifies memory area read/write. (default) Function Sets memory areas used user program. Notes Areas reset with newly specified contents even range MAP_SET command already been allocated. Several areas re-specified cleared same time. Examples allocate addresses H'3000 H'301F read-only memory area:
MAP_SET 3000 301F R(RET)
change access type write-only memory area allocated addresses H'03FF
MAP_SET W(RET)
Rev. 1.0, 09/99, page
4.33
MEMORY_DISPLAY
Displays memory contents
MEMORY_DISPLAY
Format MEMORY_DISPLAY<start Parameters <start address> Specifies start address memory content display. <length> Specifies length (byte count) data displayed (default: H'100, max.: H'4000) <size> Data size {B|W|L|D|S|A} (byte): Byte data (default) (word): Word data (long): Long-word data (double float): Double-precision floating-point data (single float): Single-precision floating-point data (ASCII): ASCII data Function Displays memory contents. Note When memory contents displayed word size, start address must word boundary (multiple two). When memory contents displayed single-precision floating-point, double-precision floating-point, long-word size, start address must long-word boundary (multiple four). Examples display memory contents from address H'1000 byte units:
MEMORY_DISPLAY 1000;B(RET) address
00001000 00001010
000010E0 0A051 000010F0
Rev. 1.0, 09/99, page
display 16-byte memory contents from address H'1000 word units:
MEMORY_DISPLAY 1000 10;W(RET) address
00001000 4F22 7FC8 E300 1F32 A012 0009 D11E 410B
display 16-byte memory contents from address H'1000 long word units:
MEMORY_DISPLAY 1000 10;L(RET) address
00001000 4F227FC8 E3001F32 A0120009 D11E410B
display 8-byte double-precision floating-point data from address H'2000:
MEMORY_DISPLAY 2000 8;D(RET) address
00002000 2.87495706857453e-67
display 8-byte single-precision floating-point data from address H'2000:
MEMORY_DISPLAY 2000 8;S(RET) address
00002000 -2.612572e+05 00002004 9.255220e-09
display 22-byte ASCII data from address H'3000:
MEMORY_DISPLAY 3000 16;A(RET) address ASCII
00003000 0".2.A. 00003010
Rev. 1.0, 09/99, page
4.34
MEMORY_EDIT
Modifies memory contents
MEMORY_EDIT
MEMORY_EDIT<start address><data>[;<size>](RET) Format Modify: Interactive mode: MEMORY_EDIT<start address>[;<size>](RET) Parameters <start address> Specifies start address modified. <data> Specifies contents modified. <size> Data size {B|W|L|D|S|A} (byte): Memory modified byte units. (default) (word): Memory modified word units. (long): Memory modified long-word units. (double float): Memory modified double-precision floating-point units. (single float): Memory modified single-precision floating-point units. (ASCII): Memory modified ASCII character string units. Function Changes contents memory specified value. Description When command specifying interactive mode input, interactive mode entered after contents specified address displayed.
MEMORY_EDIT<start address>(RET) address data: [{<data>|^}](RET) address data: [{<data>|^}](RET) address data: .(RET)
address data: <data>: Only (RET) input: (period):
Displays data before modification. Specifies data modified. Displays contents previous address. Displays contents next address. Terminates MEMORY_EDIT command.
Rev. 1.0, 09/99, page
Note When memory contents modified word size, start address must word boundary (multiple two). When memory contents modified single-precision floating-point size, double-precision floating-point size, long-word size, start address must long-word boundary (multiple four). Examples change contents byte memory address H'1000 H'3E:
MEMORY_EDIT 1000 3E;B(RET)
change memory contents byte unit from address H'1000 interactive form:
MEMORY_EDIT 1000;B(RET) 00001000 5F(RET) 00001001 (RET) 00001002 25(RET)
00001005 .(RET)
change memory contents single-precision floating-point units from address H'2000 interactive form:
MEMORY_EDIT 2000;S(RET) 00002000 1.413991E-3 F'-3.1415922E+1(RET) 00002004 1.234567E+5 .(RET)
Rev. 1.0, 09/99, page
4.35
MEMORY_FILL
Initializes memory areas
MEMORY_FILL
Format MEMORY_FILL<start address><end address><data value>[;<size>] [<verify flag>](RET) Parameters <start address> Specifies start address memory initialized. <end address> Specifies address memory initialized. <data value> Specifies data set. <size> Data size {B|W|L|D|S} (byte): Byte data (default) (word): Word data (long): Long-word data (double float): Double-precision floating-point data (single float): Single-precision floating-point data <verify flag> Data verified after setting {V|N} Verified (default) verified Function Sets initial data specified range addresses. Note When word-size data written into memory area range, start address must word boundary (multiple two). When single-precision floating-point size, doubleprecision floating-point size, long-word size written into memory area range, start address must long-word boundary (multiple four). Examples clear addresses H'1000 H'1FFF then verify them:
MEMORY_FILL 1000 1FFF 0(RET)
H'FF00 addresses H'2000 H'2FFF word units without verifying them:
MEMORY_FILL 2000 2FFF FF00;W N(RET)
Rev. 1.0, 09/99, page
4.36
MEMORY_MOVE
Moves memory blocks
MEMORY_MOVE
Format MEMORY_MOVE<start address><end address> <transfer destination address>(RET) Specifies start address transfer source. Parameters <start address>: <end address>: Specifies address transfer source. <transfer destination address>: Specifies start address transfer destination. Function Copies memory data specified range specified transfer destination. Before copying, allocate area transfer destination using MAP_SET command. Example copy contents addresses H'1000 H'14FF addresses H'2000 later:
MEMORY_MOVE 1000 14FF 2000 (RET)
Rev. 1.0, 09/99, page
4.37
PERFORMANCE_ANALYSIS
Sets execution performance analysis
PERFORMANCE_ANALYSIS
Format PERFORMANCE_ANALYSIS[<start address>](RET) Parameter <start address> Specifies start address function whose execution performance analyzed. When start address specified, execution performance functions (only those actually executed) analyzed. Function Analyzes maximum, minimum total execution cycle call counts specified function(s). Note analysis results invalid value changed (pipeline reset) .<register> other commands during function analysis. Example specify execution performance analysis functions:
:PERFORMANCE_ANALYSIS(RET)
Rev. 1.0, 09/99, page
4.38
PERFORMANCE_ANALYSIS_CLEAR
Clears execution performance analysis
PERFORMANCE_ANALYSIS_CLEAR
Format Parameter <index> Specifies function number cleared (index checked execution performance analysis display). index specified, analysis results cleared. Function Clears execution performance analysis. Example clear analysis results index no.1:
:PERFORMANCE_ANALYSIS_CLEAR 1(RET)
Rev. 1.0, 09/99, page
4.39
PERFORMANCE_ANALYSIS_DISPLAY
PERFORMANCE_ANALYSIS_DISPLAY Displays execution performance analysis results
Format Parameter Display type {A|C} (address): Displays analysis results address (ascending) order (default). (cycle): Displays analysis results cycle count (descending) order. Function Displays execution performance analysis results following format: INDEX: Registered number function ADDRESS: Start address function MAXCYCLE: Maximum execution cycle count function MINCYCLE: Minimum execution cycle count function TOTALCYCLE: Total execution cycle count function COUNT: Call count function Ratio total execution cycle count function that whole user program HISTOGRAM: Displays above ratio histogram Description Displays execution cycle count each specified function. execution cycle count obtained from difference between accumulative execution cycle counts execution call instructions from specified function that return instructions from specified function. 9999 functions set. Examples display analysis results address (ascending) order:
INDEX ADDRESS 00001234 00005678 MAXCYCLE 20000 15000 MINCYCLE 10000 5000 TOTALCYCLE COUNT 50000 600000 HISTOGRAM #### #####
Rev. 1.0, 09/99, page
display analysis results cycle count (descending) order:
:PERFORMANCE_ANALYSIS_DISPLAY C(RET) INDEX ADDRESS 00005678 00001234 MAXCYCLE 15000 20000 MINCYCLE 5000 10000 TOTALCYCLE COUNT 600000 50000 HISTOGRAM ##### ####
Rev. 1.0, 09/99, page
4.40
PERFORMANCE_ANALYSIS_ENABLE
PERFORMANCE_ANALYSIS_ENABLE Enables/disables resets execution performance analysis
Format Parameter Specification type {E|D|R} (enable): Enables analysis. (disable): Disables analysis. (reset): Resets analysis results. Function Enables/disables execution performance analysis resets analysis results. Description Execution performance analysis disabled when simulator initiated. resetting, only analysis results reset execution performance analysis enable/disable setting registered start address (including functions) changed. Examples disable execution performance analysis:
PERFORMANCE_ANALYSIS_ENABLE D(RET)
reset analysis results:
PERFORMANCE_ANALYSIS_ENABLE R(RET)
Rev. 1.0, 09/99, page
4.41
QUIT
QUIT
Exits simulator/debugger
Format QUIT(RET) Function Exits simulator/debugger returns Closes execution history command files they opened. Example terminate simulator/debugger processing:
QUIT (RET)
(The csdsh simulator/debugger terminated prompt will displayed)
Rev. 1.0, 09/99, page
4.42
RADIX
RADIX
Sets radix
RADIX{B|O|D|H}(RET) Format Set: Display: RADIX(RET) Parameter Radix {B|O|D|H} Sets radix binary. Sets radix octal. Sets radix decimal. Sets radix hexadecimal. radix hexadecimal when simulator/debugger invoked. Function Sets displays default radix. radix displayed parameter specified. When input before numeric data, input precedes default radix. Display contents Binary Octal Decimal Hexadecimal Examples display current radix:
RADIX(RET) Hexadecimal
change radix decimal:
RADIX D(RET) RADIX(RET) Decimal
Rev. 1.0, 09/99, page
4.43
REGISTER
Displays registers
REGISTER
Format REGISTER[{C|F|A}](RET) Parameter Specification display register {C|F|A} (cpu): Displays register contents (and registers SH-DSP) (default) (fpu): Displays register contents (Valid only SH-2E, SH-3E, SH-4) (all): Displays contents CPU, FPU, management registers (display management register valid only SH-3, SH-3E, SH-4). Function Displays following register contents. Display SH-1 SH-2 series registers -General registers: R0-R15 -Control registers: GBR, -System registers: MACH, MACL, Display SH-DSP series registers -General registers: -Control registers: -System registers: registers -Data registers: -Control register: Display SH-3 series registers -General registers: -Control registers: -System registers: Management registers:
R0-R15 GBR, VBR, MACH, MACL, A0G, A1G,
R0-R15, R0_BANK-R7_BANK GBR, VBR, SSR, MACH, MACL, PTEH, PTEL, TTB, TEA, MMUCR, EXPEVT, INTEVT, TRA,
Rev. 1.0, 09/99, page
Display SH-2E series registers -General registers: -Control registers: -System registers: registers: -Floating-point registers: -Control registers: -System registers: Display SH-3E series: registers -General registers: -Control registers: -System registers: Management registers:
R0-R15 GBR, MACH, MACL, FR0-FR15 FPSCR FPUL
R0-R15 R0_BANK-R7_BANK GBR, VBR, SSR, MACH, MACL, PTEH, PTEL, TTB, TEA, MMUCR, EXPEVT, INTEVT, TRA,
registers -Floating point registers: FR0-FR15 -Control register: FPSCR -System register: FPUL Display SH-4 series: registers -General registers: -Control registers: -System registers: Management registers:
R0-R15 R0_BANK-R7_BANK GBR, VBR, SSR, SPC, SGR, MACH, MACL, PTEH, PTEL, TTB, TEA, MMUCR, EXPEVT, INTEVT, TRA, CCR, QACR0, QACR1
registers -Floating point registers: FR0-FR15, XF0-XF15, DR0, DR2, DR4, DR6, DR8, DR10, DR12, DR14, XD0, XD2, XD4, XD6, XD8, XD10, XD12, XD14 -Control register: FPSCR -System register: FPUL
Rev. 1.0, 09/99, page
Example
display registers: SH-1/SH-2 series
REGISTER A(RET) PC=00000000 SR=000000F0:-1111- SP=00000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
SH-DSP series
REGISTER A(RET) PC=00000000 SP=00000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 RS=00000000 RE=00000000 MOD=00000000 DSR=00000000:-COBA0G=00 A0=00000000 M0=00000000 X0=00000000 Y0=00000000 A1G=00 A1=00000000 M1=00000000 X1=00000000 Y1=00000000
SH-3 series
REGISTER A(RET) PC=00000000 SR=700000F0:-MRB-1111- SP=00000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 R0_BANK-R3_BANK 00000000 00000000 00000000 00000000 R4_BANK-R7_BANK 00000000 00000000 00000000 00000000 SSR=00000000 SPC=00000000 PTEH=00000000 PTEL=00000000 TTB=00000000 TEA=0000000 MMUCR=00000000 EXPEVT=00000000 INTEVT=00000000 TRA=00000000 CCR=00000000
Rev. 1.0, 09/99, page
REGISTER C(RET) PC=00000000 SR=700000F0:-MRB-1111- SP=00000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 R0_BANK-R3_BANK 00000000 00000000 00000000 00000000 R4_BANK-R7_BANK 00000000 00000000 00000000 00000000 SSR=00000000 SPC=00000000
SH-3E series
REGISTER A(RET) PC=00000000 SR=700000F0:-MRB-1111- SP=00000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 R0_BANK-R3_BANK 00000000 00000000 00000000 00000000 R4_BANK-R7_BANK 00000000 00000000 00000000 00000000 SSR=00000000 SPC=00000000 PTEH=00000000 PTEL=00000000 TTB=00000000 TEA=0000000 MMUCR=00000000 EXPEVT=00000000 INTEVT=00000000 TRA=00000000 CCR=00000000 FPUL=00000000 FPSCR=00040001:-D-RZ FR0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
FR8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 FR0- FR4- FR8-11 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00
FR12-15 0.000000e+00
Rev. 1.0, 09/99, page
REGISTER F(RET) PC=00000000 SR=700000F0:-MRB-1111- SP=00000000 FPUL=00000000 FPSCR=00040001:-D-RZ FR0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
FR8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 FR0- FR4- FR8-11 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00
FR12-15 0.000000e+00
REGISTER C(RET) PC=00000000 SR=700000F0:-MRB-1111- SP=00000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 R0_BANK-R3_BANK 00000000 00000000 00000000 00000000 R4_BANK-R7_BANK 00000000 00000000 00000000 00000000 SSR=00000000 SPC=00000000
SH-2E series
REGISTER A(RET) PC=00000000 SR=000000F0:-1111- SP=00000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 FPUL=00000000 FPSCR=00040001:-D-RZ FR0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
FR8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 FR0- FR4- FR8-11 FR12-15 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00
Rev. 1.0, 09/99, page
REGISTER F(RET) PC=00000000 SR=000000F0:-1111- SP=00000000 FPUL=00000000 FPSCR=00040001:-D-RZ FR0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
FR8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 FR0- FR4- FR8-11 FR12-15 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00
REGISTER C(RET) PC=00000000 SR=000000F0:-1111- SP=00000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
SH-4 series
REGISTER A(RET) PC=00000000 SR=700000F0:-P1B-1111-F SP=00000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 R0_BANK-R3_BANK 00000000 00000000 00000000 00000000 R4_BANK-R7_BANK 00000000 00000000 00000000 00000000 SSR=00000000 SPC=00000000 DBR=00000000 SGR=00000000 PTEH=00000000 PTEL=00000000 TTB=00000000 TEA=00000000 MMUCR=00000000 EXPEVT=00000000 INTEVT=00000000 TRA=00000000 CCR=00000000 QACR0=00000000 QACR1=00000000 FPUL=00000000 FPSCR=00040001:-0SSZ-RZ FR0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
FR8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 FR0- FR4- FR8-11 FR12-15 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00
Rev. 1.0, 09/99, page
XF0-7
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
XF8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 XF0- XF4- XF8-11 XF12-15 DR0-6 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00
0000000000000000 0000000000000000 0000000000000000 0000000000000000
DR8-14 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ,DR2 ,DR6 0.000000000000000e+00 0.000000000000000e+00 0.000000000000000e+00 0.000000000000000e+00
,DR10 0.000000000000000e+00 0.000000000000000e+00 DR12,DR14 0.000000000000000e+00 0.000000000000000e+00 XD0-6 0000000000000000 0000000000000000 0000000000000000 0000000000000000
XD8-14 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ,XD2 ,XD6 0.000000000000000e+00 0.000000000000000e+00 0.000000000000000e+00 0.000000000000000e+00
,XD10 0.000000000000000e+00 0.000000000000000e+00 XD12,XD14 0.000000000000000e+00 0.000000000000000e+00
REGISTER F(RET) PC=00000000 SR=700000F0:-P1B-1111-F SP=00000000 FPUL=00000000 FPSCR=00040001:-0SSZ-RZ FR0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
FR8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 FR0- FR4- FR8-11 FR12-15 XF0-7 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
XF8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 XF0- XF4- XF8-11 XF12-15 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00
Rev. 1.0, 09/99, page
DR0-6
0000000000000000 0000000000000000 0000000000000000 0000000000000000
DR8-14 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ,DR2 ,DR6 0.000000000000000e+00 0.000000000000000e+00 0.000000000000000e+00 0.000000000000000e+00
,DR10 0.000000000000000e+00 0.000000000000000e+00 DR12,DR14 0.000000000000000e+00 0.000000000000000e+00 XD0-6 0000000000000000 0000000000000000 0000000000000000 0000000000000000
XD8-14 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ,XD2 ,XD6 0.000000000000000e+00 0.000000000000000e+00 0.000000000000000e+00 0.000000000000000e+00
,XD10 0.000000000000000e+00 0.000000000000000e+00 XD12,XD14 0.000000000000000e+00 0.000000000000000e+00
REGISTER C(RET) PC=00000000 SR=700000F0:-P1B-1111-F SP=00000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 R0_BANK-R3_BANK 00000000 00000000 00000000 00000000 R4_BANK-R7_BANK 00000000 00000000 00000000 00000000 SSR=00000000 SPC=00000000 DBR=00000000 SGR=00000000
Rev. 1.0, 09/99, page
4.44
RESET
RESET
Resets simulator/debugger
Format RESET(RET) Function Resets simulator/debugger. After this command executed, simulator/debugger follows: Pipeline: Reset Registers: Initialized follows: SH-1/SH-2/SH-DSP series H'F0 Others: SH-2E series H'F0 FPSCR: H'40001 Others: SH-3 H'700000F0 Others: SH-3E/SH-4 H'700000F0 FPSCR: H'40001 Others: Memory: memory settings cleared. User program: information concerning user program deleted, simulator/debugger assumes that program loaded. Command: command settings excluding RADIX command cleared initialized. Example reset simulator/debugger:
RESET(RET)
Rev. 1.0, 09/99, page
4.45
ROUND_MODE
Specifies displays floating-point rounding mode
ROUND_MODE
ROUND_MODE{Z|N}(RET) Format Set: Display: ROUND_MODE (RET) Parameter Rounding mode {Z|N} Rounds toward zero (default). Rounds nearest value. Function Specifies floating-point rounding mode.
Examples display current rounding mode:
ROUND_MODE(RET) ROUND ZERO
specify round-to-nearest mode:
ROUND_MODE N(RET)
Rev. 1.0, 09/99, page
4.46
SAVE_STATUS
Saves current simulator/debugger status file
SAVE_STATUS
Format SAVE_STATUS[<file name>](RET) Parameter <file name> Specifies name file which simulation status saved. When file name omitted, file sdsh.sav assumed. When file extension omitted, extension .sav added. Function Saves current simulation status file. Name program file which been loaded last information Default radix Memory setting information Trace condition Break information Register information Example save simulation state file test1.sav:
SAVE_STATUS test1.sav(RET)
Rev. 1.0, 09/99, page
4.47
STACK_ANALYSIS
Enables/disables resets stack analysis results
STACK_ANALYSIS
Format STACK_ANALYSIS{E|D|R}(RET) Parameter Enable/disable/reset {E|D|R} (enable): Enables stack analysis. (disable): Disables stack analysis. (reset): Resets stack analysis results. Function Enables/disables stack analysis resets analysis results. Description resetting, only analysis results reset stack analysis enable/disable setting changed. Examples enable stack analysis:
STACK_ANALYSIS E(RET)
reset stack analysis results:
STACK_ANALYSIS R(RET)
disable stack analysis:
STACK_ANALYSIS D(RET)
Rev. 1.0, 09/99, page
4.48
STACK_ANALYSIS_DISPLAY
Displays stack analysis results
STACK_ANALYSIS_DISPLAY
Format Parameters Displays program counter value (not displayed default). Displays maximum/minimum stack pointer values (not displayed default). Function Displays cycle count stack value when stack changed results stack analysis. When specified, program counter value when stack changed displayed. When specified, maximum minimum stack values displayed. Description Analyzes stack use. Saves changes values during program execution. buffer configured form ring stores 9999 data. When 10000 more data saved, buffer overwritten from head. Displayed items follows:
CYCLE
XXXXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXXXX XXXXXXXX XXXXXXXX CYCLE
XXXXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXXX XXXXXXXX XXXXXXXX
[CYCLE]: Cycle count [SP]: Stack pointer value [PC]: Program counter value [Max]: Displays maximum stack pointer value. [Min]: Displays minimum stack pointer value. Stack analysis disabled when simulator initiated.
Rev. 1.0, 09/99, page
Examples display stack analysis results:
STACK_ANALYSIS_DISPLAY(RET) CYCLE 10000 999998 00000FF0 00000900 00000FFC
display stack analysis results including maximum minimum program counter stack pointer values:
STACK_ANALYSIS_DISPLAY M(RET) CYCLE 10000 9999999999 CYCLE 9999999999 10000
00000FF0 000000F0 00000090 00000F00 00000FFC 00000FF0
00000FFC 00000FF0 00000090 00000F00
Rev. 1.0, 09/99, page
4.49
STATUS
STATUS
Displays simulator/debugger status
Format STATUS(RET) Function Displays type endian when simulator/debugger started, execution cycle count cache ratio when simulator/debugger stops. Display SH-1, SH-2, SH-2E, SH-DSP
CPU=xxx ENDIAN=xxxx CYCLE=xxxx
Display SH-3 SH-3E
CPU=xxx ENDIAN=xxxx CYCLE=xxxx
CACHE HIT=xx%
Display SH-4
CPU=xxx ENDIAN=xxxx CYCLE=xxxx
OPERAND CACHE HIT=xx%
INSTRUCTION CACHE HIT=xx%
type Endian Execution cycle count (10-digit decimal) Cache ratio (percentage) Instruction cache ratio (percentage) Operand cache ratio (percentage)
Rev. 1.0, 09/99, page
Examples display simulator/debugger status when type SH-1 endian specified startup.
STATUS (RET) CPU=SH1 ENDIAN=BIG CYCLE=128
display simulator/debugger status when type SH-3E endian specified startup.
STATUS (RET) CPU=SH3E ENDIAN=BIG CYCLE=4186
CACHE HIT=89%
display simulator/debugger status when type SH-4 little endian specified startup.
STATUS (RET) CPU=SH4 ENDIAN=LITTLE CYCLE=157353 OPERAND CACHE HIT=34%
INSTRUCTION CACHE HIT=89%
Rev. 1.0, 09/99, page
4.50
STEP
STEP
Performs step execution (executes subroutine step)
Format STEP[<step count>][R](RET) Parameters <step count> Specifies number instruction execution steps. (H'1 H'FFFF) When omitted, step executed. Register content display (register): Displays contents registers after instruction execution. Function Executes instructions time starting current program counter specified number steps. Description Displays mnemonic executed instruction each time instruction executed. option specified, contents register after instruction execution also displayed. subroutine branched BSR, BSRF instruction, execution performed from start subroutine instruction following instruction (since delay branch instruction) step. Execution stops when break condition break command satisfied error detected simulator/debugger. this case, stop cause displayed. Example execute five instructions, executing subroutine though were single instruction:
STEP (RET) 00000000 00000002 00000004 00000006 00000008 MOV.L MOV.L LDS.L @R15+, R3,@R14 @(H'0084:8,PC),
5000 Step normal
Rev. 1.0, 09/99, page
4.51
STEP_G
STEP_G
Specifies step execution address range executing subroutine step
Format STEP_G<start address><end address>[R](RET) Parameters <start address> Specifies dummy start address (H'0 H'FFFFFFFF). this simulator/debugger, start address step execution range always current value regardless this setting. <end address> Specifies address step execution range. Register content display (register): Displays contents register after step execution. Function Executes instructions time from current address address. Description Displays mnemonic last executed instruction. option specified, contents register after instruction execution also displayed. subroutine branched BSR, BSRF instruction, execution performed from start subroutine instruction following instruction (since delay branch instruction) step. Execution stops when break condition break command satisfied error detected simulator/debugger. this case, stop cause displayed. relationship between start addresses follows: When address value, last make even value (ANDing with 0xfffffffe make even value). Examples: 100, ffff fffe When current address address, step execution performed current address step. When current address address, step execution performed current address step. When current address address, step execution performed from current address address. Step execution stops when value becomes outside range from current addresses address (except during subroutine execution).
Rev. 1.0, 09/99, page
Example perform step execution from current address address H'8:
STEP_G (RET) 00000008 LDS.L @R15+,PR
5000 Step normal
Rev. 1.0, 09/99, page
4.52
STEP_INTO
Performs step execution
STEP_INTO
Format STEP_INTO[<step count>][R](RET) Parameters <step count> Specifies number instruction execution steps. (H'1 H'FFFF) When omitted, step executed. Register content display (register): Displays contents registers after instruction execution. Function Executes instructions time starting current program counter specified number steps. When subroutine called program, called subroutine also executed step time. Description Displays mnemonic executed instruction each time instruction executed. option specified, contents register after instruction execution also displayed. Execution stops when break condition break command satisfied error detected simulator/debugger. this case, stop cause displayed.
Rev. 1.0, 09/99, page
Examples execute instruction then display mnemonic executed instruction contents registers following instruction execution (For SH-3):
STEP_INTO R(RET) PC=00001002 SR=700000F0:-MRB-IIII- SP=00000000 GBR=00000000 VBR=00000000 MACH=00000000 MACL=00000000 PR=00000000 R0-7 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R8-15 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 R0_BANK-R3-BANK 00000000 00000000 00000000 00000000 R4_BANK-R7-BANK 00000000 00000000 00000000 00000000 SSR=00000000 SPC=00000000 PTEH=00000000 PTEL=00000000 TTB=00000000 TEA=00000000 MMUCR=00000000 EXPEVT=00000000 INTEVT=00000000 TRA=00000000 CCR=00000000 00001000 #H'00,R3
+++5000 Step normal
execute three instructions:
STEP_INTO 3(RET) 00000404 00000406 00000408 MOV.L MOV.L ADD.L #0000002E,R4 #FFFFFFFF,R3 R1,R2
+++5000 Step normal
Rev. 1.0, 09/99, page
4.53
STEP_INTO_G
Specifies step execution range
STEP_INTO_G
Format STEP_INTO_G<start address><end address>[R](RET) Parameters <start address> Specifies dummy start address (H'0 H'FFFFFFFF). this simulator/debugger, start address step execution range always current value regardless this setting. <end address> Specifies address step execution range. Register content display (register): Displays contents register after instruction execution. Function Executes instructions time from current address address. When subroutine called program, called subroutine also executed step time. Description Displays mnemonic instruction which been executed last. option specified, contents register after instruction execution also displayed. When subroutine called program, called subroutine also executed step time. Execution stops when break condition break command satisfied error detected simulator/debugger. this case, stop cause displayed. relationship between start addresses follows: When address value, last make even value (ANDing with 0xfffffffe make even value). Examples: 100, ffff fffe When current address address, step execution performed current address step. When current address address, step execution performed current address step. When current address address, step execution performed from current address address. Step execution stops when value becomes outside range from current addresses address (also during subroutine execution).
Rev. 1.0, 09/99, page
Example perform step execution from current address address H'6:
STEP_INTO_G 6(RET) 00000006 ADD.L R1,R2
+++5000 Step normal
Rev. 1.0, 09/99, page
4.54
(Only SH-3/SH-3E/SH-4 Series)
Modifies contents
Format SH-3 SH3E Modification: TLB<index><way>[<AA data>][:<DA data>](RET) Interactive mode: TLB<index><way>(RET) SH-4 Modification: TLB[{I|U}]<entry>[<AA data>][:<DA data>](RET) Interactive mode: TLB[{I|U}]<entry>(RET) Parameters <index> Specifies index modified. (H'00 H'1F) <way> Specifies modified. (H'0 H'3) data> Specifies data written into address array. data> Specifies data written into data array. type modified {I|U} Specifies instruction (ITLB) (default). Specifies unified (UTLB). <entry> Specifies entry modified. Function Modifies contents.
Rev. 1.0, 09/99, page
Description Modification (direct): Modifies contents with specified data. Modification (interactive mode): modification data data) omitted, contents modified interactively using following formats. Displays current data, requests modification data input. SH-3 SH-3E
TLB<index><way>(RET) aaaaaaaa/dddddddd [<AA data>][:<DA data>](RET) aaaaaaaa/dddddddd
(1): Index (2-digit hexadecimal) (2): (1-digit hexadecimal) (3): Current address array data (8-digit hexadecimal) (4): Current data array data (8-digit hexadecimal) SH-4
TLB<entry>(RET) aaaaaaaa/dddddddd [<AA data>][:<DA data>](RET) aaaaaaaa/dddddddd
(1): Entry (2-digit hexadecimal) (2): Current address array data (8-digit hexadecimal) (3): Current data array data (8-digit hexadecimal) following entered instead modification data: .(period): Terminates command. Returns previous entry. (RET) only: Goes next entry.
Rev. 1.0, 09/99, page
Examples modify entry index SH-3:
00000000 00000000(RET)
modify contents sequentially from entry index SH-3:
0(RET) 00000000/00000000 00000101 00000500 (RET) 00000000/00000000 00000101 00000900 (RET) 00000000/00000000 (RET) 00000000/00000000 ^(RET) 00000000/00000000 00000101 00001100 (RET) 00000000/00000000 00000101 00001100 (RET) 00000000/00000000 .(RET)
Rev. 1.0, 09/99, page
4.55
TLB_DUMP (Only SH-3/SH-3E/SH-4 Series)
Displays contents
TLB_DUMP TLBD
Format
SH-3 SH3E TLB_DUMP(RET) SH-4 TLB_DUMP[{I|U}](RET)
{I|U} Parameter type displayed Specifies instruction (ITLB) (default). Specifies unified (UTLB). Function Displays contents address data arrays. Description Displays contents following formats: SH-3 SH-3E
<NO> <WAY0> <WAY1> <WAY2> <WAY3>
aaaaaaaa/dddddddd aaaaaaaa/dddddddd aaaaaaaa/dddddddd aaaaaaaa/dddddddd
(1): Index (2-digit hexadecimal) (2): Current address array data (8-digit hexadecimal) Bits (five bits) always (3): Current data array data (8-digit hexadecimal) SH-4
<NO> <ADDR ARRAY> <DATA ARRAY> aaaaaaaa/dddddddd
(1): Entry (2-digit hexadecimal) (2): Address array data (8-digit hexadecimal) (3): Data array data (8-digit hexadecimal)
Rev. 1.0, 09/99, page
Example display contents indexes SH-3:
TLB_DUMP(RET) <NO> <WAY0> <WAY1> <WAY2> <WAY3>
00000000/00000000 00000000/00000000 00000000/00000000 00000000/00000000 00000000/00000000 00000000/00000000 00000000/00000000 00000000/00000000
00000000/00000000 00000000/00000000 00000000/00000000 00000000/00000000
Rev. 1.0, 09/99, page
4.56
TLB_FLUSH (Only SH-3/SH-3E/SH-4 Series)
Flushes contents
TLB_FLUSH TLBF
Format
SH-3/SH-3E series TLB_FLUSH(RET) SH-4 series TLB_FLUSH[{I|U}](RET)
Parameters Type flush {I|U} Specifies instruction (ITLB). (Default) Specifies unified (UTLB). Function Flushes contents. Example flush contents SH3:
TLB_FLUSH(RET)
Rev. 1.0, 09/99, page
4.57 TLB_SEARCH (Only SH-3/SH-3E/SH-4 Series)
TLB_S
Other recent searches
SN74BCT8244A - SN74BCT8244A SN74BCT8244A Datasheet
SN54BCT8244A - SN54BCT8244A SN54BCT8244A Datasheet
PD17145 - PD17145 PD17145 Datasheet
PD17145U10261J - PD17145U10261J PD17145U10261J Datasheet
MP725 - MP725 MP725 Datasheet
Max220 - Max220 Max220 Datasheet
Max220I - Max220I Max220I Datasheet
LMH6678 - LMH6678 LMH6678 Datasheet
IMP803 - IMP803 IMP803 Datasheet
CDB4391A - CDB4391A CDB4391A Datasheet
BAW56 - BAW56 BAW56 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
