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DESCRIPTIO Sample Rate: 800ksps Power Dissipation: 80mW 72.5dB S/


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LTC1409 12-Bit, 800ksps Sampling Converter with Shutdown
DESCRIPTIO
Sample Rate: 800ksps Power Dissipation: 80mW 72.5dB S/(N 86dB Nyquist Pipeline Delay (4mW) Sleep (10µW) Shutdown Modes Operates with Internal 15ppm/°C Reference External Reference True Differential Inputs Reject Common Mode Noise 20MHz Full Power Bandwidth Sampling ±2.5V Bipolar Input Range 28-Pin Wide SSOP Package
®1409 1µs, 800ksps, sampling 12-bit converter that draws only 80mW from supplies. This easy-to-use device includes high dynamic range sampleand-hold precision reference. digitally selectable power Shutdown modes provide flexibility power systems. LTC1409 full-scale input range ±2.5V. Maximum specs include ±1LSB ±1LSB over temperature. Outstanding performance includes 72.5dB S/(N Nyquist input frequency 400kHz. unique differential input sample-and-hold acquire single-ended differential input signals 20MHz bandwidth. 60dB common mode rejection allows users eliminate ground loops common mode noise measuring signals differentially from source. compatible, 12-bit parallel output port. There pipeline delay conversion results. separate convert start input data ready signal (BUSY) ease connections FIFOs, DSPs microprocessors. digital output driver power supply allows direct connection logic.
APPLICATI
Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems
registered trademarks Linear Technology Corporation.
TYPICAL APPLICATI
800kHz, 12-Bit Sampling Converter
LTC1409 DIFFERENTIAL AVDD +AIN ANALOG INPUT (-2.5V 2.5V) -AIN OVDD 2.50V VREF OUTPUT REFCOMP BUSY 10µF AGND D11(MSB) CONVST SHDN NAP/SLP OGND 12-BIT PARALLEL DGND CONTROL LINES 10µF
Effective Bits Signal-to-(Noise Distortion) Input Frequency
10µF
EFFECTIVE BITS
fSAMPLE 800ksps 100k INPUT FREQUENCY (Hz)
LTC1409 TA01
NYQUIST FREQUENCY
S/(N (dB)
LTC1409 TA02
LTC1409 ABSOLUTE RATI
PACKAGE/ORDER ATIO
VIEW +AIN -AIN VREF REFCOMP AGND D11(MSB) DGND PACKAGE 28-LEAD PLASTIC AVDD OVDD BUSY CONVST SHDN NAP/SLP OGND PACKAGE 28-LEAD PLASTIC WIDE
AVDD OVDD (Notes
Supply Voltage (VDD) Negative Supply Voltage (VSS). Total Supply Voltage (VDD VSS) Analog Input Voltage (Note 0.3V 0.3V Digital Input Voltage (Note 0.3V Digital Output Voltage 0.3V 0.3V Power Dissipation. 500mW Operating Temperature Range LTC1409C. 70°C LTC1409I. 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1409CG LTC1409CSW LTC1409IG LTC1409ISW
TJMAX 110°C, 95°C/W TJMAX 110°C, 130°C/W (SW)
Consult factory Military grade parts.
VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco IOUT(REF) (Note (Note CONDITIONS
With Internal Reference (Notes
±0.3 ±0.3
UNITS Bits ppm/°C
ALOG
SYMBOL PARAMETER tACQ tjitter CMRR
(Note
CONDITIONS 4.75V 5.25V, 5.25V 4.75V High Between Conversions During Conversions
±2.5
UNITS
Analog Input Range (Note Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio
-1.5
psRMS
2.5V (-AIN +AIN) 2.5V
LTC1409
ACCURACY
SYMBOL S/(N PARAMETER
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance REFCOMP Output Voltage CONDITIONS IOUT IOUT 4.75V 5.25V 5.25V 4.75V 0.1mA |IOUT| 0.1mA IOUT
DIGITAL PUTS DIGITAL OUTPUTS
SYMBOL PARAMETER High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage 4.75V 10µA 200µA 4.75V 160µA 1.6mA VOUT VDD, High High (Note VOUT VOUT CONDITIONS 5.25V 4.75V
Level Output Voltage
ISOURCE ISINK
High-Z Output Leakage High-Z Output Capacitance Output Source Current Output Sink Current
POWER REQUIRE
SYMBOL PARAMETER Positive Supply Voltage Negative Supply Voltage Positive Supply Current Mode Sleep Mode
(Note
CONDITIONS
73.0 72.5
UNITS
Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal (Note 400kHz Input Signal (Note Total Harmonic Distortion Peak Harmonic Spurious Noise Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth S/(N 68dB 100kHz Input Signal, First Five Harmonics 400kHz Input Signal, First Five Harmonics 400kHz Input Signal fIN1 29.37kHz, fIN2 32.446kHz
(Note
2.480 2.500 0.01 0.01 4.06 2.520 UNITS ppm/°C LSB/V LSB/V
(Note
UNITS
0.05 0.10
(Note
4.75 4.75 5.25 5.25 UNITS
CONDITIONS (Notes (Note High CONVST SHDN NAP/SLP CONVST SHDN NAP/SLP
LTC1409
POWER REQUIRE
SYMBOL PARAMETER Negative Supply Current Mode Sleep Mode Power Dissipation Mode Sleep Mode
PDISS
CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Setup Time CONVST Setup Time NAP/SLP SHDN Setup Time CONVST Time CONVST BUSY Delay Data Ready Before BUSY
SHDN CONVST Wake-Up Time (Note (Notes 25pF
Delay Between Conversions Wait Time After BUSY Data Access Time After
Relinquish Time 70°C 40°C 85°C Time CONVST High Time Aperture Delay Sample-and-Hold
indicates specifications which apply over full operating temperature range; other limits typicals 25°C. Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect ground with DGND AGND wired together (unless otherwise noted). Note When these voltages taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below above without latch-up. Note When these voltages taken below they will clamped internal diodes. This product handle input currents greater than 100mA below without latchup. These pins clamped VDD.
(Note
0.01 UNITS
CONDITIONS High CONVST SHDN NAP/SLP CONVST SHDN NAP/SLP
CONVST SHDN NAP/SLP CONVST SHDN NAP/SLP
(Note
CONDITIONS
1250
UNITS
(Notes (Notes (Notes
(Note 25pF
100pF
Note fSAMPLE 800kHz, unless otherwise specified. Note Linearity, offset full-scale specifications apply singleended +AIN input with -AIN grounded. Note Integral nonlinearity defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Bipolar offset offset voltage measured from 0.5LSB when output code flickers between 0000 0000 0000 1111 1111 1111. Note Guaranteed design, subject test. Note Recommended operating conditions.
LTC1409
CHARACTERISTICS
Note falling CONVST edge starts conversion. CONVST returns high critical point during conversion create small errors. best results ensure that CONVST returns high either within 650ns after conversion start after BUSY rises. Note Signal-to-noise ratio (SNR) measured 100kHz distortion measured 400kHz. These results used calculate signal-to-noise plus distortion (SINAD).
TYPICAL PERFORMANCE CHARACTERISTICS
S/(N Input Frequency Amplitude
SIGNAL/(NOISE DISTORTION) (dB)
AMPLITUDE BELOW FUNDAMENTAL)
SIGNAL/(NOISE DISTORTION) (dB)
20dB
60dB
100k INPUT FREQUENCY (Hz)
Spurious-Free Dynamic Range Input Frequency
SPURIOUS-FREE DYNAMIC RANGE (dB)
-100
AMPLITUDE (dB)
100k INPUT FREQUENCY (Hz)
Signal-to-Noise Ratio Input Frequency
-100 100k INPUT FREQUENCY (Hz)
Distortion Input Frequency
100k INPUT FREQUENCY (Hz)
LTC1409 TPC01
LTC1409 TPC02
LTC1409 TPC03
Intermodulation Distortion Plot
fSAMPLE 800kHz fIN1 88.19580078kHz fIN2 111.9995117kHz
-100 -120
LTC1409 TPC04
100k
150k
200k FREQUENCY (Hz)
250k
300k
350k
400k
LTC1409 TPC05
LTC1409 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity Output Code
1.00 1.00
0.50
ERROR (LSB) ERROR (LSB)
-0.50
-1.00 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
LT1409 TPC07
AMPLITUDE POWER SUPPLY FEEDTHROUGH (dB)
Power Supply Feedthrough Ripple Frequency
-100 100k RIPPLE FREQUENCY (Hz) DGND
COMMON MODE REJECTION (dB)
CTIO
(Pin Positive Analog Input, ±2.5V. (Pin Negative Analog Input, ±2.5V. VREF (Pin 2.50V Reference Output. REFCOMP (Pin 4.06V Reference Output. Bypass AGND using 10µF tantalum parallel with 0.1µF 10µF ceramic. AGND (Pin Analog Ground. (Pins 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground Internal Logic. AGND. (Pins 18): Three-State Data Outputs. OGND (Pin 19): Digital Ground Output Drivers. AGND. NAP/SLP (Pin 20): Power Shutdown Mode. Selects mode invoked SHDN pin. selects Sleep mode high selects quick wake-up mode. SHDN (Pin 21): Power Shutdown Input. logic level will invoke Shutdown mode selected NAP/SLP pin. (Pin 22): Read Input. This enables output drivers when low.
Differential Nonlinearity Output Code
0.50
-0.50
-1.00 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
LT1409 TPC06
Input Common Mode Rejection Input Frequency
100k INPUT FREQUENCY (Hz)
LT1409 TPC09
LTC1409 TPC08
LTC1409
CTIO
CONVST (Pin 23): Conversion Start Signal. This active signal starts conversion falling edge. (Pin 24): Chip Select. input must recognize CONVST inputs. BUSY (Pin 25): BUSY output shows converter status. when conversion progress. Data valid rising edge BUSY. (Pin 26): Negative Supply. Bypass AGND using 10µF tantalum parallel 0.1µF 10µF ceramic. OVDD (Pin 27): Positive Supply Output Drivers. logic, short logic, short supply logic being driven. AVDD (Pin 28): Positive Supply. Bypass AGND 10µF tantalum parallel with 0.1µF 10µF ceramic.
CTIO BLOCK DIAGRA
+AIN
VREF 2.5V ZEROING SWITCHES
12-BIT CAPACITIVE
REFCOMP (4.06V) AGND DGND INTERNAL CLOCK SUCCESSIVE APPROXIMATION REGISTER
NAP/SLP SHDN
TEST CIRCUITS
Load Circuits Access Timing
LTC1409 TC01
Hi-Z
Hi-Z
CSAMPLE
CSAMPLE
AVDD
COMP
OVDD OUTPUT LATCHES OGND CONTROL LOGIC
LTC1409
CONVST
BUSY
Load Circuits Relinquish Time
100pF 100pF
LTC1409 TC02
Hi-Z
Hi-Z
LTC1409
APPLICATIONS INFORMATION
CONVERSION DETAILS LTC1409 uses successive approximation algorithm internal sample-and-hold circuit convert analog signal 12-bit parallel output. complete with precision reference internal clock. control logic provides easy interface microprocessors DSPs. (Please refer Digital Interface section data format.) Conversion start controlled CONVST inputs. start conversion successive approximation register (SAR) reset. Once conversion cycle begun cannot restarted. During conversion, internal differential 12-bit capacitive output sequenced from most significant (MSB) least significant (LSB). Referring Figure +AIN -AIN inputs connected sample-and-hold capacitors (CSAMPLE) during acquire phase comparator offset nulled zeroing switches. this acquire phase, minimum delay 150ns will provide enough time sample-and-hold capacitors acquire analog signal. During convert phase comparator zeroing switches open, putting comparator into compare mode. input switches connect CSAMPLE capacitors ground, transferring differential analog input charge onto summing junction. This input charge successively compared with binary-weighted charges supplied
+CSAMPLE +AIN HOLD -CSAMPLE -AIN HOLD +CDAC
AMPLITUDE (dB)
AMPLITUDE (dB)
ZEROING SWITCHES HOLD
HOLD
+VDAC -CDAC COMP
-100
-VDAC
OUTPUT LATCHES
LTC1409
Figure Simplified Block Diagram
differential capacitive DAC. decisions made high speed comparator. conversion, differential DACs output balances +AIN -AIN input charges. contents 12-bit data word) which represents difference +AIN -AIN loaded into 12-bit output latches. DYNAMIC PERFORMANCE LTC1409 excellent high speed sampling capability. (Fast Four Transform) test techniques used test ADC's frequency response, distortion noise rated throughput. applying distortion sine wave analyzing digital output using algorithm, ADC's spectral content examined frequencies outside fundamental. Figure shows typical LTC1409 plots.
-100 -120 LT1409 F02a FREQUENCY (kHz) fSAMPLE 800kHz 97.45kHz SFDR 89.1dB SINAD 73.1dB
Figure LTC1409 Nonaveraged, 4096 Point FFT, Input Frequency 100kHz
fSAMPLE 800kHz 375kHz SFDR 89dB SINAD 72.5dB
-120 FREQUENCY (kHz) LT1409 F02b
Figure LTC1409 Nonaveraged, 4096 Point FFT, Input Frequency 375kHz
LTC1409
APPLICATIONS INFORMATION
Signal-to-Noise Ratio signal-to-noise plus distortion ratio [S/(N ratio between amplitude fundamental input frequency amplitude other frequency components output. output band limited frequencies from above below half sampling frequency. Figure shows typical spectral content with 800kHz sampling rate 100kHz input. dynamic performance excellent input frequencies beyond Nyquist limit 400kHz. Effective Number Bits Effective Number Bits (ENOBs) measurement resolution directly related S/(N equation: [S/(N 1.76]/6.02 where effective number bits resolution S/(N expressed maximum sampling rate 800kHz LTC1409 maintains near ideal ENOBs Nyquist input frequency 400kHz. Refer Figure
EFFECTIVE BITS
AMPLITUDE BELOW FUNDAMENTAL)
fSAMPLE 800kHz 100k INPUT FREQUENCY (Hz)
LTC1409
Figure Effective Bits Signal/(Noise Distortion) Input Frequency
Total Harmonic Distortion Total Harmonic Distortion (THD) ratio harmonics input signal fundamental itself. out-of-band harmonics alias into frequency band between half sampling frequency. expressed
.Vn2 where amplitude fundamental frequency through amplitudes second through harmonics. input frequency shown Figure LTC1409 good distortion performance Nyquist frequency beyond.
-100 100k INPUT FREQUENCY (Hz)
LTC1409
Figure Distortion Input Frequency
Intermodulation Distortion input signal consists more than spectral component, transfer function nonlinearity produce intermodulation distortion (IMD) addition THD. change sinusoidal input caused presence another sinusoidal input different frequency. pure sine waves frequencies applied input, nonlinearities transfer function create distortion products difference frequencies -nfb, where etc. example, order terms include fb). input sine waves equal magnitude, value decibels) order products expressed following formula:
IMD( Amplitude Amplitude
Peak Harmonic Spurious Noise peak harmonic spurious noise largest spectral component excluding input signal This
LTC1409
APPLICATIONS INFORMATION
AMPLITUDE (dB)
-100 -120 100k 150k 200k FREQUENCY (Hz) 250k 300k 350k 400k
LTC1409
Figure Intermodulation Distortion Plot
value expressed decibels relative value full-scale input signal. Full Power Full Linear Bandwidth full power bandwidth that input frequency which amplitude reconstructed fundamental reduced full-scale input signal. full linear bandwidth input frequency which S/(N dropped 68dB effective bits). LTC1409 been designed optimize input bandwidth, allowing undersample input signals with frequencies above converter's Nyquist Frequency. noise floor stays very high frequencies; S/(N becomes dominated distortion frequencies beyond Nyquist. Driving Analog Input differential analog inputs LTC1409 easy drive. inputs driven differentially single-ended input (i.e., -AIN input grounded). +AIN -AIN inputs sampled same instant. unwanted signal that common mode both inputs will reduced common mode rejection sample-and-hold circuit. inputs draw only small current spike while charging sample-and-hold capacitors conversion. During conversion analog inputs draw only small leakage current. source impedance driving circuit then LTC1409 inputs driven directly. source impedance increases will acquisition time (see Figure
ACQUISITION TIME (µs)
fSAMPLE 800kHz fIN1 88.19580078kHz fIN2 111.9995117kHz
minimum acquisition time, with high source impedance, buffer amplifier should used. only requirement that amplifier driving analog input(s) must settle after small current spike before next conversion starts (settling time must 150ns full throughput rate).
0.01 0.01
SOURCE RESISTANCE
LTC1409
Figure Acquisition Time Source Resistance
Choosing Input Amplifier Choosing input amplifier easy requirements taken into consideration. First, limit magnitude voltage spike seen amplifier from charging sampling capacitor, choose amplifier that output impedance 100) closed-loop bandwidth frequency. example, amplifier used gain unity-gain bandwidth 50MHz, then output impedance 50MHz should less than 100. second requirement that closed-loop
LTC1409
APPLICATI
ATIO
bandwidth must greater than 20MHz ensure adequate small-signal settling full throughput rate. slower amps used, more settling time provided increasing time between conversions. best choice drive LTC1409 will depend application. Generally applications fall into categories: applications where dynamic specifications most critical, time domain applications where accuracy settling time most critical. following list summary amps that suitable driving LTC1409, more detailed information available Linear Technology databooks LinearViewCD-ROM. 1220: 30MHz unity-gain bandwidth voltage feedback amplifier. ±15V supplies. Excellent specifications, 90ns settling 0.5LSB. LT1223: 100MHz video current feedback amplifier. supply current. ±15V supplies. distortion above 400kHz. noise. Good applications. LT1227: 140MHz video current feedback amplifier. 10mA supply current ±15V supplies. Lowest distortion frequencies above 400kHz. noise. Best applications. LT1229/LT1230: Dual quad 100MHz current feedback amplifiers. ±15V supplies. noise. Good specs. supply current each amplifier. LT1360: 37MHz voltage feedback amplifier. 3.8mA supply current. Good AC/DC specs. ±15V supplies. 70ns settling 0.5LSB. LT1363: 50MHz, 450V/µs amps. 6.3mA supply current. Good AC/DC specs. 60ns settling 0.5LSB. LT1364/LT1365: Dual quad 50MHz, 450V/µs amps. 6.3mA supply current amplifier. 60ns settling 0.5LSB. Input Filtering noise distortion input amplifier other circuitry must considered since they will LTC1409 noise distortion. small-signal bandLinearView trademark Linear Technology Corporation.
width sample-and-hold circuit 20MHz. noise distortion products that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter sufficient many applications. example, Figure shows 1000pF capacitor from ground source resistor limit input bandwidth 1.6MHz. 1000pF capacitor also acts charge reservoir input sample-and-hold isolates input from sampling glitch sensitive circuitry. High quality capacitors resistors should used since these components distortion. silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors also generate distortion from self heating from damage that occur during soldering. Metal film surface mount resistors much less susceptible both problems. When high amplitude unwanted signals close frequency desired signal frequency, multiple pole filter
ANALOG INPUT 1000pF -AIN LTC1409 VREF +AIN 10µF AGND
LTC1409 F07b
REFCOMP
Figure Input Filter
0.1µF LTC1560-1
+AIN
-AIN LTC1409
0.1µF 10µF
VREF
REFCOMP
AGND
LTC1409
Figure 500kHz Order Elliptic Lowpass Filter
LTC1409
APPLICATI
ATIO
required. Figure shows simple implementation using LTC1560 order elliptic continuous time filter. Input Range ±2.5V input range LTC1409 optimized noise distortion. Most amps also perform best over this same range, allowing direct coupling analog inputs eliminating need special translation circuitry. Some applications require other input ranges. LTC1409 differential inputs reference circuitry accommodate other input ranges often with little additional circuitry. following sections describe reference input circuitry they affect input range. Internal Reference LTC1409 on-chip, temperature compensated, curvature corrected, bandgap reference that factory trimmed 2.500V. connected internally reference amplifier available VREF (Pin Figure resistor series with output that easily overdriven external reference other circuitry. reference amplifier gains voltage VREF 1.625 create required internal reference voltage. This provides buffering between VREF high speed capacitive DAC. reference amplifier compensation pin, REFCOMP (Pin must bypassed with capacitor ground. reference amplifier stable with capacitors greater. best noise performance, 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic recommended (see Figure 8b).
2.5V BANGAP REFERENCE
4.0625V
REFCOMP
REFERENCE
10µF
AGND
LTC1409
LTC1409 F08a
Figure LTC1409 Reference Circuit
LT1019A-2.5 VOUT ANALOG INPUT -AIN LTC1409 VREF +AIN 10µF AGND
LTC1409 F08b
REFCOMP
Figure Using LT1019-2.5 External Reference
VREF driven with other means shown Figure This useful applications where peak input signal amplitude vary. input span then adjusted match peak input signal, maximizing signal-to-noise ratio. filtering internal LTC1409 reference amplifier will limit bandwidth settling time this circuit. settling time should allowed for, after reference adjustment.
ANALOG INPUT LTC1450 12-BIT RAIL-TO-RAIL -AIN LTC1409 1.25V VREF +AIN
10µF
REFCOMP
AGND
LTC1409
Figure 9.Driving VREF with
Differential Inputs LTC1409 unique differential sample-and-hold circuit that allows rail-to-rail inputs. will always convert difference +AIN (-AIN) independent common mode voltage. common mode rejection holds extremely high frequencies, Figure 10a. only requirement that both inputs exceed AVDD power supply voltages. Integral nonlinearity errors (INL) differential nonlinearity errors (DNL) independent common mode voltage,
LTC1409
APPLICATI
ATIO
COMMON MODE REJECTION (dB)
1000 INPUT FREQUENCY (Hz) 10000
OUTPUT CODE
LTC1409 TPC09
Figure 10a. CMRR Input Frequency
ANALOG INPUT ±2.5V RANGE RANGE -AIN LTC1409 2.5V 10µF AGND
LTC1409 F10b
+AIN
VREF
REFCOMP
Figure 10b. Selectable ±2.5V Input Range
however, bipolar zero error (BZE) will vary. change typically less than 0.1% common mode voltage. Dynamic performance also affected common mode voltage. will degrade inputs approach either power supply rail, from 86dB with common mode 75dB with common mode 2.5V 2.5V. Differential inputs allow greater flexibility accepting different input ranges. Figure shows circuit that converts analog input signal with additional translation circuitry. Full-Scale Offset Adjustment Figure shows ideal input/output characteristics LTC1409. code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB,. 1.5LSB, 0.5LSB).
output two's complement binary with 1LSB FS)/4096 5V/4096 1.22mV.
111.111 111.110 111.101 000.010 000.001 000.000 -(FS 1LSB) INPUT RANGE
LTC1409 F11a
1LSB
Figure 11a. LTC1409 Transfer Characteristics
ANALOG INPUT
+AIN
-AIN LTC1409
10µF
VREF
REFCOMP
AGND
LTC1409 F11b
Figure 11b. Offset Full-Scale Adjust Circuit
applications where absolute accuracy important, offset full-scale errors adjusted zero. Offset error must adjusted before full-scale error. Figure shows extra components required full-scale error adjustment. Zero offset achieved adjusting offset applied input. zero offset error apply 0.61mV (i.e., 0.5LSB) +AIN adjust offset input until output code flickers between 0000 0000 0000 1111 1111 1111. full-scale adjustment, input voltage 2.49817V (FS/2 1.5LSBs) applied adjusted until output code flickers between 0111 1111 1110 0111 1111 1111.
LTC1409
APPLICATI
ATIO
BOARD LAYOUT BYPASSING Wire wrap boards recommended high resolution high speed converters. obtain best performance from LTC1409, printed circuit board with ground plane required. Layout printed circuit board should ensure that digital analog signal lines separated much possible. particular, care should taken digital track alongside analog signal track. analog ground plane separate from logic system ground should established under around ADC. (AGND), (ADC's DGND) other analog grounds should connected this single analog ground point. REFCOMP bypass capacitor OVDD bypass capacitor should also connected this analog ground plane. other digital grounds should connected this analog ground plane. impedance analog digital power supply common returns essential noise operation foil width these tracks should wide possible. applications where data outputs control signals connected continuously active microprocessor bus, possible errors conversion results. These errors feedthrough from microprocessor successive approximation comparator. problem eliminated forcing microprocessor into WAIT state during conversion using three-state buffers isolate data bus. traces connecting pins bypass capacitors must kept short should made wide possible.
ANALOG INPUT CIRCUITRY
+AIN -AIN REFCOMP AGND 10µF 0.1µF
10µF 0.1µF
ANALOG GROUND PLANE
Figure Power Supply Grounding Practice
LTC1409 differential inputs minimize noise coupling. Common mode noise +AIN -AIN leads will rejected input CMRR. -AIN input used ground sense +AIN input; LTC1409 will hold convert difference voltage between +AIN -AIN. leads +AIN (Pin -AIN (Pin should kept short possible. applications where this possible, +AIN -AIN traces should sideby-side equalize coupling. SUPPLY BYPASSING High quality, series resistance ceramic, 10µF bypass capacitors should used REFCOMP pins shown Typical Application first page this data sheet. Surface mount ceramic capacitors such Murata GRM235Y5V106Z016 provide excellent bypassing small board space. Alternatively 10µF tantalum capacitors parallel with 0.1µF ceramic capacitors used. Bypass capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible. Example Layout Figure 13a, 13b, show schematic layout suggested evaluation board. layout demonstrates proper decoupling capacitors ground plane with layer printed circuit board.
LTC1409 AVDD OVDD DGND OGND DIGITAL SYSTEM
LTC1409
10µF 0.1µF
79L05 SS12 10µF OP-AMP DECOUPLING 0.1µF 0.1µF 0.1µF DIGITAL I.C. BYPASSING -15V
LT1121
DATA 15pF
D(0.11) LTC1410 LT1360
ATIO
REFCOMP AGND DGND SHDN CONVST BUSY DVDD AVDD NAP/SLP OGND 74HC374 10µF VREF -AIN +AIN
0.001µF
VREF VREF
0.1µF
0.1µF
74HC14
74HC14
NOTE
/D11 74HC14
74HC374
10µF 0.1µF 10µF
0.1µF
NOTES: UNLESS OTHERWISE SPECIFIED. RESISTOR VALUE OHMS, 1/8W, SMT. CAPACITOR VALUES 50V, 20%, SMT. REPLACED WITH 10µF, 25V, Z5U, CERAMIC
74HC14
LTC1409
Figure 13a. Suggested Evaluation Circuit Schematic
74HC14
74HC14
APPLICATI
22µF
SS12
22µF
0.1µF 0.1µF
LTC1409
APPLICATI
ATIO
Figure 13b. Suggested Evaluation Circuit Board Component Side Silkscreen
Figure 13c. Suggested Evaluation Circuit Board Component Side Layout
LTC1409
APPLICATI
ATIO
Figure 13d. Suggested Evaluation Circuit Board Solder Side Layout
Digital Interface converter designed interface with microprocessors memory mapped device. control inputs common peripheral memory interfacing. separate CONVST used initiate conversion. Internal Clock converter internal clock that eliminates need synchronization between external clock signals found other ADCs. internal clock factory trimmed achieve typical conversion time 0.9µs, maximum conversion time over full operating temperature range 1.15µs. external adjustments required. guaranteed maximum acquisition time 150ns. addition, throughput time 1250ns minimum sample rate 800ksps guaranteed. Power Shutdown LTC1409 provides power Shutdown modes, Sleep, save power during inactive periods. mode reduces power leaves only digital logic reference powered wake-up time
from active 200ns. Sleep mode bias currents shut down only leakage current remains, about 1µA. Wake-up time from Sleep mode much slower since reference circuit must power settle 0.01% full 12-bit accuracy. Sleep mode wake-up time dependent value capacitor connected REFCOMP (Pin wake-up time 10ms with recommended 10µF capacitor. Shutdown controlled (SHDN). shutdown when low. Shutdown mode selected with (NAP/SLP); high selects Nap. Timing Control Conversion start data read operations controlled three digital inputs: CONVST, logic applied CONVST will start conversion after been selected (i.e., low). Once initiated, cannot restarted until conversion complete. Converter status indicated BUSY output. BUSY during conversion. Figures through show several different modes operation. modes (Figures both tied low. falling edge CONVST starts conversion. data outputs always enabled data
LTC1409
APPLICATI
NAP/SLP
ATIO
SHDN
LTC1409 F14a
Figure 14a. NAP/SLP SHDN Timing
SHDN CONVST
LTC1409 F14b
Figure 14b. SHDN CONVST Wake-Up Timing
CONVST
LTC1409
Figure CONVST Setup Timing
tCONV CONVST BUSY DATA DATA DB11 DATA DB11 DATA DB11
LTC1409
Figure Mode CONVST Starts Conversion. Data Outputs Always Enabled (CONVST
latched with BUSY rising edge. Mode shows operation with narrow logic CONVST pulse. Mode shows narrow logic high CONVST pulse. mode (Figure tied low. falling edge CONVST signal again starts conversion. Data outputs three-state until read with signal. Mode used operation with shared databus. slow memory modes (Figures tied CONVST tied together. starts conversion reads output with signal. Conversions started external sample clock). slow memory mode processor applies logic CONVST) starting conversion. BUSY goes forcing processor into WAIT state. previous conversion result appears data outputs. When conversion complete, conversion results appear data outputs; BUSY goes high releasing processor, processor takes CONVST) back high reads conversion data. mode, processor takes CONVST) low, starting conversion reading previous conversion result. After conversion complete, processor read result initiate another conversion.
LTC1409
APPLICATI
ATIO
tCONV
CONVST BUSY DATA DATA DB11 DATA DB11 DATA DB11
LTC1409
Figure Mode CONVST Starts Conversion. Data Outputs Always Enabled
tCONV CONVST BUSY DATA DATA DB11
LTC1409
Figure Mode CONVST Starts Conversion. Data Read
tCONV CONVST BUSY DATA DATA DB11 DATA DB11 DATA DB11 DATA DB11
LTC1409
Figure Slow Memory Mode Timing
tCONV CONVST BUSY DATA DATA DB11 DATA DB11
LTC1409
Figure Mode Timing
LTC1409
PACKAGE DESCRIPTIO
0.0256 (0.65)
Dimensions inches (millimeters) unless otherwise noted. Package 28-Lead Plastic SSOP (0.209)
(LTC 05-08-1640)
0.397 0.407* (10.07 10.33)
0.205 0.212** (5.20 5.38)
0.068 0.078 (1.73 1.99) 0.301 0.311 (7.65 7.90)
0.005 0.009 (0.13 0.22)
0.022 0.037 (0.55 0.95)
0.010 0.015 *DIMENSIONS INCLUDE MOLD FLASH. MOLD FLASH (0.25 0.38) SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSIONS INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
0.002 0.008 (0.05 0.21)
SSOP 0694
Package 28-Lead Plastic Small Outline (Wide 0.300)
(LTC 05-08-1620)
0.697 0.712* (17.70 18.08) 0.291 0.299** (7.391 7.595) 0.010 0.029 (0.254 0.737) 0.093 0.104 (2.362 2.642) 0.037 0.045 (0.940 1.143) NOTE 0.394 0.419 (10.007 10.643)
0.009 0.013 (0.229 0.330)
0.050 0.004 0.012 (1.270) (0.102 0.305) 0.014 0.019 (0.356 0.482) NOTE: IDENT, NOTCH CAVITIES BOTTOM PACKAGES MANUFACTURING OPTIONS. PART SUPPLIED WITH WITHOUT OPTIONS *DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE NOTE 0.016 0.050 (0.406 1.270)
(WIDE) 0996
RELATED PRODUCTS
PART NUMBER LTC1273/75/76 LTC1274/77 LTC1278/79 LTC1282 LTC1410 LTC1415 LTC1419 LTC1605 DESCRIPTION Complete Sampling 12-Bit ADCs with 70dB SINAD Nyquist Power 12-Bit ADCs with Sleep Mode Shutdown High Speed Sampling 12-Bit ADCs with Shutdown Complete 12-Bit with 12mW Power Dissipation High Speed Sampling 12-Bit High Speed Sampling 12-Bit 14-Bit, 800ksps Sampling 16-Bit, 100ksps Sampling COMMENTS 300ksps, Single Dual Supplies 100ksps, 8-Bit 12-Bit Digital 500ksps/600ksps, Single Dual Supplies Fully Specified 3V/±3V Supply 1.25Msps, 71dB SINAD Nyquist, Power 1.25Msps, Single Supply, Lowest Power 81.5dB SINAD, 150mW from Supplies Single Supply, ±10V Input Range, Power
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417 (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 www.linear-tech.com
1409f LT/TP 0397 PRINTED
LINEAR TECHNOLOGY CORPORATION 1995

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