Verilog Model M45PExx Flash Pack This Project gives Verilog behav

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Verilog Model M45PExx Flash Pack This Project gives Verilog behav

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UM0091 USER MANUAL
Verilog Model M45PExx Flash Pack
This Project gives Verilog behavioral model M45PExx family Serial Flash Memory devices. give more complete example Verilog project, some other Verilog files also provided. project based blocks, M45PExx Memory M45PExx Driver blocks, gathered together under M45PExx_Testbench.v shown Figure 1.).
M45PExx_Macro.v M45PExx_Testbench.v: This initializes content memory array, specified M45PExx_Initial.dat. M45PExx_Memory.v: Verilog simulation model M45PExx Flash memory simulates behavior M45PExx memory. decodes protocol, executes memory Read Write operations, checks timing received signal M45PExx_Driver.v: This file defines instructions that transmitted M45PExx memory.
Figure Project Architecture
M45PExx_Macro.v M45PExx_Testbench.v
Initializes memory array M45PExx_Initial.dat
M45PExx_Driver.v M45PExx_Memory.v
Decodes protocol Executes memory read write operation Checks received signal's timing
AI09773
When simulating project, following files must compiled: M45PExx_Macro.v: Defines parameters DC/AC characteristics M45PExx memory. M45PExx_Testbench.v: Links M45PExx_Driver.v M45PExx_Memory.v. M45PExx_Memory.v: Describes behavioral model M45PExx Serial Flash memory device. M45PExx_Driver.v: Simulates master transmitting instructions M45PExx_Memory.v. Messages when Running Simulation When running simulation, M45PExx Verilog model send messages, prompt status model, commonly used most Verilog simulators: Note: note message normal information. Warning: warning message informs user that M45PExx Verilog model properly driven (through bus) that sequence compliant with M45PExx specification. Error: error message also informs user that M45PExx Verilog model properly driven (through bus) that sequence compliant with M45PExx specification.
July 2004
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Initialization File initialization file, M45PExx_Initial.dat, provided defining initial content memory array. When starting simulation, simulated memory array automatically loaded with contents that specified this file. M45PExx_Initial.dat file that provided with this Verilog model filled with FFh. This easily replaced user's initialization file changing system task parameter, $readmemh, named M45PExx_Initial.dat, M45PExx_Testbench.v file. format used this initialization file
Each byte data specified hexadecimal With exactly byte specified line each line terminated <carriage return>
Driver File Description
M45PExx_Driver.v provided only example file driving M45PExx Flash memory model. easy replace this file with user's M45PExx memory-access driver file. this file replaced, user must change M45PExx_Testbench.v, that links user's driver file M45PExx_memory.v. this model, thirteen tasks defined M45PExx_Driver.v file. Each task corresponds instructions that defined M45Pxx datasheet. M45PExx_Driver.v, these tasks invoked generate drives memory access. WRITE_ENABLE: generates Write Enable instruction sequence, bit.
WRITE_DISABLE: generates Write Disable instruction sequence, reset bit. READ_STATUS_REGISTER: generates Read Status Register instruction sequence, read contents Status Register. PAGE_ERASE: generates Page Erase instruction sequence, erase addressed page. Format: PAGE_ERASE (address)
address: destination address page erase.
SECTOR_ERASE: generates Sector Erase instruction sequence, erase addressed sector. Format: SECTOR_ERASE (address)
address: destination address sector erase. DEEP_POWER_DOWN: generates Deep Power-down instruction sequence.
RELEASE_FROM_DEEP_POWER_DOWN: generates Release from Deep Power-down instruction sequence. READ_DATA_BYTES: generates Read Data Bytes instruction sequence, read bytes data. Format: READ_DATA_BYTES address)
number data bytes read out. address: source address data bytes.
READ_DATA_BYTES_FAST: generates Fast Read Data Bytes instruction sequence, read bytes data higher frequency. Format: READ_DATA_BYTES_FAST address)
number data bytes read out. address: source address data bytes.
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PAGE_WRITE_SAME_DATA: generates Page Write instruction sequence, erase addressed page write bytes data, each with same value, beginning specified address. Format: PAGE_WRITE_SAME_DATA data, address)
number data bytes written. data: data byte written each address. address: destination address first data byte.
PAGE_WRITE_DIFF_DATA: generates Page Write instruction sequence, erase addressed page write bytes data, with different values, beginning specified address. Format: PAGE_WRITE_DIFF_DATA address)
number data bytes written. address: destination address start data bytes. data that written this task, passed variable named page_wr_buf. Before invoking PAGE_WRITE_DIFF_DATA task, data values should assigned page_wr_buf variable. (Care should exercised ensure that value that passed PAGE_WRITE_DIFF_DATA task same number bytes that have been assigned variable).
Assignment format: page_wr_buf {data1, data2. data (where 256) following example, eight different data bytes written addresses 000000h 000007h: page_wr_buf PAGE_WRITE_DIFF_DATA (12, 24'h000000); //Wait Page Write Cycle completed PAGE_PROGRAM_SAME_DATA: generates Page Program instruction sequence, program bytes data, each with same value, beginning specified address. Format: PAGE_PROGRAM_SAME_DATA data, address)
number data bytes programmed. data: data byte programmed each address. address: destination address first data byte.
PAGE_PROGRAM_DIFF_DATA: generates Page Program instruction sequence, program bytes data, with different values, beginning specified address. Format: PAGE_PROGRAM_DIFF_DATA address)
number data bytes programmed. address: destination address start data bytes.
data that programmed this task, passed variable named page_pg_buf. Before invoking PAGE_PROGRAM_DIFF_DATA task, data values should assigned page_pg_buf variable. (Care should exercised ensure that value that passed PAGE_PROGRAM_DIFF_DATA task same number bytes that have been assigned variable). Assignment format: page_pg_buf {data1, data2. data (where 256) following example, eight different data bytes programmed addresses 000000h 000007h: page_pg_buf PAGE_PROGRAM_DIFF_DATA (12, 24'h000000); //Wait Page Program Cycle completed
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REVISION HISTORY
Table Document Revision History
Date 06-Jul-2004 Version First Issue Revision Details
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Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics. other names property their respective owners. 2004 STMicroelectronics rights reserved STMicroelectronics GROUP COMPANIES Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www.st.com

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