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USER'S MANUAL M345/M350
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PREFACE
Super10 M345/M350
PREFACE introducing ST10 family member Super10, STMicroelectronics expanding offer strategic segments such Disk Drive, Automotive, Consumer, Telecom Industrial. broad range supplier, confirms company's position partner innovative fast moving world high-technology digital applications. addition existing attractive product portfolios, proposes Super10 system development Intellectual Property (IP) cells System-On-Chip (SOC) integration. Designed block, offering process portability highest density technologies, Super10 stands cost competitive solution developments. Built basis popular ST10 family, Super10 generation brings wider operating frequency range from static greater than with above future. Super10 provides faster execution time twice speed ST10, enhanced capabilities with instructions reduced power consumption mW/MHz while maintaining upward compatibility with ST10 code. Principally, result single cycle execution most instructions, addition optimized instructions zero cycle context switching interrupts, Super10 offers outstanding real time performances. With product development provides complete effective customer support. Based development environment (efficient tool chain, expert field application engineers third party development tools), system hardware design easier faster. High Level Languages well software tools, such compilers simulators, associated documentation (available ST's site www.st.com/Super10) complete ST's offer. addition, brings standard dedicated training with complete documentation. training sessions designed that hardware software engineers start working efficiently from beginning their product development knowing Super10 architecture accompanied tools detail. Considering these advantages, re-using code existing ST10 applications, Super10 migration path towards higher performance lower system development costs faster time-to-market, well being choice system development: Super10 definitely your winning choice.
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Super10 M345/M350
TABLE CONTENTS 2.2.1 2.2.2 3.3.1 3.3.2 3.3.3 3.3.4 3.4.1 3.4.2 3.5.1 4.2.1 4.2.2 INTRODUCTION ARCHITECTURE OVERVIEW DIFFERENCES BETWEEN M345/M350 M340 MEGACELLS NOTATION REGISTER DESCRIPTION LOOKING FOR: SYSTEM OVERVIEW CENTRAL PROCESSING UNIT (CPU) MEMORY ORGANIZATION Super10 Memory Space On-chip Memory Modules EXTERNAL CONTROLLER (EBC) PROGRAM MEMORY CONTROLLER (PMC) INTERRUPT CONTROLLER SYSTEM CONTROL MEMORY ORGANIZATION STORAGE ORGANIZATION WORDS, BYTES BITS MEMORY INTERNAL PROGRAM MEMORY DPRAM, DATA MEMORY AREA DPRAM Area Data Memories Special Function Register Areas General Purpose Registers (GPRs) AREA Source Destination Pointers External Controller (EBC) registers EXTERNAL MEMORY SPACE Reserved Start-up Memory Area CROSSING MEMORY BOUNDARIES SYSTEM STACK EXTERNAL CONTROLLER (EBC) INTRODUCTION TIMING PRINCIPLES Demultiplexed Mode Multiplexed Mode Page
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Super10 M345/M350
4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.4.1 4.4.2 4.4.3 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.6.7 4.6.8 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.2.1 5.2.1.1 5.2.1.2 5.2.2 5.3.1 5.3.2 5.3.2.1 5.3.2.2 5.3.3 READY READY CONTROLLED CYCLES Synchronous READY READY Asynchronous READY READY Combining READY READY function with predefined wait-states READY READY line active before programmed phase cycle with/without phase BURST MODES Page Mode Read Controlled Burst Mode Synchronous Burst Mode (clock controlled) INTERFACE SIGNALS EXTERNAL CONTROLLER REGISTER DESCRIPTION Configuration Register Overview EBCMOD0 TCONCSx TCONBURSTCSx FCONCSx ADDRSELx Idle State External Arbitration Multi-master Systems CENTRAL PROCESSING UNIT (CPU) ARITHMETIC LOGIC UNIT (ALU) Data Types Immediate Constants 16-bit Adder/Subtracter, Barrel Shifter 16-bit Logic Unit Manipulation Unit Multiply Divide Unit Processor Status Word Status MULIP) CODE ADDRESSING Segmented mode Code Segment Instruction Pointers Instruction Pointer Code Segment Pointer Non-Segmented Mode DATA ADDRESSING Short Addressing Modes Long Addressing Modes Data Page Addressing Mode DPP. Override Mechanism Indirect Addressing Modes
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5.4.1 5.4.2 5.4.3 5.4.4 5.5.1 5.5.2 5.5.3 5.5.3.1 5.5.3.2 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.2.1 6.2.2 6.2.3 7.1.1 7.1.2 7.1.3 7.1.4 SYSTEM STACK Stack Pointer Register Stack Overflow Pointer STKOV Stack Underflow Pointer STKUN Scope Stack Limit Control GENERAL PURPOSE REGISTERS (GPR) Memory Mapped Bank Global Register Bank Local Register Bank Context Switch Context Switch Changing selected Physical Register Bank Context Switching Global Register Bank Context Pointer (CP) INSTRUCTION FETCH PROGRAM FLOW CONTROL Short Loop Branch Target Addressing Modes Branch Detection Branch Prediction ATOMIC EXTended Instructions CPUCON1 Control Register UNIT MULTIPLY ACCUMULATE UNIT (MAC) 16-bit 16-bit signed/unsigned Multiplier Scaler Concatenation Unit One-bit Scaler 40-bit Adder/Subtracter Data Limiter Accumulator Shifter 40-bit Signed Accumulator Register Repeat Counter Unit Status Word Unit Control Word ADDRESSING GPRs Offset Registers IDX0 IDX1 Index Registers Offset Registers CoREG Addressing Mode INTERRUPT EXCEPTION PROCESSING INTERRUPT SYSTEM STRUCTURE Interrupt Arbitration Starting Interrupt Service Routine Saving Status During Interrupt Service Context Switching Interrupt
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7.1.4.1 7.1.4.2 7.1.4.3 7.1.4.4 7.1.5 7.1.6 7.1.7 7.1.7.1 7.1.7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.3.1 7.3.2 7.3.3 7.3.4 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.5.1 8.1.5.2 8.1.5.3 8.1.6 8.1.7 8.1.8 8.2.1 8.2.2 8.2.3 8.4.1
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Fast Context Switching Using Fast Register Bank Switching Switching Context Local Register Banks. Switching Context Between Global Register Banks Interrupt Vector Table Fast Interrupt Jump Table Cache External Interrupt Basic External Interrupt Standard External Interrupt PERIPHERAL EVENT CONTROLLER Control Registers Interrupt Control Register Source Destination Pointers Handler Interrupt Actions Summary Channels Assignment Arbitration Interrupt Register Table Ordered Trap Number HARDWARE SOFTWARE TRAPS Hardware Traps Class Traps Class Traps Software Traps SYSTEM CONTROL SYSTEM RESET START-UP Hardware Reset Reset Configuration Software Reset Watchdog Timer Reset RSTOUT RSTOUT2 RSTOUT Reset Output. RSTOUT2 Reset Output. Bidirectional Reset. Registers Description Reset Behaviour Summary Reset Start-up Sequence WATCHDOG TIMER (WDT) Overview Register Description Functional Description BOOTSTRAP LOADER ROUTINE (BSL) OVERVIEW POWER REDUCTION MODES Idle Mode
Super10 M345/M350
8.4.2 8.4.3 8.4.4 8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 9.3.1 9.3.2 9.6.1 9.6.2 10.1 10.1.1 10.1.2 10.1.3 10.1.4 11.1 11.2 11.3 11.4 Sleep Mode Power Down Mode Flexible Peripheral Management CLOCK GENERATION SYSTEM CONTROL CONFIGURATION REGISTER WRITE PROTECTION SECURITY SYSTEM Introduction Protected Registers Levels Protection Switching Protection Level Recommendations SUMMARY MEGACELL REGISTERS GENERAL PURPOSE REGISTERS (GPRS) ZEROS ONES CONSTANT REGISTERS SPECIAL FUNCTION REGISTERS (SFRS) SFR/ESFR Registers Ordered Name SFR/ESFR Registers Ordered Address REGISTERS ORDERED ADDRESS INTERRUPT REGISTERS ORDERED ADDRESS TRAP VECTORS Interrupt Vectors Ordered Trap Number Trap Vector Table RECOMMENDATIONS INSTRUCTION PIPELINE DEPENDENCIES AMONG INSTRUCTIONS DIFFERENT PIPELINE STAGES General Purpose Registers Indirect Addressing Modes Memory Bandwidth Conflicts CPU-SFRs (CSFRs) Pipeline REVISION HISTORY VERSION FEBRUARY 2003 VERSION 23RD JUNE 2003 VERSION 23RD DECEMBER 2003 VERSION 12TH 2004 ANNEX1: PROTECTED BITS WORD INDEX
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Super10
USER'S MANUAL
INTRODUCTION Super10 designed Intellectual Property (IP) Megacell super integration fitting perfectly customer dedicated designs. Built basis popular ST10 family, Super10 architecture brings attractive features combined with outstanding performances. These performances based enhanced optimized core, enhanced capabilities, speed with single cycle execution most instructions, ultra-fast context switching. addition, Super10 supports fast data processing keeping upward compatibility with existing ST10 codes. Optimization brings reduced power consumption range mW/MHz less despite high frequency operation), combined with small silicon size cells. includes powerful standard peripherals (asynchronous serial interface (ASC), synchronous serial interface (SSC), pulse width modulation module (PWM), Timer module (GPT)) standard ports taking advantage zero cycle context switching interrupts. This manual starts with overview system showing Super10 architecture. definition different units detailed following chapters. addition features functionalities each unit, interaction unit with overall system explained. Comments recommendations complete description make easy simple technical manual. Following this aim, some redundancies have been intentionally brought different sections when needed. Word Index main topics ends manual. With help this manual manuals listed below, user going find complete information needed design application based Super10 microcontroller. This Manual this manual reference M345/M350 Super10 Megacell. First time readers should read Chapter Introduction page Chapter System Overview page preliminary information. other chapters cover dedicated items like memories, CPU, interrupts, have internal redundancy references giving many feedbacks when complementary information needed. Section Looking For: page Chapter Word Index page index give necessary indexes fast access when looking some specific data. Additional Documentation M340 Megacell detailled Super10 M340 V1.2 User's Manual Peripherals Super10 covered Super10 Standard Peripheral User's Manual, instruction covered Super10 Instruction Reference Guide, electrical timing specifications product found data sheet your specific product.
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Super10 M345/M350
INTRODUCTION
Architecture Overview generation ST10/C16x families, Super10 system architecture, inherited from successful hardware software concept these families, offers outstanding performance wide range applications. modular structure described Chapter System Overview page illustrates Super10 optimized flexible architecture (refer Figure page 14). Central Processing Unit (CPU) exchanges data with several sources through different interfaces. includes Dual Port (DPRAM) memory specific data storage. Program Memory Controller (PMC) controls transfers with Internal Program Memory. interrupt controller manages interrupt exception requests sent peripherals other cells. System Control Unit (SCU) supports some product specific features like External Interrupt control Clock Generation central control tasks including Reset, Power saving, control, Watchdog Timer (WDT). these units detailed following dedicated chapters. Exchanges take place main buses, internal program memory bus, 16-bit internal data bus, 16-bit enhanced peripheral bus, 16-bit external data memory mentioned Chapter External Controller (EBC) page Super10 memory space based unified memory organization. code data accessed within same linear address space. external internal memories (RAM, DPRAM, Flash when integrated) mapped single Mbyte memory space (refer Chapter Memory Organization page description). on-chip emulation interface supports emulation modes contributes efficiency Super10 development tools. These dedicated information brought with tool documentation.
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INTRODUCTION
Super10 M345/M350
Differences between M345/M350 M340 Megacells local bank been added, with M345/M350 possible local banks (instead two) global bank General Purpose Register bank. Four Fast interrupts (instead implemented, direct jump interrupt routine. detection system stack overflow/underflow been improved leading efficient detection stack violations whatever stack operation external controller supports burst mode used with Flash memories. interrupt nodes (instead available. They driven external interrupt. Full performance PEC. CoSHL instruction with round. DPRAM interface. DPRAM longer inside Super10 Megacell, customer choose DPRAM size Kbytes). Peripheral interface that allows connect megacell some "ST10 legacy peripherals" which inside megacell like CAPCOM. User's identification register User's Manufactory identification register have been implemented. control/Status registers program these features have been included M345/M350 registers, keeping upward compatibility with M340. They listed following table. Table List M345/M350 Registers
Name ADCIC ADEIC BNKSEL2 BNKSEL3 CC0IC CC1IC CC2IC CC3IC CC4IC CC5IC CC6IC CC7IC CC23IC CC24IC CC25IC CC26IC CC27IC CC28IC CC29IC CC30IC CC31IC EI0IC Physical Address FF98h FF9Ah EC24h EC26h FF78h FF7Ah FF7Ch FF7Eh FF80h FF82h FF84h FF86h F16Eh F170h F172h F174h F176h F178h F184h F18Ch F194h F182h 8-bit Address Type SFR-b SFR-b SFR-b SFR-b SFR-b SFR-b SFR-b SFR-b SFR-b SFR-b ESFR-b ESFR-b ESFR-b ESFR-b ESFR-b ESFR-b ESFR-b ESFR-b ESFR-b ESFR-b Description Basic External Interrupt Basic External Interrupt Bank Selection Register Bank Selection Register Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Described Page 125-SPUM 125-SPUM
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INTRODUCTION
Name EI1IC EI2IC EI3IC EI4IC EI5IC FINT2CSP FINT2ADDR FINT3CSP FINT3ADDR T0IC T1IC T7IC T8IC TCONBURSTCS0 TCONBURSTCS1 TCONBURSTCS2 TCONBURSTCS3 TCONBURSTCS4 TCONBURSTCS5 TCONBURSTCS6 TCONBURSTCS7 USERIDCHIP USERID MANUF XP0IC XP1IC XP2IC
Physical Address F188h F18Ah F190h F192h F198h EC08h EC0Ah EC0Ch EC0Eh FF9Ch FF9Eh F17Ah F17Ch EE14h EE1Ch EE24h EE2Ch EE34h EE3Ch EE44h EE4Ch F076h F07Ah F186h F18Eh F196h
8-bit Address
Type ESFR-b ESFR-b ESFR-b ESFR-b ESFR-b SFR-b SFR-b ESFR-b ESFR-b ESFR ESFR ESFR-b ESFR-b ESFR-b
Description Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Fast Interrupt Register Fast Interrupt Address Register Fast Interrupt Register Fast Interrupt Address Register Basic External Interrupt Basic External Interrupt Basic External Interrupt Basic External Interrupt Burst Timing Configuration Register Burst Timing Configuration Register Burst Timing Configuration Register Burst Timing Configuration Register Burst Timing Configuration Register Burst Timing Configuration Register Burst Timing Configuration Register Burst Timing Configuration Register User chip Identification Register User Manufactory Identification Register Basic External Interrupt Basic External Interrupt Basic External Interrupt
Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXXXh3) XXXXh
Described Page
0000h 0000h 0000h
Notes: address ranges F1E0h F1FFh FFE0h FFFFh there 8-bit address. XXXXh: Value defined reset configuration. Hard-coded chip integrator. Reserved addresses always read FFFFh, except another reset value explicitly documented. However, enabling future enhancements without compatibility problem, these addresses should neither written used read value software. SPUM stands Standard Peripheral User's Manual.
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INTRODUCTION
Notation Register Description Register Name (FFB0h, D8h)
Super10 M345/M350
(E)SFR
Reset Value: -0FXh
Name
Bits 15,.12 11,.
Value 0000
Function These bits implemented, must kept "0", return value when read fixed These bits implemented, must kept "0", return value when read field with read/write access
function field function field Reserved combination field field read write access possible hardware write access read only access hardware write access only function diabled function enabled field read only access hardware write access only
Register Name long extensive) name register. (used assembler) short name register. FFB0h hexadecimal address register (16-bit address). short hexadecimal address (8-bit address). (E)SFR location register ESFR memory area Super10. could area also. Reset Value reset value register: means nibble bit) irrelevant. nibble cleared after reset. nibble after reset. hexadecimal value nibble after reset. bits nibble modified reset must controlled software. some bits affected reset must controlled software. bits reserved future enhancement. Reading these bits return unpredictable value. case byte word access always write these locations. These bits could masked, when using "BFLDx" instructions access register. bits reserved future enhancement. Reading these bits returns "0". case byte word access always write these locations. These bits could masked, when using "BFLDx" instructions access register. HRW: This (-field) read written software also modified hardware. This (-field) read written software. This (-field) "read-only" software modified hardware. "REG.BF2" notation used this manual refer bit-field register. Note: this kind note brings information compatibility between Super10 ST10 families
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Looking For: following list gives section chapter references specific information.
looking information about: Addressing space memory size Addressing modes Program memory Data memory Buses
INTRODUCTION
Turn these sections chapters: Section Chapter Sections 10.1 Sections Sections Sections 3.4.2 Chapter
System registers General purpose registers Sections 10.1.1 10.1.4 System stack Control Status flags Peripherals Interrupts Context switch Instruction format Pipeline phases Sections Chapter Instruction Reference Guide Sections 5.1.6- 5.1.7 6.1.9 6.1.10 Instruction Reference Guide Sections 3.3.3 Standard Peripheral User's Manual Sections 5.1.6 5.5.3 Chapter Sections 7.1.4 Chapter Sections 5.1.1 5.3.2.2 6.2.3 Instruction Reference Guide Chapter
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SYSTEM OVERVIEW
SYSTEM OVERVIEW
Super10 M345/M350
Super10 designed offer process portability maximum super-integration flexibility. constitutive elements have been optimized bring best compromise between operating speed, power consumption silicon size. Based modular concept already mentioned Super10 microcontroller includes units described following sections. block diagram Figure illustrates interaction link between units supported fast buses. memory capabilities addressing space structure detailed Chapter page Figure System Block Diagram
JTAG
DPRAM
Data Memory*
Program Memory*
chip Emulation Super10 Interrupt Controller
Program Memory Controller
Peripheral
Peripheral
Peripheral
Watchdog Timer
Clock Generation* System Control Unit
Port
Port
Port
implementation this cell product specific, refer product data sheet Internal Dual Port Memory Internal Program Memory External Memory Peribus Internal Data Memory Internal Peripheral Central Processing Unit (CPU) Super10 combines many powerful enhancements keeping compatibility ST10 generation. core system, improvements lead faster more efficient accesses different memories peripheral units. particular combination Instruction Fetch Unit (IFU) with Exception-Injection handler, Instruction Pipeline (IPIP) Write-back Buffer (WB) allows continuous instruction flow (refer Section page leads execution most instructions average cycle. dedicated 16-bit arithmetic unit addresses generation address unit with dedicated address-offset pointers implemented Address Data Unit (ADU). Arithmetic Logic Unit (ALU) supports 8-16-bit arithmetic unit, 16-bit barrel shifter, multiply-divide unit, 8-16-bit logic unit powerful manipulation unit.
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SYSTEM OVERVIEW
Multiply Accumulate Unit (MAC) includes 16-bit multiplier with 32-bit result generation, 40-bit accumulator, 40-bit barrel shifter repeat control unit applications. This unit handles signed-unsigned 32-bit integer format signed-unsigned 32-bit fractional format. banks registers brings flexible fast context switching capabilities. detailed Chapter page Memory Organization external internal memories (RAM, DPRAM, Flash when integrated) mapped single memory space. order provide full integrated system, some "on-chip" memories integrated different Super10 devices. Refer product data sheet information on-chip memories Chapter page details. 2.2.1 Super10 Memory Space Super10 memory space Mbyte linear address space. physically separated memory areas, including internal ROM-Flash-DPRAM (when integrated), internal RAM, internal Special Function Register Areas (SFRs ESFRs), external memory mapped into common address space. Mbytes address space arranged segments Kbytes each. Each segment sub-divided blocks Kbytes. 191th segment (from address BF'0000h BF'FFFFh) reserved area used ST's on-chip specific program. This segment cannot allocated user's program. Data have stored internal Data RAM, DPRAM external memory. Instruction codes have stored internal program memory external memory. 2.2.2 On-chip Memory Modules Mbytes on-chip Program memory integrated Super10 devices. This Internal Program Memory used both code (instructions) data (constants, tables, storage. Super10 differentiates between several internal memory types internal peripheral areas. Kbyte Dual Port (DPRAM) implemented store General Purpose Register banks, some variables data unit optionally System Stack. Kbytes SRAM named Data Memory integrated support variable data storage System Stack. Special Function Registers (SFR- ESFR) basically located on-chip areas bytes. External Controller (EBC) external memory accesses performed External Controller (EBC). programmed four modes: 16-bit.24-bit Addresses, 16-bit Data, Demultiplexed 16-bit.24-bit Addresses, 16-bit Data, Multiplexed 16-bit.24-bit Addresses, 8-bit Data, Demultiplexed 16-bit.24-bit Addresses, 8-bit Data, Multiplexed allow different kinds external memories, Super10 timings features configurable many ways thanks complete control registers. example some address ranges accessed with different characteristics, external chip select (CS) signals available, ready function supports slow memories, HOLD/HLDA protocol available arbitration. Three different burst modes implemented take advantage speed most available Flash memories. detailed description given Chapter page Program Memory Controller (PMC) provides with instructions stored internal program memory. instructions requested located Internal Program Memory external memory space. this case, forwards request EBC. Mbytes on-chip program memory space cannot addressed external memory, even less than Mbytes implemented on-chip, this memory space must considered reserved external memory addressing signals generated.
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SYSTEM OVERVIEW
Super10 M345/M350
Interrupt Controller Super10 improves already powerful feature ST10 family: real-time processing performance. This been achieved with efficient interrupt controller additional dedicated register banks enabling zero cycle context switching interrupt. interrupt system includes different interrupt nodes programmable within interrupt priority levels trap functions handle system exception occurring run-time. transfers simply performed with Peripheral Event Controller (PEC) providing eight different channels fastest data byte data word transfer between locations. operate single byte-word mode continuous transfer, with without pointer management with without interrupt generation. System Control This unit controls central tasks some product specific features. following typical functions implemented this unit: Reset Control unit internal system reset sequence initializes device into default state. default reset value each register documented register description associated table. After reset peripherals their predefined default state (refer Section page 133). Power Saving Control idle mode, power down mode sleep mode Super10 fully supported power saving control block. additional power saving, peripherals disabled enabled individually (refer Section page 144). Control identification most important silicon parameters three identification registers implemented. They provide information chip manufacturer, chip type properties. These registers used automatic test selection (refer Section page 156). External Interrupt Control unit manages asynchronous fast external interrupt inputs (refer Section 7.1.7 page 115). Central System Control This block controls Super10 central system behavior thanks some system configuration registers. provide high protection operation, some system control registers locked (write protected) after initialization routine (EINIT). However, some these registers accessed during operation under special security procedure (refer Section page description this proctection). Watchdog timer (WDT) Watchdog timer represents fail-safe mechanisms which used prevent controller from malfunctioning. However, watchdog timer only prevent long term malfunctioning (refer Section page 139).
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Super10 M345/M350
MEMORY ORGANIZATION
MEMORY ORGANIZATION
memory space Super10 organized unified memory. This means that code, data, registers accessed within same linear address space. physically separated memory areas, including internal ROM, Flash, SRAM, DPRAM (where integrated), internal RAM, internal Special Function Register Areas (SFRs ESFRs), external memory mapped into common address space. Super10 provides total addressable memory space Mbytes. This address space arranged segments Kbytes each, each segment again subdivided into four data pages Kbytes each (see Figure entire memory space accessed byte word wide. Figure Memory Areas Address Space
Segment Data Page 1023
Mbytes
Program Memory
Kbytes
Start-up Memory
Segment reserved** DPRAM Area 00'FFFFh 00'F000h 00'E000h Kbytes
Mbytes
External Memory
Segment
Data Page
Internal-IO Area
On-chip Data Memory Kbytes 00'C000h
Mbytes
External
Segment
Data Page
00'8000h
Mbyte
External Memory
Segment Segment
Data Page
External Memory
00'4000h
Kbytes
Segment Data Page Data Page Mbytes
Data Page
Kbytes page
System Segment Kbytes
Depend product implementation Customer's choice Start-up memory used.
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MEMORY ORGANIZATION
Super10 M345/M350
Data stored part internal memory areas. Code stored part internal memory areas, except blocks, internal area, DPRAM Internal Data RAM, which have used control data, instructions. Kbytes segment number (BF'0000h BF'FFFFh) reserved area used ST's on-chip specific program. This segment cannot allocated user's program. Note: Accesses implemented internal memory areas will produce unpredictable results. Refer product data sheet precise description implemented on-chip memories. Storage Organization Words, Bytes Bits Memory Bytes stored even byte addresses. Words stored ascending memory locations with byte even byte address being followed high byte next byte address. Double word instructions stored ascending memory location subsequent words. Single bits always stored specified position word address. memory registers store data instructions little endian byte order (the least significant bytes lower addresses). byte ordering illustrated Figure position least significant byte even byte address, position most significant byte next byte address. addressing supported part Special Function Registers, part DPRAM General Purpose Registers. Figure Storage Words, Byte Bits Memory
xx'xxxAh
Bits Bits Byte Byte Word (High Byte) Word (Low Byte) Double Word (High Byte) Double Word (Third Byte)
xx'xxx9h xx'xxx8h xx'xxx7h xx'xxx6h xx'xxx5h xx'xxx4h xx'xxx3h xx'xxx2h xx'xxx1h xx'xxx0h xx'xxxFh
Double Word (Second Byte) Double Word (Low Byte)
Note:
Byte units forming single word double word must always stored within same physical (internal, external, ROM, RAM) organizational (page, segment) memory area. cross segment boundaries.
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MEMORY ORGANIZATION
Internal Program Memory Super10 reserves on-chip address area Mbytes Internal Program Memory. internal memory ROM, Flash SRAM. Internal Program Memory area starts from beginning segment number address C0'0000h. Depending device specification, Internal Program Memory part whole Mbyte space then expands segment number address FFFFh (when Mbytes implemented). Internal Program Memory used both code (instructions) data (constants, tables, etc.) storage. Code fetches always made even word addresses. highest possible code storage location Internal Program Memory either xx'xxFEh single word instructions, xx'xxFCh double word instructions. word byte data read accesses indirect long 16-bit addressing modes. There short addressing mode Internal Program Memory operands. word data access made even byte address. double word access made modulo address (even word address). highest possible word data storage location Internal Program Memory xx'xxFEh, highest double word location xx'xxFCh. Note: Internal Program Memory provided single storage, therefore addressable. locations above depend available Internal Program Memory. DPRAM, Data Memory Area Super10 differentiates between several internal memory types internal peripheral areas (see Figure page segment (00'C000h.00'FFFFh) holds Special Function Register Areas (SFR ESFR), internal DPRAM Areas provide fast accesses using dedicated Data Page Pointers. Data Memory located page part page Note: Code accesses possible from DPRAM, Data Memory I/O-SFR areas. 3.3.1 DPRAM Area DPRAM serves for: General Purpose Register Banks (GPRs) Variable other data storage, specially used operands Kbyte memory area (00`F200h. 00'FDFFh) reserved DPRAM. upper bytes DPRAM (00'FD00h.00'FDFFh) bank GPRs provided single storage, thus they addressable (see shaded blocks Figure word byte data DPRAM accessed indirect long 16-bit addressing modes selected register points data page word data access made even byte address. highest possible word data storage location DPRAM 00'FDFEh. Note: strongly recommended locate system stack Data Memory integrated) external instead DPRAM area. This choice leads simpler management system stack because banks located DPRAM stack located Data Memory. 3.3.2 Data Memories Data Memory serves for: Variable other data storage System Stack (recommended choice) Kbyte memory area (00`8000h.00'DFFFh) reserved Data Memory. word byte data Data Memory accessed indirect long 16-bit addressing modes selected register points data page data page word data access made even byte address. highest possible word data storage location Data Memory 00'DFFEh. Note: Data Memory addressable.
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MEMORY ORGANIZATION
Super10 M345/M350
3.3.3 Special Function Register Areas functions CPU, interface, ports, on-chip peripherals Super10 controlled number so-called Special Function Registers (SFRs). These SFRs arranged within areas bytes each. first register block, area, located bytes above DPRAM (00'FE00h.00'FFFFh), second register block, Extended (ESFR) area, located bytes below DPRAM (00'F000h.00'F1FFh). Figure Areas
00'FFFFh DPRAM Area Internal Area Data Page 00'F000h 00'E000h Area 00'FE00h DPRAM 00'FD00h 00'FFFFh
3Kbytes 00'C000h 00'FA00h
Data Memory Kbytes Data Page
reserved 00'F600h DPRAM
00'8000h 00'F200h ESFR Area 00'F000h Data Page
00'EE00h
INT/PEC External Memory 00'4000h reserved NEXUS
00'EC00h
00'EA00h
Data Page
00'E800h
Internal
System Segment Kbytes
reserved "ST10 legacy peripherals" connected peribus interface
00'E400h
Reserved space bytes bit-addressable area 00'E000h
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addressed indirect long 16-bit addressing modes. Using 8-bit offset together with implicit base address allows address word SFRs their respective bytes. However, this does work respective high bytes! Note: High byte accesses SFR`s using short addressing modes possible (see Section page details). Writing byte causes non-addressed complementary byte cleared! upper half ESFR areas bit-addressable, respective control/ status bits directly modified checked using manipulation instructions. Before accessing registers ESFR area using 8-bit addresses direct addressing, EXTend Register (EXTR) instruction required switch short addressing mechanism from standard area EXTended area. This required 16-bit indirect addresses. order minimize switching banks, ESFR area mostly hold registers which mainly required initialization mode selection. Registers that need accessed frequently allocated standard area, wherever possible. Note: C-Compilers equipped monitor accesses ESFR area will automatically insert EXTR instructions, switch bank address, issue error case missing excessive EXTR instructions.
3.3.4 General Purpose Registers (GPRs) Super10 uses banks working registers named General Purpose Registers (GPR). bank active time. GPRs belong global register bank, located internal DPRAM (memory-mapped), three local banks (not memory mapped). GPRs accessed short 2-bit 4-bit addressing mode, short 8-bit mode direct 24-bit mode global bank only. GPRs also utilized indirect address pointer. They used word wise byte wise format (refer Section page details). Note: Global GPRs banks located DPRAM addressable using manipulation instructions. Area Some parts Super10 memory area reserved control data registers. These internal external memory areas have following special properties: Accesses buffered cached write back buffers caches Super10 used store read write accesses. Special handling destructive reads pipeline Super10 allows speculative reads. Memory locations area read until speculations solved. Destructive read accesses delayed. Write before read execution Because pipeline length Super10, read instruction able read memory location before preceding write instruction executed write access. Data forwarding ensures correct instruction flow execution. case read access, read access will delayed until writes pending pipeline executed. case write access, peripherals change their internal states. Write accesses must really executed before next read access initiated. Note: avoid pipeline effect, above mentioned features guarantee proper accesses data, additional peripherals must implemented dedicated I/Os area benefit this feature. manipulation instructions (BSET, BCLR.) read-modify-write approach. read access these instructions will delayed until write accesses finished.
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MEMORY ORGANIZATION
following memory areas marked I/O: Mbyte external located 20'0000h 3F'FFFFh area located from 00'FE00h 00'FFFFh ESFR area located from 00'F000h 00'F1FFh Kbyte internal located from 00'E000h 00'EFFFh Note:
Super10 M345/M350
external areas support real byte accesses. internal areas support real byte transfers. Writing byte causes non-addressed complementary byte cleared!
3.4.1 Source Destination Pointers support fast data transfer between memory locations interrupt request, Peripheral Event Controller (PEC) uses source destination pointer each channels. Note: contrast ST10 family pointer registers longer located internal DPRAM. pointers located Kbyte internal area.
source destination pointer address from 00'EC40h 00'EC8Eh area. Each channel uses pair pointers stored subsequent word registers with source pointer (SRCPx) lower destination pointer (DSTPx) higher word address channel number) segment register (PECSEGx). registers part itself addressed internal peripheral bus. Note: channel used, corresponding pointer locations available cannot used word byte storage. Writing byte pointers causes non-addressed complementary byte cleared. more details about source destination pointers data transfer Section page 116. 3.4.2 External Controller (EBC) registers From address 00'EE00h 00'EEFFh, bytes reserved configuration registers. Refer Chapter page have description each register. Note: access internal areas, implemented not, does activate signals thus externally accessible.
External Memory Space Super10 address space Mbytes. Only parts this address space occupied internal memory areas. This external memory accessed external interface. External word byte data only accessed indirect long 16-bit addressing modes using four registers. There short addressing mode external operands. word data access made even byte address double word accesses modulo byte addresses even word address (refer Section page 62). Note: external memory provided single storage therefore addressable. 3.5.1 Reserved Start-up Memory Area Kbyte memory area segment (BF'0000h.BF'FFFFh) reserved factory start-up code. This on-chip memory accessed using part EBC`s external memory space. Even this memory part external memory space, accesses visible port pins EBC. During normal code execution this segment accessible Super10. case read access will deliver predefined 0000h value write access will executed. memory segment accessed only during start-up sequence. Note: segment (BF'0000h.BF'FFFFh) usable system application. External memories peripherals cannot located this segment.
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Crossing Memory Boundaries address space Super10 implicitly divided into equally sized blocks different granularity into logical memory areas described Figure Instruction codes stored Kbyte segment four Kbyte page areas internal Program Memory external memory space. Crossing boundaries between these blocks (code data) areas requires special attention ensure that controller executes desired operations. Memory Areas partitions address space that represent different kinds memory provided all). These memory areas internal areas, internal area, internal Program Memory available), external I/Os external memory. Accessing subsequent data locations that belong different memory areas lead erroneous results. There restriction memory boundaries word aligned. However, when executing code, different memory areas (Internal Program Memory areas external memory) must switched explicitly branch instructions. Sequential boundary crossing supported lead erroneous results. Segments contiguous blocks Kbytes each. They referenced code segment pointer code fetches explicit segment number data accesses overriding standard scheme. During code fetching segments changed automatically must switched explicitly using JMPS, CALLS RETS instructions. larger sequential programs, prevent prefetcher from trying leave current segment, highest used code location segment must contain unconditional branch instruction respective following segment. Data Pages contiguous blocks Kbytes each. They referenced data page pointers DPP3.0 explicit data page number data accesses overriding standard scheme. Each register select possible 1024 data pages. register that used current access selected upper bits 16-bit data address. Subsequent 16-bit data addresses that cross Kbytes data page boundaries will different data page pointers, while physical locations need subsequent within memory. System Stack Super10 provides Kbyte standard system stack fitting with Kbyte segment granularity memory organization. This function detailed following sections. Nevertheless wider system stack implemented. standard system stack located internally on-chip memories external memory. 16-bit Stack Pointer (SP) register addresses stack within Kbyte segment. Stack Pointer SEGment register (SPSEG) selects segment where stack located. management size stack controlled mean STKOV STKUN registers (refer Section page 68).
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EXTERNAL CONTROLLER (EBC)
Super10 M345/M350
Introduction Although Super10 provides powerful on-chip peripherals on-chip program data memories, these internal units only cover small fraction Super10 Mbyte addressing space. external interface allows access additional external volatile non-volatile memories peripherals. external supports various interfaces, tailored perfectly into given application system. integrated External Controller (EBC) configured with registers. control registers bring enough flexibility timings accuracy addressing external memories peripherals adapt Super10 most applications. list control registers given Table page register functions explained following sections. supports external chip select channels. Each these chip select signals programmable registers. FCONCSx registers specify external cycles terms address (multiplexed demultiplexed), data width (16-bit 8-bit wide), chip select enable READY signal control. timing access controlled TCONCSx/TCONBURSTCSx timing configuration registers, which specify length different access phases. parameters used access within specific address area defined corresponding ADDRSELx address select register. seven register sets (x=1,.7) allow define seven independent "address windows" with their specific parameters, while external accesses outside these windows, controlled EBCMOD0, FCONCS0 TCONCS0/TCONBURSTCS0 registers. external timing related clock. signals generated relation rising edge this clock. dedicated Chip Select Channel with fixed address range parameter allocated start-up memory 191th segment. When addressing this area signals accessible user. Note: external protocol compatible that ST10. However, external timing improved terms accuracy number possible wait-states. ST10 registers SYSCON BUSCONx longer used. configuration external controller done usually during application initialization. Therefore, considering configuration, only some initialization routines have adapted some ST10 code Super10 application.
Timing Principles timing external accesses adapted demultiplexed multiplexed buses. access cycle split phases. Some phases more related access types (demultiplexed multiplexed). following timing diagrams associated phase description show different cases.
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4.2.1 Demultiplexed Mode Figure Demultiplexed Read
Phase name clock
EXTERNAL CONTROLLER (EBC)
Address
Data Read Clocks Bit-field PHAx PHBx PHCx PHDx
Data 1-32 PHEx RDPHFx Possible clock cycles Bit-field TCONCSx register
Programmable clock cycles phases phases always exist with minimum clock cycle
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Figure Demultiplexed Write
Phase name clock
Super10 M345/M350
Address
Data Write Clocks Bit-field PHAx PHBx PHCx PHDx
Data 1-32 PHEx WRPHFx
Programmable clock cycles phases phases always exist with minimum clock cycle
Possible clock cycles Bit-field TCONCSx register
Phase phase adjusted from clock periods according TSCONCSx.PHAx bit-field value. Chip-Select (CS) change, data drivers forced tri-state during this phase. Phase cycles inserted only when current access using same than previous one. example, continuous external accesses, when access using channel followed access using one, Phase cycles inserted according programmed value TCONCSx.PHAx bit-field channel (and TCONCSy.PHAy one). This feature adapts timing devices with long turn-off delay data drivers like EPROMs FLASHs (see Figure Phase cycles inserted while addresses next cycle active already. there some idle cycles between accesses, these taken into account Phase shortened accordingly. example there three tri-state cycles programmed idle cycles occur then Phase lasts only clock period. Phase phase clock periods long, defined TCONCSx.PHBx bit-field value. used device and/or register selection before read/write command activation. defines minimal possible active length clock period). During this phase, address valid external device. Phase phase similar phases except that level. clock periods programmed with TCONCSx.PHCx bit-field. Phase cycles used delay read/write command signals. Phase phase clock period. write mode, participates set-up time data before write command becomes active. phase selected with TCONCSx.PHDx bit-field.
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Phase phase programmed from clock periods according TCONCSx.PHEx bit-field value. determines read/write signal duration number wait-states being inserted. minimum duration clock period. read mode data fetched from external device, write mode data onto Super10. Read data registered with terminating clock period this phase. READY function also lengthen this phase (see Section page 30). READY controlled access cycles have unlimited cycle time. When used burst mode burst sub-phases controlled with TCONBURSTCSx register. Refer Section Burst Modes page description. Phase phase access. take clock periods programmed with TCONCSx.PHFx bit-field. Addresses data write held while write command inactive. number hold-states being inserted phase independently programmed TCONCSx.RDPHFx read accesses TCONCSx.WRPHFx write accesses. write mode, offers adjust hold time data bus. Note: phases always exist they have minimum clock cycle duration.
Figure Phase Cycle Insertion
Phase name
TCONCS1.PHA1 TCONCS5.PHA5 TCONCS3.PHA3
Phase Phase
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4.2.2 Multiplexed Mode Figure Multiplexed Read
Phase name clock
Super10 M345/M350
Address Data Address A23.A16 Clocks Bit-field PHAx
Address Address PHBx PHCx PHDx
Data
1-32 PHEx
RDPHFx
Programmable clock cycles phases phases always exist with minimum clock cycle
Possible clock cycles Bit-field TCONCSx register
Figure Multiplexed Write
Phase name clock
Address Data
Address
Data
Address A23.A16 Clocks Bit-field PHAx PHBx
Address
PHCx
PHDx
1-32 PHEx
WRPHFx
Programmable clock cycles phases phases always exist with minimum clock cycle
Possible clock cycles Bit-field TCONCSx register
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Phase phase adjusted from clock periods according TSCONCSx.PHAx bit-field value. Chip-Select (CS) change, during this phase, data drivers forced tri-state. Phase phase clock periods long, defined TCONCSx.PHBx bit-field value. used device and/ register selection before read/write command activation. defines minimal possible active length clock period). During this phase, address valid external device. Phase phase similar phases except that level. take clock periods programmed with TCONCSx.PHCx bit-field. Phase cycles used delay read/write command signal increase address hold time after falling edge. Phase phase take clocks. used tri-state address multiplexed when read cycle performed. write cycles used have data valid before command applied. brings, way, flexibility data set-up time. phase selected with TCONCSx.PHDx bit-field. Phase phase programmed from clock periods according TCONCSx.PHEx bit-field value. determines read/write signal duration number wait-states being inserted. minimum duration clock period. read mode data fetched from external device, write mode data onto Super10. Read data registered with terminating clock period this phase. READY function also lengthen this phase (see Section page 30). READY controlled access cycles have unlimited cycle time. When used burst modes burst sub-phases controlled with TCONBURSTCSx register. Refer Section Burst Modes page description restriction using burst modes multiplexed mode. Phase phase access. take clock periods programmed with TCONCSx.PHFx bit-field. Written data held while write command inactive. number hold-states being inserted phase independently programmed TCONCSx.RDPHFx read accesses TCONCSx.WRPHFx write accesses. write mode, offers adjust hold time bidirectional data bus. Note: phases always exist they have minimum clock cycle duration.
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READY READY Controlled Cycles Super10 provides control external cycles thanks READY READY input signal (programmable polarity synchronous asynchronous mode). This feature useful when response (access) time peripheral constant, when programmable wait-states enough. this case during Phase Super10 first counts programmable number clock cycles (1.32) then monitors READY READY line determine current cycle. external device drives READY READY active indicate that data have been latched (Super10 write cycle) available (Super10 read cycle). READY READY function globally (for channels) enabled when EBCMOD0.RDYDIS clear. selectively enabled disabled each chip select channel with FCONCSx.RDYENx bit. READY READY Polarity signal active level programmable with EBCMOD0.RDYPOL bit. kinds external devices (using READY READY line with active high active READY) connected bus. Knowing addressed device, software will have manage correct polarity selection before addressing bus. Particular care must taken design applications using READY READY function, especially when READY READY function enabled specific address window, every cycle within this address window must terminated with active READY READY signal from external addressed device. Otherwise controller hangs until next reset. 4.3.1 Synchronous READY READY Figure Demultiplexed READ With Synchronous READY
Phase name Phase cycles
clock
(READY)
Idle
Valid
READY Directly used Data this example: PHA, PHC, PHD, cycle cycle, cycles Valid Inserted periods clock waiting valid READY
READY READY function synchronous mode when FCONCSx.RDYMODx set. This mode provides fastest cycles, requires set-up hold times with respect clock (see Figure 10). synchronous mode, first monitoring READY READY line done last programmed wait-state phase.
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4.3.2 Asynchronous READY READY READY READY function asynchronous mode when FCONCSx.RDYMODx cleared. This mode less restrictive than synchronous mode require some additional wait-states internal synchronization explained below. READY READY signal (especially asynchronous mode) deactivated external addressed device response trailing (rising) edge respective (RD) read (WR) write command (see Figure 11). asynchronous mode first sampling READY READY line done beginning last programmed wait-state phase. READY READY line inactive sampled again next rising edge clock. line sampled active, registered signal used next rising edge clock idle cycle terminates cycle (see Figure 11). phase been programmed with wait-state, first sampling READY READY line done beginning phase (see Figure 12). Figure Demultiplexed READ With Asynchronous READY
Phase name Phase cycles
clock
(READY)
Idle
ADDR
Valid
Active Sample READY READY must deactivated
Data this example: PHA, PHC, PHD, cycle cycle, cycles
Registered Valid Inserted periods clock before reading Data
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Figure Asynchronous READY with Programmed Wait-state Phase
Phase name Phase cycles
clock
Idle
(READY)
Valid
READY Active Sample Registered Valid Inserted periods clock before reading Data READY line must inactive
Data this example: PHA, PHC, PHD, cycle cycle, cycles
Programming phase with wait-state could lead erroneous cycle READY READY still active first sampling point. 4.3.3 Combining READY READY function with predefined wait-states Combining READY READY function with predefined wait-states advantageous cases: Typically external wait-state READY READY control logic takes while generate READY READY signal when cycle starts. inserting some phase cycles Super10 monitoring starts when READY READY line been properly activated. When using READY READY function with so-called "normally-READY" peripherals, early sampling READY READY line lead erroneous cycles. These peripherals pull their READY READY output active while they idle. When accessed, they drive READY READY line inactive until cycle completed, then they drive active again. however, peripheral drives READY READY line inactive little late, after first sampling, Super10 going read active READY READY line wrongly terminates current cycle. inserting some predefined wait-states phase, first sampling READY READY line done when peripheral properly drives READY READYY line (see Figure page 31).
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4.3.4 READY READY line active before programmed phase cases must considered describe external cycle: READY READY line becomes active before last programmed wait-state phase. This shown Figure data latched next rising edge clock idle cycle terminates cycle. READY READY line becomes active just last programmed wait-state phase, last cycle completed before READY READY line sampled active. This shown Figure data latched next rising edge clock idle cycle terminates cycle. This configuration similar described Figure Figure Asynchronous READY Active Before Last Programmed Wait-state Phase
Phase name Phase cycles
clock
Idle
this example: PHA, PHC, PHD, cycle cycle, cycles
Valid
Active Sample READY Registered Data Valid
READY sampling starts rising edge last programmed Phase (3rd). this example last cycle phase terminated idle cycle inserted cycle.
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Super10 M345/M350
Figure Asynchronous READY Active Last Programmed Wait-state Phase
Phase name Phase cycles
clock
Idle
this example: PHA, PHC, PHD, cycle cycle, cycles
Valid
Active Sample READY Registered Data Valid
this example programmed phase cycles elapsed, takes cycle between active sample registered idle cycle complete cycle.
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4.3.5 cycle with/without phase phase used conjunction with synchronous/asynchronous READY READY function. phase cycles have been programmed, idle phase clock automatically inserted between current access next shown Figures Using phase leads insert some wait-states terminate cycle shown Figure this case idle cycle does exist. Programming phase least with wait-state) both read write operation gives user additional flexibility control cycle. Figure Asynchrounous READY With Phase
Phase name Phase cycles
clock
(READY)
READY Registered Data Valid
this example: PHA, PHC, cycle cycle, cycles, cycles
Burst Modes controller Super10 M345/M350 Megacell allows code fetching burst accesses. Three different modes available: Page mode Read Controlled Burst mode Synchronous Burst mode (clock controlled). burst capability enhances Super10 performances when executing code from memory connected external interface. Burst accesses usually comprise initial access phase identical standard access (with Tacc latency) followed burst access phases (with Tburst latency). reading first word (with Tacc) defines start address following words (with Tburst) read from consecutive linear addresses. burst access time (Tburst) significantly smaller than initial (standard) access time (Tacc). M345/M350 burst sequence words long, means that standard access again performed after each word fetch. Reading Flash memory word pages leads total access time Tacc 3xTburst). maximun words which read sequentially page size feature given Flash memory datasheet. example using ST's M59DRT032E Flash memory, page size bytes words) Tacc 100ns Tburst 35ns.
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Super10 M345/M350
total page access time (Tacc 3xTburst) 205ns instead 400ns standard access. Note: page mode only runs demultiplexed mode, read controlled burst mode synchronous burst mode possible both multiplexed demultiplexed modes. READY function 8-bit modes supported burst modes. burst access aborted CPU, this case less than words read. 4.4.1 Page Mode page mode Super10 M345/M350 increments bits address (ADD2:1) automatically address consecutive locations. target Flash memory outputs corresponding data word described Figure Figure Page Mode Read Access
clock
Phase
1-32
2-16
2-16
2-16
ADD(23:3)
Addr1
Addr2
ADD(2:1)
Data Word
this example: PHA, PHC, cycles
Flash memory outputs data word (ADD2:1) address change leading basically asynchronous reading process. access starts with phase (ALE assertion). starting address burst driven beginning phase. strobe asserted beginning phase. phase must compatible with Flash initial access latency. Thanks range programmable clock cycles phase, Super10 most Flash memories. first data word sampled phase part address (ADD2:1) incremented. Then burst phase starts, corresponds burst access latency. page mode burst phase programmable with PHEbLx bit-field TCONBURSTCSx register. There burst phases word reading sequence Super10 EBC. During burst phases asserted. burst reading aborted step sequence simply de-asserting signals. This mode supports most standard Flash memories.
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4.4.2 Read Controlled Burst Mode read controlled mode used devices like ST's M59BW102 Flash memory. This kind synchronous access with signal giving start address burst read signal being used clock output next sequential word. signal toggle during burst phase shown Figure Figure Read Controlled Burst Mode Access
clock
Phase
1-32
ADD(23:3)
Addr1
Addr2
ADD(2:1)
1-15 1-16
Data Word
this example: PHA, PHC, cycles
this mode lower bits address (ADD2:1) could stay unchanged words given page since Flash samples address lines only when address latch enable asserted. Anyway Super10 outputs address lines each word like page mode. access starts with phase (ALE assertion). starting address burst driven beginning phase. strobe asserted beginning phase. phase must compatible with Flash initial access latency. adjusted thanks programmable clock cycles phase. first data word sampled phase part address (ADD2:1) incremented. Then burst phase starts, corresponds burst access latency. read controlled mode line driven high back duration burst sub-phases. sub-phases programmable using PHEbhx PHEbLx bit-fields TCONBURSTCSx register Flash memory specifications. total duration phase adding Ebl. There burst phases word reading sequence Super10 EBC. During burst phases asserted. burst reading aborted step sequence simply de-asserting signals.
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4.4.3 Synchronous Burst Mode (clock controlled) support Flash memories operating true synchronous mode, Super10 M345/M350 Megacell generates specifics signals, Latch Burst Address (LBA) Burst AdvAnce (BAA) signals. Latch Burst Address (LBA) asserted clock period indicate that burst address valid address bus. Burst Advance (BAA) used target Flash increment burst address counter. synchronous burst mode timings detailled Figure Figure Synchronous Burst Read Access
clock
Phase ADD(23:3)
1-32
Addr1
Addr2
ADD(2:1)
1-15
Data Word
this example: PHA, PHC, cycles, must
synchronous mode data word output Flash clock edge. access starts with phase (ALE, assertion). starting address burst driven beginning phase. properly latch burst starting address (Flash memory requirement), assertion must last only clock period, therefore phase must programmed clock cycle. Note that once burst starting address been latched Flash address don't care address changes until next burst starting. Anyway Super10 outputs address lines each word like page mode. strobe asserted beginning phase. phase must compatible with Flash initial access latency, adjusted thanks programmable clock cycles phase. first data word sampled Super10 phase. asserted clock cycle before phase. Then starts phase, burst counter address incremented rising edge BAA. phase corresponds burst access latency. synchronous burst mode line driven high back duration burst sub-phases. sub-phases programmable using PHEbhx/PHEbLx bit-fields TCONBURSTCSx register. There burst phases word reading sequence Super10 EBC. During burst phases asserted. burst reading aborted step sequence simply de-asserting signals.
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Interface Signals Table summarizes different signals used EBC. Table Interface Signals
Signal Name A[23:0] These 24-bit address Demultiplexed Mode: A[23:0] Multiplexed mode: AD[15:0] A[23:16] only Signal Function
These data-bit less significant address-bit Demultiplexed Mode: Data only Multiplexed Mode: Address Data multiplexed
Address Latch Enable signal external devices connected External Memory Read Strobe activated every external data instruction) read access.
WR/WRL
External Memory Write Strobe mode: activated every external data write access. mode: activated only byte data write accesses 16-bit every data write access 8-bit bus.
BHE/WRH
External Memory Byte High Enable/Write High Strobe mode: activated every external data access upper byte 16-bit data bus. mode: activated only high byte data write accesses 16-bit bus.
CS[7:0] READY READY
External Chip Select signals. Ready Input Programmable polarity. When Ready function enabled, inactive level this during external memory access will force insertion memory wait-states during phase, active level will terminate cycle.
HOLD HLDA
External Master Hold Request Input (see Section 4.6.8 External Arbitration Multi-master Systems page Hold Acknowledge Output Input (see Section 4.6.8 page Master mode: Output Slave mode: Input
BREQ
Request Output (see Section 4.6.8 page Latch Burst Address Output (see Table 4.4.3 page Burst AdvAnce Output (see Table 4.4.3 page
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External Controller Register Description control registers covered write protection security system. They write protected after execution EINIT instruction unless security level changed (see Section page details). 4.6.1 Configuration Register Overview EBCMOD0 register used program global functions. chip select registers control functionality linked Eight signals implemented. There four 16-bit registers dedicated each They support timing selection, configuration, burst mode configuration window address allocation. Except RSTCFG.CSSEL bit-field "000b", default chip select active long other chip select internal address space addressed. address whole external memory space, consequently there ADDRSEL0 register (see Figure page Section 8.1.2 page 133). Table Configuration Register Overview
Name EBCMOD0 TCONCS0 TCONBURSTCS0 FCONCS0 TCONCS1-7 TCONBURSTCS1-7 FCONCS1-7
Description Global configuration pins Timing control Timing control burst mode Function control Timing control CS1.CS7 Timing control CS1.CS7 burst mode Function control CS1.CS7 Address window selection CS1.CS7
Address 00EExxh
Reset Value 0XXXh1 7A7Fh2 0000h1 00X1h1 0000h 0000h 0000h 0000h
ADDRSEL1-7
Notes:
registers initialized during reset phase. They redefined during start-up routine according some hardware setups during reset configuration. Reset value depends start-up code used product. Refer product specification exact value. avoid unpredictable behaviour EBC, FCONCSx registers MUST CONFIGURED AFTER corresponding ADDRSELx TCONCSx registers have been programmed properly.
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registers mapped internal space Data page segment Figure Chip Select Channel Dedicated Registers
00'EEFEh
Channel Control
ADDRSEL7 TCONBURSTCS7 FCONCS7 TCONCS7 ADDRSEL6 TCONBURSTCS6 FCONCS6 TCONCS6 ADDRSEL5 TCONBURSTCS5 FCONCS5 TCONCS5 ADDRSEL4 TCONBURSTCS4 FCONCS4 TCONCS4 ADDRSEL3 TCONBURSTCS3 FCONCS3 TCONCS3 ADDRSEL2 TCONBURSTCS2 FCONCS2 TCONCS2 ADDRSEL1 TCONBURSTCS1 FCONCS1 TCONCS1 TCONBURSTCS0 FCONCS0 TCONCS0
Channel Control
Channel Control
Channel Control
Channel Control
Channel Control
Channel Control
Channel Control
00'EE4Eh 00'EE4Ch 00'EE4Ah 00'EE48h 00'EE46h 00'EE44h 00'EE42h 00'EE40h 00'EE3Eh 00'EE3Ch 00'EE3Ah 00'EE38h 00'EE36h 00'EE34h 00'EE32h 00'EE30h 00'EE2Eh 00'EE2Ch 00'EE2Ah 00'EE28h 00'EE26h 00'EE24h 00'EE22h 00'EE20h 00'EE1Eh 00'EE1Ch 00'EE1Ah 00'EE18h 00'EE16h 00'EE14h 00'EE12h 00'EE10h
Control
EBCMOD0
00'EE00h
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4.6.2 EBCMOD0 Mode Register EBCMOD0 (EE00h)
Name RDYPOL Bits RDYDIS ALEDIS BYTDIS WRCFG EBCDIS SLAVE ARBEN CSPEN 7,.4 0000 0101 1000 other APEN 3,.0 0000 0001 0101 1000 other Value READY Polarity READY signal active READY signal active high READY Disable READY enabled READY disabled Disable enabled disabled Disable enabled disabled
Super10 M345/M350
Description CSPEN
Reset value: 0XXXh
APEN
RDYPOL RDYDIS ALEDIS BYTDIS WRCFG EBCDIS SLAVE ARBEN
Configuration pins WR/WRL, BHE/WRH pins ouput signals respectively pins ouput signals respectively pins Disable dedicated pins allocated function according selected configuration SLAVE mode enable arbiter acts master mode arbiter acts slave mode Arbitration Pins enable HOLD, HLDA BREQ pins tristate pins HOLD, HLDA BREQ Pins Enable None Five CS[4:0] Eight CS[7:0] reserved Address Enable None A[16] Five A[20:16] Eight A[23:16] reserved
Notes: change content valid before next external access cycle. EBCMOD0.ARBEN must activate HOLD, HLDA BREQ external arbitration pins. When ARBEN cleared, HOLD, HLDA BREQ pins stay their inactive high state.
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4.6.3 TCONCSx
EXTERNAL CONTROLLER (EBC)
Timing Configuration Chip Select channel 7.0) TCONCSx (EE10h,.EE48h)
Name Bits Value Reserved PHEx WRPHFx RDPHFx
(TCONCS0 Reset Value: XXXXh)1 Reset Value: 0000h
PHDx Description PHCx PHBx PHAx
This reserved future enhancement. Reading This returns "0". case byte word access always write this location. WRPHFx 14,13 RDPHFx 12,11 PHEx 10,.6 00000 11111 PHDx PHCx PHBx PHAx Write Phase Read Phase Phase Phase 1clk Phase Phase Phase
Note:
TCONCS0 reset value depends start-up code used product. Refer product specification exact value.
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4.6.4 TCONBURSTCSx Timing Configuration Chip Select channel 7.0) Burst Mode TCONBURSTCSx (EE14h,.EE4Ch)
Name Bits 15,8 Value Reserved Description
Super10 M345/M350
Reset Value: 0000h
PHEbL
PHEbh
These bits reserved future enhancement. Reading these bits returns "0". case byte word access always write these locations. PHEbhx 0000 1111 PHEbLx 0000 1111 Phase high) Phase low)
Note:
reset value TCONBURSTCSx registers 0000h, mandatory program TCONBURSTCSx register before enabling burst mode FCONCSx.BURST bit-field.
programming TCONBURSTCSx registers depends type burst mode used. Table Table TCONBURSTCSx register Phase Selection
Burst Mode Page mode Read controlled mode Synchronous mode PHEbhx Clock Cycles PHEbLx Clock Cycles
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4.6.5 FCONCSx
EXTERNAL CONTROLLER (EBC)
Function Configuration Chip Select Channel 7.0) FCONCSx (EE12h,.EE4Ah)
Name Bits 15,.8 Value BURST
(FCONCS0 Reset Value: 00X1h) Reset Value: 0000h
BTYPx ENCSx MODx
Description Reserved These bits reserved future enhancement. Reading these bits returns "0". case byte word access always write these locations. Burst Mode Selection Code Fetching
BURSTx
burst synchronous burst page mode read controlled burst mode reserved External Type Selection
BTYPx
8-bit Demultiplexed mode 8-bit Multiplexed mode 16-bit Demultiplexed mode 16-bit Multiplexed mode Reserved This reserved future enhancement. Reading this returns "0". case byte word access always write this location. Ready Mode
RDYMODx
asynchronous READY/READY synchronous READY/READY Ready enable
RDYENx
access time controlled PHEx bit-field TCONCSx register access time controlled PHEx bit-field READY/READY signal Enable Chip Select
ENCSx
disabled enabled
Note:
Disabling chip select only effects chip select output signal corresponding address window deactivated too. disabled address window ignored address window arbitration.
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EXTERNAL CONTROLLER (EBC)
4.6.6 ADDRSELx Address range size Select Chip Select window 7.1) ADDRSELx (EE1Eh,.EE4Eh)
Name RGSAD RGSZ Bits 3,.0 Value Description Address Range Start Address Selection Address Range Size Selection
Super10 M345/M350
Reset Value: 0000h
RGSZ
RGSAD
Note:
FCONCS0/TCONCS0 registers control external accesses outside seven address windows ADDRSEL1.ADDRSEL7, there ADDRSEL0 register.
Definition Address Areas seven register sets (x=1, allow define seven separate address areas Super10 address space. Within each these address areas, external accesses performed four different modes independently mode other areas mode specified global chip select Each ADDRSELx register cuts address window, which external accesses controlled parameters registers FCONCSx TCONCSx/TCONBURSTCSx. given window size only most significant address bits range start address (ADDRSELx.RGSAD) used (marked Table number relevant bits depends range size (ADDRSELx.RGSZ) window. These bits valid addresses inside window. lower bits ADDRSELx.RGSAD bit-field (marked disregarded. additional chip select channel used accessing start-up memory. located fixed address 191th segment. size this address area fixed Kbytes. address area from BF'0000h FF'FFFFh used start-up memory internal program memory. Therefore, this address area cannot used external resources connected external bus. Table Address Range Size ADDRSELx
Range Size RGSZ Selected address range 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 11xx Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Mbyte Mbytes Mbytes Mbytes reserved Relevant bits RGSAD Range start address A[23:0] selected with R-bits RGSAD RRRR RRRR RRRR RRRR RRRR RRR0 RRRR RRRR RR00 RRRR RRRR R000 RRRR RRRR 0000 RRRR RRR0 RRRR RR00 RRRR R000 RRRR 0000 RRR0 0000 RR00 0000 R000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
RRRR RRRR RRRR RRRR RRRR RRRX RRRR RRRR RRXX RRRR RRRR RXXX RRRR RRRR XXXX RRRR RRRX XXXX RRRR RRXX XXXX RRRR RXXX XXXX RRRR XXXX XXXX RRRX XXXX XXXX RRXX XXXX XXXX RXXX XXXX XXXX
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Note:
EXTERNAL CONTROLLER (EBC)
range start address only boundaries specified selected range size.
Address Window Arbitration each external access compares current address with address select registers (programmable ADDRSELx hardwired address select registers start-up memory). This comparison done three levels. Priority (highest): Registers ADDRSELx evaluated before ADDRSELy respectively. match with these registers directs access respective external area using corresponding control registers FCONCSx/TCONCSx ignoring registers ADDRSELy. Priority match with registers ADDRSELy directs access respective external area using corresponding control registers FCONCSy/TCONCSy. Priority (lowest): there match with address select register (neither hardwired ones programmable ADDRSEL) access external uses general control registers FCONCS0/TCONCS0. Figure Address Window Arbitration
Highest priority
Lowest priority
Note:
Only indicated overlaps allowed. other overlaps lead erroneous cycles: overlaps same level priority forbiden, e.g. must overlap must overlap CS7; order overlap fixed, e.g. overlap only, overlap only, overlap only overlap only; hardwired address ranges start-up memory monitor memory defined non-overlapping.
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EXTERNAL CONTROLLER (EBC)
Super10 M345/M350
4.6.7 Idle State When external interface enabled, external access currently executed, idle. long internally mapped resources like RAM, peripherals registers, etc. used only, external interface does change (see Table external control signals WRL/WRH enabled) remain inactive (high) until next external access. Table Status External Interface during Idle State
Pins AD15.AD0 A15.A0 A23.A16 CS7.CS0 Tristate (floating) Undefined address used interface) Undefined segment address selected pins) Inactive (high) Level corresponding last external access Inactive (low) Inactive (high) Inactive (high) Inactive (high) Inactive (high) Inactive (high) Internal accesses only
4.6.8 External Arbitration Multi-master Systems some high performance applications, system need share external devices (like memories, peripherals,.) between several MCUs. Super10 supports such multi-master structure thanks arbitration capability. This arbitration allows external master request Super10 HOLD input. Super10 floats lines acknowledges this request HLDA output. outputs have internal pull-up control lines become available requester. During this time Super10 keep executing, long does need access external bus. actions that just require internal resources, like instruction data memory on-chip peripherals, executed parallel while external used other master. When Super10 needs regain external occupied another master, sends request BREQ output. order prevent some accesses from other master, PSW.HLDEN must cleared during execution program sequences using unsharable external resources. this case Super10 will answer HOLD requests from other external masters. serve requests from other masters PSW.HLDEN must set. PSW.HLDEN cleared during hold state running (HOLD line held other master), running hold state will only last when HOLD line becomes inactive (high), then Super10 allowed access external bus. next external requests will answered when Super10 release again. Connecting Super10s this would require additional logic combine respective output signals HLDA BREQ. This avoided setting controllers Master mode second Slave mode (HLDA switched input). This allows directly connect slave controller another master controller without glue logic (see Figure page 49). Slave Mode selected setting EBCMOD0.SLAVE bit, default mode after reset Master Mode. HOLD, HLDA BREQ external arbitration pins enabled setting EBCMOD0.ARBEN bit. When EBCMOD0.ARBEN cleared, HOLD, HLDA BREQ pins stay their inactive high state. During reset arbitration pins tristate, except BREQ which pulled inactive high.
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Super10 M345/M350
EXTERNAL CONTROLLER (EBC)
HOLD, HLDA BREQ pins keep their arbitration function even after arbitration mechanism been switched clearing PSW.HLDEN long EBCMOD0.ARBEN set. master default owner external bus. driving even idle. slave returns master idle, even master idle, too. master hold state though having pending request, drives BREQ active minimum clock after activating HLDA. master slave requesting external same time several accesses, they toggle ownership after each access cycle. Both master slave lock arbitration execute several access cycles with PSW.HLDEN being cleared. possible have more than masters external bus. this case Super10s have into master mode separate schedule logic used, handle ownership. Connecting Masters, Master Mode Slave Mode When multiple Super10s Super10 another master have share external resources some glue logic required. This glue logic needed masters does automatically remove hold request after having used shared resources. logic also defines currently active master enables other masters regain control case need. When Super10s have connected this external glue logic left out. this case controllers must operate Master Mode (default after reset) while other must operate Slave Mode (selected with SLAVE '1'). Note: Master mode Slave mode settings cannot changed dynamically. After first time PSW.HLDEN getting valid settings frozen cannot changed until reset. write EBCMOD0.SLAVE does change more value after first time PSW.HLDEN active.
Slave Mode Super10 inverts direction HLDA uses input, while master's HLDA remains output. This approach does require additional glue logic arbitration (see Figure 21). Figure Sharing External Resources using Master Slave Mode
HOLD Super10 Master Mode HLDA
HOLD HLDA Super10 Slave Mode
BREQ
BREQ
When arbitration enabled (EBCMOD0.ARBEN '1') three corresponding pins controlled EBC. direction HLDA directly controlled according EBCMOD0.SLAVE bit.
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EXTERNAL CONTROLLER (EBC)
Super10 M345/M350
Entering Hold State Access Super10 external requested driving HOLD input low. After synchronizing this signal Super10 will complete current external cycle active), release external grant access driving HLDA output low. During hold state Super10 treats external interface follows: Address data bus(es) float tristate. Command lines pulled high internal pull-up devices (RD, WR/WRL, BHE/WRH). Address latch control line pulled internal pull-down device. outputs pulled high internal pull-up devices. Should Super10 require access external during hold mode, activates request output BREQ notify arbitration circuitry. BREQ activated only during hold mode. will inactive during normal operation. Figure External Arbitration, Releasing
HOLD
HLDA
BREQ
Other signals
Note:
Super10 will complete currently running cycle before granting access indicated broken lines. This delay hold acknowledge compared Figure Figure shows first possibility BREQ active.
Exiting Hold State external master returns access rights Super10 driving HOLD input high. After synchronizing this signal Super10 will drive HLDA output high, actively drive control signals resume executing external cycles required. Depending arbitration logic, external returned Super10 under circumstances: external master does more require access shared resources gives access rights, Super10 needs access shared resources demands this activating BREQ output. arbitration logic then deactivate HLDA other masters free external Super10, depending priority different masters. Note: Hold State terminated clearing PSW.HLDEN bit.
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Super10 M345/M350
Figure External Arbitration (Regaining Bus)
EXTERNAL CONTROLLER (EBC)
HOLD
HLDA
BREQ
Other signals
Note:
falling BREQ edge shows last chance BREQ trigger indicated regain-sequence. Even BREQ activated earlier regain-sequence initiated HOLD going high. BREQ HOLD connected external arbitration circuitry. Please note that HOLD also deactivated without Super10 requesting bus.
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CENTRAL PROCESSING UNIT (CPU)
CENTRAL PROCESSING UNIT (CPU)
Super10 M345/M350
Super10 represents third generation well known ST10 core family. combines many powerful enhancements while keeping compatibility ST10 family. architecture results high performance, fast efficient access different kinds memories, proficient peripheral units integration. Most instructions executed cycle leading double speed program execution compared previous ST10. integrated Multiply Accumulate Unit (MAC) drastically increases performance intensive tasks. Super10 structure includes seven main units listed below: Arithmetic Logic Unit (ALU) 8-bit 16-bit Arithmetic Unit 16-bit Barrel Shifter Multiplication Division Unit 8-bit 16-bit Logic Unit manipulation Unit Multiply Accumulate Unit (MAC) 16-bit multiplier with 32-bit result generation* 40-bit Accumulator with 40-bit Barrel Shifter Repeat Control Unit Address Data Unit (ADU) 16-bit arithmetic unit address generation address unit with dedicated address offset pointers General Purpose Registers (GPR) Files Register File with independent register banks High performance Instruction Fetch Unit (IFU) High bandwidth fetch interface Instruction FIFO High performance Branch, Call Loop Processing with instruction flow prediction Instruction Pipeline (IPIP) stage prefetch pipeline bypassable stage execution pipeline Write Back Buffer (WB) Injection Exception Handler Handling Interrupt requests Handling hardware failures same hardware-multiplier used unit. processing efficiency mainly capability Arithmetic Logic Unit (ALU). Super10 includes ALUs, standard data processing Parallel Data Processing (MAC) unit Digital Signal Processing (DSP) applications. Super10 ALUs include 16-bit arithmetic logic operations well powerful manipulation. Once pipeline been filled, most instructions completed cycle. ALUs described Section page Section page Address Data Unit provides ALUs with data generates addresses. register files status, control data storage associated CPU. order maintain continuous processing, Instruction Fetch unit with Instruction Pipeline manages program flow while Injection-Exception handler controls different interrupt requests.
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Figure Architecture
Prefetch Unit Branch Unit FIFO CPUCON1 CPUID Return Stack Instruction Fetch Unit IDX0 IDX1 DPP0 DPP1 DPP2 DPP3 Injection/Exception Handler VECSEG
CENTRAL PROCESSING UNIT (CPU)
Peripheral 2-Stage Prefetch Pipeline
5-Stage Pipeline
Internal Program Memory
SPSEG STKOV STKUN Context Pointer
Write-Buffer
Internal Data Memory
Address Data Unit
Local Bank
Local Bank
Multiply Unit (MAE)
Division Unit Multiply Unit Zeros
Bit-Mask-Gen. Barrel-Shifter
INTERNAL DPRAM GLOBAL BANKS
Local Bank
Bank
Ones GPRs
Bank
Global Bank
Bank
Multiply Accumulate Unit
Arithmetic Logic Unit
Kbytes
Arithmetic Logic Unit (ALU) standard arithmetic, shift logical operations performed 16-bit ALU. addition standard Arithmetic Logic Unit, Super10 includes manipulation, multiply divide units. internal execution blocks have been optimized perform operations either 8-bit 16-bit numbers. Once pipeline been filled, most instructions completed cycle. status flags automatically updated register (see Section 5.1.6 page after each operation. These flags allow branching upon specific conditions. Support both signed unsigned arithmetic provided user selectable branch test. status flags preserved automatically upon entry into interrupt trap routine. 5.1.1 Data Types Super10 supports operations booleans/bits, characters, integers signed unsigned fractional numbers. Super10 data formats support ANSI data types. Additionally ANSI data types, some C-Compilers support types which allow efficient manipulation instructions embedded control applications (refer Instruction Reference Guide complete information). Table Data Formats
Data Format BYTE WORD Size (bytes) 255U -128 +127 65535U -32768 32767 53/186 Range
CENTRAL PROCESSING UNIT (CPU)
Super10 M345/M350
5.1.2 Immediate Constants addition powerful addressing modes Super10 instruction also supports wordwide bytewide immediate constants. optimum utilization available code storage, these constants represented instruction formats either bits. short constants always zero-extended, while long constants truncated, when necessary match data format some particular operations. 5.1.3 16-bit Adder/Subtracter, Barrel Shifter 16-bit Logic Unit standard arithmetic logical operations performed 16-bit ALU. case byte operations, signals from sixth seventh result used control condition flags. Multiple precision arithmetic supported "Carry-in" signal from previously calculated portions desired operation. 16-bit barrel shifter provides multiple shifts, rotations arithmetic shifts supported single cycle. 5.1.4 Manipulation Unit Super10 offers large number instructions processing supported special manipulation unit. manipulation instructions provide efficient control testing peripherals. Unlike other microcontrollers, Super10 features instructions that provide direct access operands bit-addressable space without requiring move them into temporary locations. same logical instructions that available words bytes also used bits. user compare modify control peripheral instruction. Multiple shift instructions have been included avoid long instruction streams single shift operations. These instructions require single cycle. addition, bit-field instructions able modify multiple bits operand single instruction, using ATOMIC/EXTended sequence. upper bytes area, ESFR area DPRAM bit-addressable, directly manipulated using instructions. other SFRs must accessed byte/word wise. instructions that manipulate single bits groups internally read-modify-write sequence that accesses whole word, which contains specified bit(s). This method several consequences: Bits only modified within internal bit-addressable areas mentioned above, External locations cannot used with instructions. Note: GPRs bit-addressable independently allocation global register bank context pointer Even GPRs located bit-addressable locations provide this feature.
With hardware modifiable bits (marked "HRW" register descriptions), expected result instructions accessing these registers, especially manipulation instructions, achieved. hardware events occuring during execution such instructions taken into account without side effect. case simultaneous modifications such bits hardware event user's code access, software ALWAYS priority. Example: During read-modify-write sequence like BSET T2IC.IE, interrupt request (hardware event) within sequence correctly target register. case BCLR T2IC.IR, interrupt request (hardware event) within sequence removed software priority.
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Super10 M345/M350
CENTRAL PROCESSING UNIT (CPU)
5.1.5 Multiply Divide Unit Super10 multiply divide unit separated parts. fast 16x16-bit multiplier, which executes multiplication cycle. other division sub-unit which performs division algorithm cycles maximum. According data division types, division length varies between cycles. divide instruction requires cycles executed. performance reasons rest division algorithm running background during following cycles maximum) while further instructions executed parallel. another instruction tries unit again while division still running, execution this instruction halted until division finished (either execute MUL/DIV instruction access MDH/MDL). Interrupt tasks also started executed immediately without delay. previous division will finished background. instruction interrupt task uses multiply divide unit while previous division process finished, instruction flow will halted well. avoid these stalls, multiply division unit should used during first cycles interrupt tasks. This requires one-cycle instructions executed between interrupt entry first instruction which uses multiply divide unit again (worst case). Multiply/Divide High Register 16-bit register (not bit-addressable) contains high word 32-bit multiply/divide register which used when performs multiplication division using implicit addressing (DIV, DIVL, DIVLU, DIVU, MUL, MULU). After implicitly addressed multiplication this register represents high order bits 32-bit result. long divisions, register loaded with high order bits 32-bit dividend before division started. After division register represents 16-bit remainder. Multiply Divide High Word (FE0Ch, 06h)
Name Bits 15,.0 Value High part high order bits 32-bit multiply divide register Description
Reset value: 0000h
Note:
Whenever this register updated software, Multiply/Divide Register (MDRIU) flag Multiply/Divide Control register (MDC) '1'.
Multiply/Divide Register 16-bit register (not bit-addressable) contains word 32-bit multiply/divide register which used when performs multiplication division using implicit addressing (DIV, DIVL, DIVLU, DIVU, MUL, MULU). After multiplication, this register represents order bits 32-bit result. long divisions, register loaded with order bits 32-bit dividend before division started. After division, register represents 16-bit quotient.
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CENTRAL PROCESSING UNIT (CPU)
Multiply Divide Word (FE0Eh, 07h)
Name Bits 15,.0 Value part Description
Super10 M345/M350
Reset value: 0000h
order bits 32-bit multiply divide register
Note:
Whenever this register updated software, Multiply/Divide Register (MDRIU) flag Multiply/Divide Control register (MDC) '1'. MDRIU flag cleared whenever register read software.
Divide Control Register This bit-addressable 16-bit register implicitly used when performs division multiplication ALU. Multiply Divide Control (FF0Eh, 87h)
Name MDRIU Bits 15,.5 3,.0 Value
MDRIU
Reset value: 0000h
Description These bits implemented, must kept "0", return value when read Multiply/Divide Register Cleared, when register read software. when register written software, when multiply divide instruction executed. These bits implemented, must kept "0", return value when read
MDRIU flag only portion register that used multiplication division within Super10. This indicates usage register. remaining portions register never used dedicated multiplication division hardware. This flag reflects running idle state multiply/divide unit. MDH/MDL registers already use, they have saved later restored. 5.1.6 Processor Status Word This bit-addressable register reflects current status microcontroller. groups bits represent current status, current interrupt status. separate bits (USR0 USR1) within register provided general purpose flags when using USRxC0xxx repeatable instructions they loop flag. this case they must used general purpose flags.
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Super10 M345/M350
Processor Status Word (FF10h, 88h)
Value HLDEN BANK USR1 USR0 MULIP Priority Level Lowest Priority Highest Priority Global Interrupt/PEC Enable Interrupt/PEC requests disabled Interrupt/PEC requests enabled HLDEN ILVL Name ILVL Bits 15,.12 BANK
CENTRAL PROCESSING UNIT (CPU)
USR1 USR0 MULIP
Reset value: 0000h
Description
HOLD Enable Multi-master arbitration disabled. HOLD signal inactive. Multi-master arbitration enabled. HOLD signal active. Register file bank selection Global register bank Local register bank Local register bank Local register bank User Flag This flag when equals zero USR1C0xxx repeat instruction used. User Flag This flag when equals zero USR0C0xxx repeat instruction used. Multiplication/Division progress Always read table Flag Source operand neither 8000h Source operand 8000h Zero Flag result zero result zero Overflow Flag Overflow produced Overflow produced Carry Flag carry/borrow produced Carry/borrow produced Negative Result result negative result negative
Notes: USRxC0xxx repeat instructions used, USR0 USR1 bits serve general purpose flag. "8000h" word data type "80h" byte data type.
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CENTRAL PROCESSING UNIT (CPU)
Super10 M345/M350
5.1.7 Status MULIP) condition flags within indicate status resulting from last performed operation. They majority instructions according specific rules depending operation data movement. explicit write operation register supersedes condition flag values which implicitly generated CPU. explicit read access register returns value register after execution immediately preceding instruction. Note: Some care must taken when using status flags after execution instruction explicitly writing register, condition flags longer reflect current status. After reset status bits cleared. N-Flag: majority operations, N-flag '1', most significant result contains '1', otherwise cleared. case integer operations, N-flag interpreted sign result (negative: N='1', positive: N='0'). Negative numbers always represented complement corresponding positive number. range signed numbers extends from '-8000h' '+7FFFh' word data type, from '-80h' '+7Fh' byte data type. Boolean operations with only operand, N-flag represents previous state specified bit. Boolean operations with operands N-flag represents logical XORing specified bits. C-Flag: After addition C-flag indicates that "Carry" from most significant specified word byte data type been generated. After subtraction comparison C-flag indicates "Borrow" which represents logical negation "Carry" addition. This means that C-flag '1', carry from most significant specified word byte data type been generated during subtraction. Subtraction performed complement addition. C-flag cleared when this complement addition caused "Carry". C-flag always cleared logical, multiply divide operations, because these operations cause "Carry" flag set. shift rotate operations C-flag represents value shifted last. shift count zero specified, C-flag will cleared. C-flag also cleared Prioritize operation (PRIOR instruction), because never shifted during normalization operand. Boolean operations with only operand C-flag always cleared. Boolean operations with operands C-flag represents logical ANDing specified bits. V-Flag: addition, subtraction complement operations V-flag result exceeds range 16-bit signed numbers word operations ('-8000h' '+7FFFh'), 8-bit signed numbers byte operations ('-80h' '+7Fh'). Otherwise, V-flag cleared. Note that result integer addition, integer subtraction, complement valid V-flag indicates arithmetic overflow. multiplication division V-flag result represented word data type, otherwise cleared. Note that division zero will always cause overflow. Unlike division result, result multiplication valid regardless V-flag value. Since logical operations cannot produce invalid result, V-flag cleared these operations. V-flag used 'Sticky Bit' rotate right shift right operations also. When using C-flag only, rounding error caused shift right operation estimated half result. better resolution rounding error checking V-flag C-flag (see table below). Boolean operations with only operand V-flag always cleared. Boolean operations with operands V-flag represents logical ORing specified bits.
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Super10 M345/M350
Shift Right Rounding Error Evaluation
C-Flag V-Flag
CENTRAL PROCESSING UNIT (CPU)
Rounding Error Quantity rounding error Rounding error Rounding error Rounding error
Z-Flag: Z-flag normally '1', result operation equals zero, otherwise cleared. case addition subtraction with "Carry" leading result zero combined with Z-flag already result previous operation, Z-flag set. This mechanism supports multiple precision calculations. Boolean operations with only operand Z-flag represents logical negation previous state specified bit. Boolean operations with operands, Z-flag represents logical NORing specified bits. prioritize operation (PRIOR instruction) Z-flag indicates whether second operand zero not. E-Flag: table flag. E-flag altered instructions which perform data movement operations. E-flag cleared those instructions which cannot reasonably used table search operations. other cases E-flag value depends value source operand signify whether search table reached not. value source operand instruction equals lowest negative number which depends data format corresponding instruction ('8000h' word data type '80h' byte data type), E-flag '1', otherwise cleared. MULIP-Flag: MULIP-flag always sticks '0'. Note: MULIP flag part ST10 task environment. compatibility reasons still implemented even used anymore.
BANK: PSW.BANK bit-field selects active General Purpose Register (GPRs) bank. BANK bit-field updated hardware upon entry into interrupt service routine, explicitly modified software. implicitly updated RETI instruction (refer Section General Purpose Registers (GPR) page Section Interrupt System Structure page detailed information). Note: BANK bit-field changed explicitly instruction able write PSW. This mean switch between three local and/or global GPRs banks. This operation recommended because pipeline dependencies. explicit change cancel pipeline. HLDEN: PSW.HLDEN used management accesses through external case multi-master system (refer Section 4.6.8 External Arbitration Multi-master Systems page 48). bit: PSW.IEN global interrupt enable bit. ILVL: PSW.ILVL bit-field selects interrupt priority level running context. Interrupt Status (IEN, ILVL) Interrupt Enable allows enable (IEN disable (IEN interrupts globally. four-bit Interrupt Level field (ILVL) specifies priority current activity. interrupt level updated hardware upon entry into interrupt service routine, also modified software prevent other interrupts from being acknowledged. case highest interrupt level '15' been assigned CPU, current operation cannot interrupted except hardware traps external maskable interrupts (NMI). After reset interrupts globally disabled, lowest priority (ILVL assigned initial activity (see Section Interrupt System Structure page detailed information).
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CENTRAL PROCESSING UNIT (CPU)
Super10 M345/M350
Code Addressing Super10 provides total addressable memory space Mbytes. This address space arranged segments Kbytes each. dedicated 24-bit code address pointer used access memories instruction fetches. This code address generated modes: segmented mode non-segmented mode. mode selected with CPUCON1.SGTDIS bit. After reset segmented mode selected. CPUCON1 (FE18h, 0Ch) Reset value: 0000h
Name SGTDIS Value WDTCTL SGTDIS INTSCXT
VECSC
Description Segmentation Disable/Enable Control Segmentation enabled (Default reset value) Segmentation disabled
Note:
CPUCON1 register covered write protection security system. write protected after execution EINIT instruction unless security level changed (See Section Register Write Protection Security System page details).
5.2.1 Segmented mode Code Segment Instruction Pointers segmented mode, address pointer parts: 8-bit Code Segment Pointer (CSP) 16-bit offset pointer called Instruction Pointer (IP). concatenation results directly correct 24-bit physical memory address shown Figure mentioned below, reset value determined level reset selects internal program memory (C0h) external memory (00h), register cleared. Figure Addressing Code Segment Instruction Pointer
Memory organized segments
FF'0000h FE'0000h
01'0000h 00'0000h segment
offset
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CENTRAL PROCESSING UNIT (CPU)
5.2.1.1 Instruction Pointer This register determines 16-bit intra-segment address currently fetched instruction within code segment selected register. register mapped into Super10's address space, thus directly accessible programmer. modified indirectly stack return instructions. register implicitly updated Super10 branch instructions after instruction fetch operations. Instruction Pointer
Reset value: 0000h
Name
Bits 15,.1
Value
Description Specifies intra-segment offset, from where current instruction fetched. refers current segment <SEGNR>. content always word-aligned
5.2.1.2 Code Segment Pointer This non-bit addressable register selects code segment being used run-time access instructions. lower bits register select segments Kbytes each, while higher bits reserved future use. register cannot written data operations. modified either directly JMPS CALLS instructions, indirectly stack RETS RETI instructions. Upon acceptance interrupt execution software TRAP instruction, register automatically loaded with segment address vector location. Code Segment Pointer (FE08h, 04h)
Name SEGNR Bits 15,.8 7,.0 Value Description These bits implemented, must kept "0", return value when read Specifies code segment, from where current instruction fetched.
Reset value: XXXXh
SEGNR
reset value specified contents VECSEG register (see Section 7.1.5 page 112).
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CENTRAL PROCESSING UNIT (CPU)
Vector Segment Pointer VECSEG (FF12h, 89h)
Name VECSEG Bits 15,.8 7,.0 Value Description
Super10 M345/M350
Reset Value: ????h
VECSEG
These bits implemented, must kept "0", return value when read Segment number Vector Table
Note:
reset value VECSEG depends state power-on reset: Super10 will start from external memory (00'0000h) when "0", VECSEG Super10 will start from Internal Program memory (C0'0000h) when pull "1", VECSEG (refer reset Section page details).
5.2.2 Non-Segmented Mode non-segmented mode enabled setting CPUCON1.SGTDIS bit. This done during initialization routine before execution EINIT instruction only (refer Section 8.1). non-segmented mode fixed value instruction which disabled segmentation. longer possible modify either directly JMPS CALLS instructions indirectly stack RETS (RETI) instruction. case interrupt processing software TRAP instruction, register automatically loaded with segment address VECSEG vector location (refer Section page detailed information). Note: correct execution interrupt tasks, contents VECSEG must same segment selected "frozen" CSP, i.e. vector table must located segment pointed CSP. Single Chip Mode contents register significant internal Program Memories accesses. -Data Addressing addressing modes, address calculation, symbols conventions used with standard instruction explained this section. Super10 contains independent arithmetic units generate, calculate update addresses data accesses, performing following major tasks: Standard Address Generation (Standard Address Generation Unit) Address Generation (DSP Address Generation Unit) Data Paging (Standard Address Generation Unit) System Stack Handling (Standard Address Generation Unit) Standard Address Unit supports linear arithmetic indirect addressing modes also generates address case other short long addressing modes. Address Generation Unit contains additional address pointers (Index registers registers) offset registers which used conjunction with CoXXX instructions only (see Section page 94). Super10 provides powerful addressing modes (short, long, indirect) word, byte data accesses. addressing modes different formats cover different scopes.
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CENTRAL PROCESSING UNIT (CPU)
5.3.1 Short Addressing Modes these addressing modes implicit base plus offset address specify 24-bit physical address. Short addressing modes allow access General Purpose Registers (GPR) (Extended) Special Function Registers (E)SFR bit-addressable memory space: Physical Address Base Address Short Address Note: byte access, word access. Table Short Addressing Modes
Mnemonic Physical Address (CP) local (CP) local 00'FE00h 00'F000h (CP) (reg0Fh) local (CP) (reg0Fh) local 00'FD00h bitoff 00'FF00h (bitoff7Fh) 00'F100h (bitoff7Fh) (CP) (bitoff0Fh) local Word offset with bitoff Immediate position with bitpos Short Address Range bitoff bitoff bitoff bitoff bitoff bitpos 0.15 0.15 00h.EFh 00h.EFh F0h.FFh F0h.FFh 00h.7Fh 80h.EFh 80h.EFh F0h.FFh 00h.FFh 0.15 Scope Access GPRs (Word) GPRs (Byte) SFRs ESFRs GPRs GPRs ESFR (Word, byte) (Word, byte) (Word) (Byte) word offset word offset word offset word offset
bitoff
bitaddr
single
mnemonics used addressing only. They specify direct access currently active context (global register bank local register bank). Both 'Rw' 'Rb' require four bits instruction format. base address global register bank determined contents register 'Rw' specifies 4-bit address relative base address (CP) used word, while 'Rb' specifies 4-bit address relative base address (CP) used byte. case active local register bank these bits used address local directly. register implied address generation. Specifies direct access (E)SFR currently active context (global local register bank). 'reg' value requires eight bits instruction format. Short 'reg' addresses range always specify (E)SFRs. that case, factor equates base address 00'FE00h standard area 00'F000h extended ESFR area. `reg' accesses ESFR area require preceding EXTx(R) instruction switch base address. Depending opcode either total word (for word operations) byte (for byte operations) addressed 'reg'. Note: high byte cannot accessed 'reg' addressing mode. Writing byte causes non-addressed complementary byte cleared!
Short 'reg' addresses range from always specify GPRs. only lower bits 'reg' significant physical address generation that similar 'Rb' 'Rw' addressing modes. Note: GPRs accessed word wise byte wise.
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CENTRAL PROCESSING UNIT (CPU)
Super10 M345/M350
bitoff Specifies direct access word bit-addressable memory space. 'bitoff' value requires eight bits instruction format. Depending specified 'bitoff' range different base addresses used generate physical addresses: Short 'bitoff' addresses range from 00'FD00h base address specify highest internal word locations range from 00'FD00hh 00'FDFEh. Short 'bitoff' addresses range from base address 00'FF00h specify internal word locations range from 00'FF00h 00'FFDEh, base address 00'F100h specify internal ESFR word locations range from 00'F100h 00'F1DEh. `bitoff' accesses ESFR area require preceding EXTx(R) instruction switch base address. short 'bitoff' addresses from FFh, only lowest four bits used generate address selected word GPR. bitaddr address specified word address within bit-addressable memory space (see 'bitoff'), position ('bitpos') within that word. Therefore, 'bitaddr' requires twelve bits instruction format. 5.3.2 Long Addressing Modes These addressing modes four registers specify 24-bit address. word byte data within entire address space accessed with these modes. 16-bit data address contains parts that have different meanings. Bits 13.0 specify 14-bit data page offset, while bits 15.14 specify Data Page Pointer (DPP) register which used generate full 24-bit address (see Figure 26). Super10 also supports override mechanism addressing scheme (EXTP(R) EXTS(R) instructions). following sections details. Note: Word accesses byte addresses executed trigger Illegal Word operand access (ILLOPA) hardware trap. Figure Data Page Addressing Mode
Memory Page number 1023 FF'0000h 1020 16-Bit Data Address
DPP0 DPP1 DPP2 DPP3 14-bit page offset
01'0000h 00'0000h 24-bit Physical Address Page Number
Page Offset
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Super10 M345/M350
CENTRAL PROCESSING UNIT (CPU)
5.3.2.1 Data Page Addressing Mode four non-bit addressable Data Page Pointer (DPP) registers select four different Kbyte data pages. registers implicitly used whenever data accesses memory location made indirect direct long 16-bit addressing modes (except override accesses EXTended instructions data transfers). Data paging performed concatenating lower bits 16-bit indirect direct long address with contents register. register selected upper bits 16-bit long address. lower bits each register select 1024 possible Kbyte data pages entire memory space. upper bits reserved future use. This 10-bit data page base address together with 14-bit page offset forms physical 24-bit address. After reset registers select data pages within segment user does want other data paging, further action required. Data Page Pointer DPP0 (FE00h, 00h)
Reset value: 0000h
Data Page Number
Data Page Pointer DPP1 (FE02h, 01h)
Reset value: 0001h
Data Page Number
Data Page Pointer DPP2 (FE04h, 02h)
Reset value: 0002h
Data Page Number
Data Page Pointer DPP3 (FE06h, 03h)
Name Bits 15,.10 9,.0 Value 1023,.0
Reset value: 0003h
Data Page Number Description
These bits implemented, must kept "0", return value when read Data Page Number Specifies data page selected DPP.
register updated instruction able modify SFR. write operation DPPx register could halt instruction flow internal instruction pipeline until actually updated. instruction that immediately follows instruction which updates register value changed DPPx.
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CENTRAL PROCESSING UNIT (CPU)
Super10 M345/M350
5.3.2.2 Override Mechanism Super10 provides address mechanism using EXTP(R) EXTS(R) instructions override addressing scheme temporarily. EXTP(R) instruction uses page mechanism EXTS(R) segment mechanism (refer Instruction Reference Guide detail Super10 instructions). EXTP(R) page override This mode uses (direct indirect) 10-bit constant encoded instruction format specify page number (#pag Rwm) segment number (#seg Rwm) 2-bit field (#irang) define many instructions have executed under EXTended sequence. Long Addressing mode referred mnemonic "mem". Table Long Addressing Mode Mnemonics
Mnemonic (DPP0) (DPP1) (DPP2) (DPP3) Physical Address mem3FFFh mem3FFFh mem3FFFh mem3FFFh mem3FFFh Scope Access Word Byte
Word Byte Word Byte
example EXTP instruction mnemonic direct mode EXTP #pag, #irang2 opcode format 01##-0 0-00pp] where bits #irang2 instructions sequence) 00pp defines immediate bits #page (the bold characters represent nibble, normal character represents bit). case indirect mode EXTP Rwm, #irang2 with format 01##-m] where bits #irang2 number that contains bits page address. immediate page value (#pag) contents register (Rwm) loaded temporary dedicated variable (Data_Page). instructions under EXTP(R) sequence using addressing scheme will substitute 10-bit
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