DESCRIPTIO 1.25Msps Sample Rate Power Dissipation: 160mW 71dB S/(
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LTC1410 12-Bit, 1.25Msps Sampling Converter with Shutdown FEATURES
DESCRIPTIO
1.25Msps Sample Rate Power Dissipation: 160mW 71dB S/(N 82dB Nyquist Pipeline Delay (7mW) Sleep (10µW) Shutdown Modes Operates with Internal 15ppm/°C Reference External Reference True Differential Inputs Reject Common Mode Noise 20MHz Full Power Bandwidth Sampling ±2.5V Bipolar Input Range 28-Pin Wide Package
LTC1410 0.65µs, 1.25Msps, 12-bit sampling converter that draws only 160mW from supplies. This easy-to-use device includes high dynamic range sample-and-hold, precision reference requires external components. digitally selectable power shutdown modes provide flexibility power systems. LTC1410's full-scale input range ±2.5V. Maximum specifications include ±1LSB ±1LSB over temperature. Outstanding performance includes 71dB S/(N 82dB Nyquist input frequency 625kHz. unique differential input sample-and-hold acquire single-ended differential input signals 20MHz bandwidth. 60dB common mode rejection allows users eliminate ground loops common mode noise measuring signals differentially from source. compatible, 12-bit parallel output port. There pipeline delay conversion results. separate convert start input data ready signal (BUSY) ease connections FIFOs, DSPs microprocessors.
registered trademarks Linear Technology Corporation.
APPLICATI
Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems
TYPICAL APPLICATI
Complete 1.25MHz, 12-Bit Sampling Converter
LTC1410 DIFFERENTIAL AVDD +AIN ANALOG INPUT (-2.5V 2.5V) -AIN DVDD 2.50V VREF OUTPUT REFCOMP BUSY 0.1µF AGND D11(MSB) CONVST SHDN NAP/SLP OGND 12-BIT PARALLEL DGND CONTROL LINES 10µF
Effective Bits Signal-to-(Noise Distortion) Input Frequency
fSAMPLE 1.25MHz 100k INPUT FREQUENCY (Hz)
LTC1410 TA02
10µF 0.1µF
EFFECTIVE BITS
0.1µF
10µF
1410 TA01
NYQUIST
S/(N (dB)
LTC1410 ABSOLUTE RATI PACKAGE/ORDER ATIO
VIEW +AIN -AIN VREF REFCOMP AGND D11(MSB) DGND PACKAGE 28-LEAD PLASTIC SSOP AVDD DVDD BUSY CONVST SHDN NAP/SLP OGND PACKAGE 28-LEAD PLASTIC WIDE
AVDD DVDD (Notes
Supply Voltage (VDD) Negative Supply Voltage (VSS) Total Supply Voltage (VDD VSS) Analog Input Voltage (Note 0.3V 0.3V Digital Input Voltage (Note 0.3V Digital Output Voltage 0.3V 0.3V Power Dissipation 500mW Operating Temperature Range LTC1410C 70°C LTC1410I 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1410CG LTC1410CSW LTC1410IG LTC1410ISW
TJMAX 110°C, 90°C/W (SW) TJMAX 110°C, 95°C/W
Consult factory Military grade parts.
VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With Internal Reference (Notes
CONDITIONS
±0.3 ±0.3
UNITS Bits ppm/°C
(Note (Note
IOUT(REF)
ALOG
SYMBOL PARAMETER tjitter CMRR
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS 4.75V 5.25V, 5.25V 4.75V High Between Conversions During Conversions
±2.5
UNITS
Analog Input Range (Note Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio
-1.5
psRMS
2.5V AIN) 2.5V
LTC1410
ACCURACY
SYMBOL S/(N
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
PARAMETER Signal-to-(Noise Distortion) Ratio Total Harmonic Distortion Peak Harmonic Spurious Noise Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth CONDITIONS 100kHz Input Signal (Note 600kHz Input Signal (Note 100kHz Input Signal, First Harmonics 600kHz Input Signal, First Harmonics 600kHz Input Signal fIN1 29.37kHz, fIN2 32.446kHz (S/(N 68dB)
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance COMP Output Voltage CONDITIONS IOUT IOUT 4.75V 5.25V 5.25V 4.75V IOUT 0.1mA IOUT
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
2.480 2.500 0.01 0.01 4.06 2.520 UNITS ppm/°C LSB/V LSB/V
DIGITAL PUTS DIGITAL OUTPUTS
SYMBOL PARAMETER High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage CONDITIONS 5.25V 4.75V 4.75V 10µA 200µA 4.75V 160µA 1.6mA VOUT VDD, High High (Note VOUT VOUT
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
Level Output Voltage
ISOURCE ISINK
High-Z Output Leakage High-Z Output Capacitance Output Source Current Output Sink Current
POWER REQUIRE
SYMBOL PARAMETER Positive Supply Voltage Negative Supply Voltage Positive Supply Current Mode Sleep Mode Negative Supply Current Mode Sleep Mode
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS (Notes (Note CONVST SHDN NAP/SLP SHDN NAP/SLP CONVST SHDN NAP/SLP SHDN NAP/SLP 4.75 4.75
72.5 71.0
UNITS
UNITS
0.05 0.10
5.25 5.25
UNITS
LTC1410
POWER REQUIRE
SYMBOL PARAMETER Power Dissipation Mode Sleep Mode
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS SHDN NAP/SLP SHDN NAP/SLP 0.01 UNITS
CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ tACQ+CONV PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Throughput Time (Acquisition Conversion) Setup Time CONVST Setup Time NAP/SLP SHDN Setup Time
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS
SHDN CONVST Wake-Up Time (Note CONVST Time (Notes CONVST BUSY Delay Data Ready Before BUSY 25pF
Delay Between Conversions Wait Time After BUSY Data Access Time After
Relinquish Time Commercial Industrial
Time CONVST High Time Aperture Delay Sample-and-Hold
Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect ground with DGND, OGND AGND wired together unless otherwise noted. Note When these voltages taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below above without latchup. Note When these voltages taken below VSS, they will clamped internal diodes. This product handle input currents greater than 100mA below without latchup. These pins clamped VDD. Note fSAMPLE 1.25MHz, unless otherwise specified. Note Linearity, offset full-scale specifications apply singleended +AIN input with grounded.
1.25
UNITS
(Notes (Notes (Notes
(Note (Note 25pF
100pF
Note Integral nonlinearity defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Bipolar offset offset voltage measured from 0.5LSB when output code flickers between 0000 0000 0000 1111 1111 1111. Note Guaranteed design, subject test. Note Recommended operating conditions. Note falling CONVST edge starts conversion. CONVST returns high critical point during conversion create small errors. best results ensure that CONVST returns high either within 425ns after start conversion after BUSY rises. Note Signal-to-noise ratio (SNR) measured 100kHz distortion measured 600kHz. These results used calculate signal-to-noise plus distortion (SINAD).
LTC1410 TYPICAL PERFORMANCE CHARACTERISTICS
S/(N Input Frequency Amplitude
SIGNAL/(NOISE DISTORTION) (dB) fSAMPLE 1.25MHz 100k INPUT FREQUENCY (Hz)
1410
AMPLITUDE BELOW FUNDAMENTAL)
SIGNAL-TO-NOISE RATIO (dB)
-20dB
-60dB
Spurious-Free Dynamic Range Input Frequency
SPURIOUS-FREE DYNAMIC RANGE (dB)
AMPLITUDE (dB)
-100 -120
ERROR (LSB)
-100
100k INPUT FREQUENCY (Hz)
AMPLITUDE POWER SUPPLY FEEDTHROUGH (dB)
Integral Nonlinearity Output Code
-100 -120 DGND
COMMON MODE REJECTION (dB)
ERROR (LSB)
-0.5
-1.0
1024 1536 2048 2560 3072 3504 4096 OUTPUT CODE
1410
1410
Signal-to-Noise Ratio Input Frequency
100k INPUT FREQUENCY (Hz)
1410
Distortion Input Frequency
100k INPUT FREQUENCY (Hz)
1410
-100
Intermodulation Distortion Plot
fSAMPLE 1.25MHz fIN1 88.19580078kHz fIN2 111.9995117kHz
Differential Nonlinearity Output Code
-0.5
-1.0
FREQUENCY (kHz)
1410
1024 1536 2048 2560 3072 3504 4096 OUTPUT CODE
1410
Power Supply Feedthrough Ripple Frequency
VRIPPLE 0.1V
Input Common Mode Rejection Input Frequency
100k RIPPLE FREQUENCY (Hz)
1410
100k INPUT FREQUENCY (Hz)
1410
LTC1410
CTIO
(Pin Positive Analog Input, ±2.5V. (Pin Negative Analog Input, ±2.5V. VREF (Pin 2.50V Reference Output. REFCOMP (Pin 4.06V Reference Bypass Pin. Bypass AGND with 10µF tantalum parallel with 0.1µF ceramic. AGND (Pin Analog Ground. (Pins 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground Internal Logic. AGND. (Pins 18): Three-State Data Outputs. OGND (Pin 19): Digital Ground Output Drivers. AGND. NAP/SLP (Pin 20): Power Shutdown Mode. Selects mode invoked SHDN pin. selects Sleep mode high selects quick wake-up mode. SHDN (Pin 21): Power Shutdown Input. logic level will invoke Shutdown mode selected NAP/SLP pin. (Pin 22): Read Input. This enables output drivers when low. CONVST (Pin 23): Conversion Start Signal. This active signal starts conversion falling edge. (Pin 24): Chip Select input must recognize CONVST inputs. BUSY (Pin 25): BUSY output shows converter status. when conversion progress. Data valid rising edge BUSY. (Pin 26): Negative Supply. Bypass AGND with 10µF tantalum parallel 0.1µF ceramic. DVDD (Pin 27): Positive Supply. Short AVDD (Pin 28): Positive Supply. Bypass AGND with 10µF tantalum parallel with 0.1µF ceramic.
CTIO BLOCK DIAGRA
+AIN CSAMPLE VREF 2.5V ZEROING SWITCHES AVDD DVDD
REFCOMP (4V) AGND DGND INTERNAL CLOCK
NAP/SLP SHDN CONVST
CSAMPLE
12-BIT CAPACITIVE COMP
OUTPUT LATCHES
SUCCESSIVE APPROXIMATION REGISTER
CONTROL LOGIC
BUSY
LTC1410
LTC1410
TEST CIRCUITS
Load Circuits Access Timing
100pF 100pF
Load Circuits Output Float Delay
Hi-Z
Hi-Z
1410 TC01
Hi-Z
Hi-Z
1410 TC02
APPLICATIONS INFORMATION
CONVERSION DETAILS LTC1410 uses successive approximation algorithm internal sample-and-hold circuit convert analog signal 12-bit parallel output. complete with precision reference internal clock. control logic provides easy interface microprocessors DSPs. (Please refer Digital Interface section data format.) Conversion start controlled CONVST inputs. start conversion successive approximation register (SAR) reset. Once conversion cycle begun cannot restarted. During conversion, internal differential 12-bit capacitive output sequenced from Most Significant (MSB) Least Significant (LSB). Referring Figure inputs connected sample-and-hold capacitors (CSAMPLE) during acquire phase comparator offset nulled zeroing switches. this acquire phase, minimum duration 100ns will provide enough time sample-and-hold capacitors acquire analog signal. During convert phase comparator zeroing switches open, putting comparator into compare mode. input switches connect CSAMPLE capacitors ground, transferring differential analog input charge onto summing junctions. This input charge successively compared with binarily-weighted charges supplied differential capacitive DAC. decisions made high speed comparator. conversion, differential output balances input charges. contents 12-bit data word) which represent difference loaded into 12-bit output latches.
+CSAMPLE +AIN SAMPLE HOLD -CSAMPLE SAMPLE HOLD +CDAC ZEROING SWITCHES HOLD HOLD
-CDAC +VDAC -VDAC OUTPUT LATCHES
1410
COMP
Figure Simplified Block Diagram
LTC1410
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE LTC1410 excellent high speed sampling capability. Fast Four Transform (FFT) test techniques used test ADC's frequency response, distortion noise rated throughput. applying distortion sine wave analyzing digital output using algorithm, ADC's spectral content examined frequencies outside fundamental.
-100 -120 FREQUENCY (kHz)
1410 F02a
fSAMPLE 1.25MHz 100.098kHz SFDR 90.1dB SINAD 72.4dB
AMPLITUDE (dB)
EFFECTIVE BITS
Figure LTC1410 Nonaveraged 4096 Point FFT, 100kHz Input
fSAMPLE 1.25MHz 599.975kHz SFDR 84.7dB SINAD 71.7dB
AMPLITUDE (dB)
-100 -120 FREQUENCY (kHz)
1410 F02b
Figure LTC1410 Nonaveraged 4096 Point FFT, 600kHz Input
Signal-to-Noise Ratio Signal-to-Noise plus Distortion ratio [S/(N ratio between amplitude fundamental input frequency amplitude other frequency components output. output band limited
frequencies from above below half sampling frequency. Figures shows typical spectral content with 1.25MHz sampling rate 100kHz 600kHz inputs. dynamic performance excellent input frequencies Nyquist limit 625kHz beyond. Effective Number Bits Effective Number Bits (ENOBs) measurement resolution directly related S/(N equation: [S/(N 1.76] 6.02 where effective number bits resolution S/(N expressed maximum sampling rate 1.25MHz LTC1410 maintains very good ENOBs Nyquist input frequency 625kHz beyond. Refer Figure
fSAMPLE 1.25MHz 100k INPUT FREQUENCY (Hz)
LTC1410 TA02
NYQUIST
S/(N (dB)
Figure Effective Bits Signal/(Noise Distortion) Input Frequency
Total Harmonic Distortion (THD) Total harmonic distortion ratio harmonics input signal fundamental itself. out-of-band harmonics alias into frequency band between half sampling frequency. expressed
LTC1410
APPLICATIONS INFORMATION
where amplitude fundamental frequency through amplitudes second through harmonics. Input Frequency shown Figure LTC1410 good distortion performance Nyquist frequency beyond.
AMPLITUDE BELOW FUNDAMENTAL) 100k INPUT FREQUENCY (Hz)
1410
AMPLITUDE (dB)
-100
Figure Distortion Input Frequency
Intermodulation Distortion (IMD) input signal consists more than spectral component, transfer function nonlinearity produce Intermodulation Distortion addition THD. change sinusoidal input caused presence another sinusoidal input different frequency. pure sine waves frequencies applied input, nonlinearities transfer function create distortion products difference frequencies nfb, where etc. example, order terms include fb). input sine waves equal magnitude, value decibels) order products expressed following formula:
Amplitude Amplitude
(fa) -100 -120 (fb) fSAMPLE 1.25MHz fIN1 88.19580078kHz fIN2 111.9995117kHz
(2fa-fb) (fb-fa)
(2fb-fa) (fa+fb) (2fa+fb) (2fa) (2fb) (fa+2fb) (3fa) (3fb)
FREQUENCY (MHz)
1410
Figure Intermodulation Distortion Plot
Peak Harmonic Spurious Noise peak harmonic spurious noise largest spectral component excluding input signal This value expressed decibel relative value full-scale input signal. Full Power Full Linear Bandwidth full power bandwidth that input frequency which amplitude reconstructed fundamental reduced full-scale input signal. full linear bandwidth input frequency which S/(N dropped 68dB effective bits). LTC1410 been designed optimize input bandwidth, allowing undersample input signals with frequencies above converter's Nyquist frequency. noise floor stays very high frequencies; S/(N does become dominated distortion until frequencies beyond Nyquist. Driving Analog Input differential analog inputs LTC1410 easy drive. inputs driven differentially single-ended input (i.e., input grounded). inputs sampled same instant. unwanted signal that common mode both inputs will reduced common mode rejection sample-and-hold circuit. inputs draw only small current spike while charging sample-and-hold
LTC1410
APPLICATIONS INFORMATION
capacitors conversion. During conversion analog inputs draw only small leakage current. source impedance driving circuit then LTC1410 inputs driven directly. source impedance increases will acquisition time (see Figure minimum acquisition time with high source impedance, buffer amplifier should used. only requirement that amplifier driving analog input(s) must settle after small current spike before next conversion starts (settling time must 100ns full throughput rate).
ACQUISITION TIME (µs)
10µF 0.1µF
LTC1410
1410
0.01
SOURCE RESISTANCE
100k
1410
Figure Acquisition Time Source Resistance
Choosing input amplifier easy requirements taken into consideration. First, choose amplifier that output impedance 100) closedloop bandwidth frequency. example, amplifier used gain closed-loop bandwidth 50MHz, then output impedance 50MHz must less than 100. second requirement that closed-loop bandwidth must greater than 20MHz ensure adequate small-signal settling full throughput rate. slower amps used, more settling time provided increasing time between conversions. Suitable devices capable driving ADC's inputs include ®1360, LT1220, LT1223, LT1224 LT1227 amps. noise distortion input amplifier must also considered since they will LTC1410 noise distortion. small-signal bandwidth
sample-and-hold circuit 20MHz. noise that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter usually sufficient. example, Figure shows 1000pF capacitor from ground source resistor will limit input bandwidth 1.6MHz. Simple filters work well applications, they will limit transient response. full speed operation, amplifiers with fast settling noise should chosen.
ANALOG INPUT 1000pF +AIN -AIN VREF REFCOMP AGND
Figure Input Filter
Internal Reference LTC1410 on-chip, temperature compensated, curvature corrected, bandgap reference which factory trimmed 2.500V. connected internally reference amplifier available VREF (Pin Figure resistor series with output that
ANALOG INPUT
+AIN -AIN
LTC1410
2.500V 4.06V
VREF REFCOMP 0.1µF AGND
BANDGAP REFERENCE
10µF
1410 F08a
Figure LTC1410 Reference Circuit
LTC1410
APPLICATIONS INFORMATION
easily overdriven applications where external reference required. reference amplifier provides buffering between internal reference capacitive DAC. reference amplifier compensation REFCOMP (Pin must bypassed with capacitor ground. reference amplifier stable with capacitors greater. best noise performance, 10µF tantalum parallel with 0.1µF ceramic recommended. VREF driven with external reference (Figure 8b), other means provide input span adjustment. VREF should kept range 2.25V 2.75V specified linearity.
LT1019A-2.5 VOUT ANALOG INPUT 10µF 0.1µF +AIN -AIN VREF REFCOMP AGND LTC1410
1410 F08b
OUTPUT CODE
Figure Using LT1019-2.5 External Reference
Full-Scale Offset Adjustment
10µF
Figure shows ideal input/output characteristics LTC1410. code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, 1.5LSB, 0.5LSB).The output two's complement binary with 1LSB [(+FS) FS)]/4096 5V/4096 1.22mV. applications where absolute accuracy important, offset full-scale errors adjusted zero. Offset error must adjusted before full-scale error. Figure shows extra components required full-scale error adjustment. Zero offset achieved adjusting offset applied input. zero offset error apply 0.61mV (i.e., 0.5LSB) +AIN adjust offset input until output code flickers between 0000 0000 0000 1111 1111 1111. full-scale adjustment, input voltage 2.49817V 1.5LSBs)
applied adjusted until output code flickers between 0111 1111 1110 0111 1111 1111.
011.111 011.110 BIPOLAR ZERO
000.001 000.000 111.111 111.110 2.5V 1LSB 4096 INPUT VOLTAGE, (+AIN) (-AIN)
1410
100.001 100.000
Figure LTC1410 Transfer Characteristics
ANALOG INPUT
+AIN -AIN VREF REFCOMP AGND LTC1410
1410
0.1µF
Figure Offset Full-Scale Adjust Circuit
BOARD LAYOUT BYPASSING Wire wrap boards recommended high resolution high speed converters. obtain best performance from LTC1410, printed circuit board with ground plane required. Layout printed circuit board should ensure that digital analog signal lines separated much possible. Particular care should taken digital track alongside analog signal track underneath ADC. analog input should screened AGND.
LTC1410
APPLICATIONS INFORMATION
High quality tantalum ceramic bypass capacitors should used VDD, REFCOMP pins shown Typical Application first page this data sheet. Bypass capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible. LTC1410 differential inputs minimize noise coupling. Common mode noise leads will rejected input CMRR. input used ground sense input; LTC1410 will hold convert difference voltage between AIN. leads (Pin (Pin should kept short possible. applications where this possible, traces should side side equalize coupling. single point analog ground separate from logic system ground should established with analog ground plane (AGND) close possible ADC. (ADC's DGND) other analog grounds should connected this single analog ground point. other digital grounds should connected this analog ground point. impedance analog digital power supply common returns essential noise operation foil width these tracks should wide possible. applications where data outputs control signals connected continuously active microprocessor bus, possible errors conversion results. These errors feedthrough from microprocessor successive approximation comparator. problem eliminated forcing microprocessor into wait state during conversion using three-state buffers isolate data bus. DIGITAL INTERFACE converter designed interface with microprocessors memory mapped device. control inputs common peripheral memory interfacing. separate CONVST used initiate conversion. Internal Clock converter internal clock that eliminates need synchronization between external clock signals found other ADCs. internal clock factory trimmed achieve typical conversion time 0.65µs maximum conversion time over full operating temperature range 0.75µs. external adjustments required. guaranteed maximum acquisition time 100ns. addition, throughput time 800ns minimum sampling rate 1.25Msps guaranteed.
REFCOMP AGND
ANALOG INPUT CIRCUITRY
10µF
0.1µF
Figure Power Supply Grounding Practice
LTC1410 10µF 0.1µF 10µF AVDD DVDD DGND OGND 0.1µF
DIGITAL SYSTEM
1410
LTC1410
APPLICATIONS INFORMATION
Power Shutdown LTC1410 provides power shutdown modes, Sleep, save power during inactive periods. mode reduces power leaves only digital logic reference powered wake-up time from active 200ns. Sleep mode bias currents shut down only leakage current remains about 1µA. Wake-up time from Sleep mode
NAP/SLP SHDN
1410 F12a
Figure 12a. NAP/SLP SHDN Timing
SHDN CONVST
1410 F12b
Figure 12b. SHDN CONVST Wake-Up Timing
much slower since reference circuit must power settle 0.01% full 12-bit accuracy. Sleep mode wake-up time dependent value capacitor connected REFCOMP (Pin wake-up time 10ms with recommended 10µF capacitor. Shutdown controlled (SHDN), shutdown when low. shutdown mode selected with (NAP/SLP); high selects Nap.
CONVST
1410
Figure CONVST Setup Timing
Timing Control Conversion start data read operations controlled three digital inputs: CONVST, logic applied CONVST will start conversion after been selected (i.e., low). Once initiated, cannot restarted until conversion complete. Converter status indicated BUSY output. BUSY during conversion. Figures through show several different modes operation. modes (Figures both tied low. falling edge CONVST starts conversion. data outputs always enabled data latched with BUSY rising edge. Mode shows operation with narrow logic CONVST pulse. Mode shows narrow logic high CONVST pulse. mode (Figure tied low. falling edge CONVST signal again starts conversion. Data outputs three-state until read with signal. Mode used operation with shared databus. slow memory modes (Figures tied CONVST tied together. starts conversion reads output with signal. Conversions started external sample clock). slow memory mode processor applies logic CONVST), starting conversion. BUSY goes forcing processor into wait state. previous conversion result appears data outputs. When conversion complete, conversion results appear data outputs; BUSY goes high releasing processor processor takes CONVST) back high reads conversion data. mode, processor takes CONVST) low, starting conversion reading previous conversion result. After conversion complete, processor read result initiate another conversion.
LTC1410
APPLICATIONS INFORMATION
CONVST BUSY DATA DATA DB11 DATA DB11 DATA DB11
1410
Figure Mode CONVST Starts Conversion. Data Outputs Always Enabled
(CONVST
CONVST BUSY
tCONV
DATA
DATA DB11
Figure Mode CONVST Starts Conversion. Data Outputs Always Enabled
(CONVST
tCONV CONVST BUSY DATA
Figure Mode CONVST Starts Conversion. Data Read
CONV
DATA DB11 DATA DB11
1410
DATA DB11
1410
LTC1410
APPLICATI
ATIO
CONV
CONVST BUSY DATA DATA DB11 DATA DB11 DATA DB11 DATA DB11-DB0
1410
Figure Slow Memory Mode Timing
CONV CONVST BUSY DATA DATA DB11 DATA DB11
1410
Figure Mode Timing
PACKAGE DESCRIPTIO
Dimensions inches (millimeters) unless otherwise noted. Package 28-Lead Plastic SSOP (0.209)
(LTC 05-08-1640)
0.397 0.407* (10.07 10.33)
0.205 0.212** (5.20 5.38)
0.005 0.009 (0.13 0.22)
0.022 0.037 (0.55 0.95)
*DIMENSIONS INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSIONS INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
0.301 0.311 (7.65 7.90)
0.068 0.078 (1.73 1.99)
0.0256 (0.65)
0.010 0.015 (0.25 0.38)
0.002 0.008 (0.05 0.21)
SSOP 0694
LTC1410
PACKAGE DESCRIPTIO
Dimensions inches (millimeters) unless otherwise noted.
Package 28-Lead Plastic Small Outline (Wide 0.300)
(LTC 05-08-1620)
0.697 0.712* (17.70 18.08)
NOTE
0.394 0.419 (10.007 10.643)
0.291 0.299** (7.391 7.595) 0.010 0.029 (0.254 0.737)
0.093 0.104 (2.362 2.642)
0.037 0.045 (0.940 1.143)
0.009 0.013 (0.229 0.330)
NOTE 0.016 0.050 (0.406 1.270)
0.050 (1.270)
NOTE: IDENT, NOTCH CAVITIES BOTTOM PACKAGES MANUFACTURING OPTIONS. PART SUPPLIED WITH WITHOUT OPTIONS *DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
0.014 0.019 (0.356 0.482)
0.004 0.012 (0.102 0.305)
(WIDE) 0996
RELATED PARTS
12-Bit Sampling Converters
PART NUMBER LTC1273/75/76 LTC1274/77 LTC1278/79 LTC1282 DESCRIPTION Complete Sampling 12-Bit ADCs with 70dB SINAD Nyquist Power 12-Bit ADCs with Sleep Mode Shutdown High Speed Sampling 12-Bit ADCs with Shutdown Complete 12-Bit ADCs with 12mW Power Dissipation COMMENTS Lower Power Cost Effective fSAMPLE 300ksps Lowest Power fSAMPLE 100ksps Cost Effective 12-Bit ADCs Best 2-Pair HDSL, fSAMPLE 500ksps/600ksps Fully Specified 3V-Powered Applications, fSAMPLE 140ksps
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
(408)432-1900 FAX: (408) 434-0507 www.linear-tech.com
1410fa LT/TP 0399 PRINTED
LINEAR TECHNOLOGY CORPORATION 1995
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