DESCRIPTIO 5Msps Sample Rate Power Dissipation: 115mW Single Supp
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LTC1405 12-Bit, 5Msps, Sampling
DESCRIPTIO
5Msps Sample Rate Power Dissipation: 115mW Single Supply Supplies Integral Nonlinearity Error <0.35LSB Differential Nonlinearity <0.25LSB 71.3dB S/(N 85dB SFDR Nyquist 100MHz Full-Power Bandwidth Sampling ±2.048V, ±1.024V ±0.512V Bipolar Input Range Input Out-of-Range Indicator True Differential Inputs with 75dB CMRR 28-Pin Narrow SSOP Package Pin-Compatible 10Msps Version (LTC1420)
LTC1405 5Msps, 12-bit sampling converter that draws only 115mW from either single dual supplies. This easy-to-use device includes high dynamic range sample-and-hold, precision reference input circuit. LTC1405 flexible input circuit that allows full-scale input ranges ±2.048V, ±1.024V ±0.512V. input common mode range rail-to-rail common mode bias voltage provided single supply applications. input digitally selectable gain. Maximum specs include ±1LSB ±1LSB over temperature. Outstanding performance includes 71.3dB S/(N 85dB SFDR Nyquist input frequency 2.5MHz. unique differential input sample-and-hold acquire single-ended differential input signals 100MHz bandwidth. 75dB common mode rejection allows users eliminate ground loops common mode noise measuring signals differentially from source. separate output logic supply allows direct connection components.
APPLICATIO
Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectral Analysis Imaging Systems
registered trademarks Linear Technology Corporation.
TYPICAL APPLICATION
GAIN (PIN (PIN OVDD OPTIONAL LOGIC SUPPLY
-AIN MODE SELECT SENSE
PIPELINED 12-BIT
OUTPUT BUFFERS
(LSBs)
(MSB)
DIGITAL CORRECTION LOGIC 2.5V REFERENCE
(LSB) 5MHz
VREF 2.048V
1405 TA01
(PIN
(PIN
(PIN
OGND
Typical Curve
1.00 0.75 0.50 0.25 -0.25 -0.50 -0.75 -1.00 1024 2048 CODE 3072 4096
1405 TA02
LTC1405
ABSOLUTE
RATI
PACKAGE/ORDER ATIO
VIEW +AIN -AIN SENSE VREF (MSB) GAIN OVDD OGND
0VDD (Notes
Supply Voltage (VDD) Negative Supply Voltage (VSS) Total Supply Voltage (VDD VSS) Analog Input Voltage (Note (VSS 0.3V) (VDD 0.3V) Digital Input Voltage (Note (VSS 0.3V) (VDD 0.3V) Digital Output Voltage (VSS 0.3V) (VDD 0.3V) Power Dissipation 500mW Operating Temperature Range LTC1405C 70°C LTC1405I 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1405CGN LTC1405IGN
PACKAGE 28-LEAD PLASTIC SSOP TJMAX 110°C, 110°C/W
Consult factory parts specified with wider operating temperature ranges.
VERTER CHARACTERISTICS
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With Internal 4.096V Reference. Specifications guaranteed both dual supply single supply operation. (Note
PARAMETER Resolution Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco IOUT(REF) (Note
CONDITIONS
±0.35 ±0.25
UNITS Bits ppm/°C
(Note
ALOG denotes specifications which apply over full operating temperature range, otherwise
specifications 25°C. Specifications guaranteed both dual supply single supply operation. (Note
PARAMETER Analog Input Range (Note +AIN (-AIN) CONDITIONS VREF 4.096V (SENSE 0V), GAIN VREF 4.096V (SENSE 0V), GAIN VREF 2.048V (SENSE VREF), GAIN VREF 2.048V (SENSE VREF), GAIN External VREF (SENSE 5V), GAIN External VREF (SENSE 5V), GAIN Between Conversions During Conversions
SYMBOL
±2.048 ±1.024 ±1.024 ±0.512 ±VREF/2 ±VREF/4
UNITS
tACQ
Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time
LTC1405 ALOG denotes specifications which apply over full operating temperature range, otherwise
specifications 25°C. Specifications guaranteed both dual supply single supply operation. (Note
PARAMETER Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio -2.048V (-AIN +AIN) 2.048V CONDITIONS SYMBOL tjitter CMRR UNITS
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. fSAMPLE 5MHz, VREF 4.096V. 0.1dBFS single ended input, (Note
SYMBOL S/(N SFDR PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Peak Harmonic Spurious Noise Intermodulation Distortion Full-Power Bandwidth Input Referred Noise ±2.048V Input Range ±1.024V Input Range, Mode (SENSE GAIN CONDITIONS 1MHz Input Signal 2.5MHz Input Signal 1MHz Input Signal, First Harmonics 2.5MHz Input Signal, First Harmonics 1MHz Input Signal 2.5MHz Input Signal fIN1 29.37kHz, fIN2 32.446kHz
ACCURACY
REFERE CHARACTERISTICS
25°C. Specifications guaranteed both dual supply single supply operation. (Note
PARAMETER Output Voltage Output Tempco Line Regulation Output Resistance VREF Output Voltage CONDITIONS IOUT IOUT 4.75V 5.25V 5.25V -4.75V 0.1mA IOUT 0.1mA SENSE GND, IOUT SENSE VREF, IOUT SENSE 2.475 2.500 0.03 4.096 2.048 Drive VREF with External Reference 2.525 UNITS ppm/°C mV/V mV/V ppm/°C
VREF Output Tempco
DIGITAL PUTS OUTPUTS
SYMBOL PARAMETER High Level Input Voltage Level Input Voltage
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. Specifications guaranteed both dual supply single supply operation. (Note
CONDITIONS 5.25V, 5.25V, 4.75V, 4.75V,
69.0 68.7
71.6 71.3 0.22 0.33
UNITS
78.5 77.0 79.5 78.0
LSBRMS LSBRMS
UNITS
LTC1405
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. Specifications guaranteed both dual supply single supply operation. (Note
SYMBOL PARAMETER Digital Input Current Digital Input Capacitance High Level Output Voltage 0VDD 4.75V, -10µA 0VDD 4.75V, -200µA 0VDD 2.7V, -10µA 0VDD 2.7V, -200µA 0VDD 4.75V, 160µA 0VDD 4.75V, 1.6mA 0VDD 2.7V, 160µA 0VDD 2.7V, 1.6mA VOUT VOUT
DIGITAL PUTS OUTPUTS
Level Output Voltage
ISOURCE ISINK
Output Source Current Output Sink Current
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. Specifications guaranteed both dual supply single supply operation. (Note
SYMBOL PARAMETER Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation CONDITIONS (Note Dual Supply Mode Single Supply Mode
POWER REQUIRE
CHARACTERISTICS
SYMBOL fSAMPLE tCONV tACQ PARAMETER Sampling Frequency Conversion Time Acquisition Time High Time Time Aperture Delay Sample-and-Hold
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. Specifications guaranteed both dual supply single supply operation. (Note
CONDITIONS
Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect ground with OGND wired together (unless otherwise noted). Note When these voltages taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below above without latchup.
CONDITIONS
UNITS
4.74 4.71 0.05 0.10 0.05 0.10
4.75 5.25
5.25 4.75
UNITS
0.02
UNITS
(Note (Note
Note When these voltages taken below they will clamped internal diodes. This product handle input currents greater than 100mA below without latchup. GAIN clamped VDD. When taken above VDD, will clamped internal diode. handle input currents greater than 100mA above without latchup. Note fSAMPLE 5MHz, unless otherwise specified.
LTC1405
ELECTRICAL CHARACTERISTICS
Note Dynamic specifications guaranteed dual supply operation with single-ended input grounded. single supply dynamic specifications, refer Typical Performance Characteristics. Note Integral nonlinearity defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Bipolar offset offset voltage measured from -0.5LSB when output code flickers between 0000 0000 0000 1111 1111 1111. Note Guaranteed design, subject test. Note Recommended operating conditions.
TYPICAL PERFORMANCE CHARACTERISTICS
S/(N+D) Input Frequency Amplitude
S/(N (dB)
DUAL SUPPLIES ±2.048V RANGE GAIN 2.5MHz INPUT AMPLITUDE (dBFS)
1405
DUAL SUPPLIES ±2.048V RANGE GAIN
DISTORTION (dB)
-6dB
SFDR (dBc dBFS)
-20dB
INPUT FREQUENCY (MHz)
S/(N+D) Input Frequency Amplitude
SINGLE SUPPLY ±1.024V RANGE GAIN
SFDR (dBc dBFS)
S/(N (dB)
-6dB
SINGLE SUPPLY ±1.024V RANGE GAIN 2.5MHz INPUT AMPLITUDE (dBFS)
1405
DISTORTION (dB)
-20dB INPUT FREQUENCY (MHz)
1405
1405
Spurious-Free Dynamic Range Input Amplitude
Distortion Input Frequency
DUAL SUPPLIES ±2.048V RANGE GAIN 0dBFS
dBFS
INPUT FREQUENCY (MHz)
1405
Spurious-Free Dynamic Range Input Amplitude
dBFS
Distortion Input Frequency
INPUT FREQUENCY (MHz)
1405
SINGLE SUPPLY ±1.024V RANGE GAIN 0dBFS
LTC1405 TYPICAL PERFORMANCE CHARACTERISTICS
SFDR Input Frequency, Differential Input
SFDR (dB) SFDR (dB) -100 INPUT FREQUENCY (MHz)
1405
DUAL SUPPLIES ±2.048V RANGE GAIN 0dBFS
HITS
Clock Frequency
(mA)
(mA)
VREF 4.096V VREF 2.048V
CMRR (dB)
CLOCK FREQUENCY (MHz)
1405
AMPLITUDE (dB)
SFDR Input Frequency, Differential Input
SINGLE SUPPLY ±1.024V RANGE GAIN 0dBFS
Grounded Input Histogram
VREF 4.096V GAIN 410554
-100 INPUT FREQUENCY (MHz)
1405
1570 CODE
1572
1420
Clock Frequency
CMRR Input Frequency
CLOCK FREQUENCY (MHz)
1405
0.01
INPUT FREQUENCY (MHz)
1405
LTC1405 Nonaveraged 4096 Point
fSAMPLE 5Msps 2.515869141MHz SFDR 86.2dB SINAD 71.3dB 4VP-P SUPPLIES
-100 -120
FREQUENCY (MHz)
1405
LTC1405
CTIO
(Pin Positive Analog Input. (Pin Negative Analog Input. (Pin 2.5V Reference Output.Optional input common mode single supply operation. Bypass with 10µF ceramic. SENSE (Pin Reference Programming Pin. Ground selects VREF 4.096V. Short VREF 2.048V. Connect SENSE drive VREF with external reference. VREF (Pin Reference. Bypass with 10µF ceramic. (Pin Reference Ground. (Pin Analog Supply. Bypass with 10µF ceramic. (Pin Analog Power Ground. (Pins 20): Data Outputs. output format two's complement. OGND (Pin 21): Output Logic Ground. GND. OVDD (Pin 22): Positive Supply Output Logic. Connect logic. shorted bypass with ceramic. (Pin 23): Analog Supply. Bypass with ceramic. (Pin 24): Analog Power Ground. (Pin 25): Negative Supply. shorted GND, bypass with ceramic. (Pin 26): Conversion Start Signal. This active high signal starts conversion rising edge. (Pin 27): Overflow Output. This signal high when digital output 011111111111 100000000000. GAIN (Pin 28): Gain Select Input PGA. selects input gain selects gain
LTC1405
CTIO BLOCK DIAGRA
GAIN
-AIN MODE SELECT SENSE
VREF 2.048V
DIAGRA
ANALOG INPUT
tCLOCK
tCONV tACQ DATA OUTPUT
1405
(PIN (PIN OVDD OPTIONAL LOGIC SUPPLY PIPELINED 12-BIT (MSB) OUTPUT BUFFERS DIGITAL CORRECTION LOGIC (LSB) 2.5V REFERENCE
1405
(PIN
(PIN
(PIN
OGND
LTC1405
APPLICATIO ATIO
Conversion Details
LTC1405 high performance 12-bit converter that operates 5Msps. complete solution with on-chip sample-and-hold, 12-bit pipelined CMOS ADC, drift programmable reference input programmable gain amplifier. digital output parallel, with 12-bit two's complement format out-ofrange (overflow) bit. rising edge begins conversion. differential analog inputs simultaneously sampled passed pipelined A/D. After more conversion starts (plus 150ns conversion time) digital outputs updated with conversion result will ready capture third rising clock edge. Thus even though conversion begun every time goes high, each result takes three clock cycles reach output. analog signals that passed from stage stage pipelined stored capacitors. signals these capacitors will lost delay between conversions long. accurate conversion results, part should clocked faster than 20kHz. some pipelined converters there clock present, dynamic logic chip will droop power consumption sharply increases. LTC1405 doesn't have this problem. part clocked 1ms, internal timer will refresh dynamic logic. Thus clock turned long periods time save power. Power Supplies LTC1405 will operate from either single dual supply, making easy interface analog input single dual supply systems. digital output drivers have their power supply (OVDD) which from allowing direct connection either digital systems. single supply operation, should connected analog ground. dual supply operation, should connected Both pins should connected clean analog supply. (Don't connect noisy system digital supply.)
Analog Input Ranges LTC1405 flexible analog input with wide selection input ranges. input range always differential voltages VREF GAIN pins (Figure input range core fixed ±VREF/2. reference voltage, VREF, either on-chip voltage reference directly driven external voltage. GAIN digital input that controls gain preamplifier sample-and-hold circuit. gain this Table gives input range terms VREF GAIN.
Table
GAIN (Logic (Logic
GAIN 1x/2x +AIN ±VREF/2 CORE
GAIN
INPUT RANGE (VIN VREF/2 VREF/2 VREF/4 VREF/4
-AIN
VREF
1405
Figure Analog Input Circuit
Internal Reference Figure shows simplified schematic LTC1405 reference circuitry. on-chip temperature compensated bandgap reference (VCM) factory trimmed 2.500V. voltage VREF sets input span ±VREF/2. internal voltage divider converts 2.048V, which connected reference amplifier. reference programming pin, SENSE, controls reference amplifier drives VREF pin. SENSE tied ground, reference amplifier feedback connected R1/R2 voltage divider, thus making VREF 4.096V. SENSE tied VREF, reference amplifier feedback connected SENSE thus making VREF 2.048V. SENSE tied VDD, reference amplifier disconnected from VREF VREF driven external voltage. With additional resistors, VREF voltage between 2.048V 4.5V.
LTC1405
APPLICATIO ATIO
external reference used drive VREF over range (Figures 3b). input impedance VREF buffer required high accuracy. Driving VREF with useful applications where peak input signal amplitude vary. input span then adjusted match peak input signal, maximizing signal-to-noise ratio. Both VREF pins must bypassed with capacitors ground. best performance, larger ceramic capacitors recommended. case external circuitry driving VREF, smaller capacitor used VREF input range changed quickly. this case, 0.05µF larger ceramic capacitor acceptable. output impedance 2.5V reference that used external circuitry. single supply applications convenient connect directly pin. Driving Analog Inputs differential inputs LTC1405 easy drive. inputs driven differentially single-ended input held fixed value). inputs simultaneously sampled common mode signal reduced high common mode rejection sample-and-hold circuit. common mode input value acceptable long input pins stay between VSS. During conversion analog inputs high impedance. conversion inputs draw small current spike while charging sample-and-hold. superior dynamic performance dual supply mode, LTC1405 should operated with analog inputs centered ground, single supply mode inputs should centered 2.5V. required, analog inputs driven differentially transformer. Refer Table summary analog input reference configurations their relative advantages.
VREF
SENSE LOGIC 2.5V REFERENCE 2.048V
1405
Figure Reference Circuit
VOUT LT1019A-2.5 VREF LTC1405 SENSE
1405 F03a
Figure Using LT1019-2.5 External Reference; Input Range ±1.25V
LTC1405
VREF SENSE LTC1450
2.048V
1405 F03b
Figure Driving VREF with
LTC1405
APPLICATIO ATIO
Table Comparison Analog Input Configurations
SUPPLIES COUPLING (Transformer) (Transformer) VREF 4.096V 4.096V 2.048V 4.096V 4.096V 4.096V 4.096V
GAIN
Coupling Input most applications analog input signal directly coupled LTC1405 inputs. input signal centered around ground, such when dual supply amps used, simply connect ground connect (Figure single power supply system with input signal centered around 2.5V, connect ground (Figure input signal centered around ground 2.5V, voltage must generated externally resistor divider voltage reference (Figure
4.096V 2.048V +AIN
+AIN LTC1405 -AIN
1405
Figure Coupling Ground Centered Signal (Dual Supply System)
2.5V
+AIN LTC1405 -AIN
1405
Figure Coupling Signal Centered Around 2.5V (Single Supply System)
±2.048 1.024 1.024 2.048 4.096 ±1.024 1.024 2.048 ±1.024 1.024 COMMENTS Best SNR, Best SINAD, Single Supply Worse Noise than Above Case Best Single Supply Noise, Optimal Same Above Very Best SNR, Very Best SNR, Single Supply
LTC1405 -AIN SENSE
1405
Figure Coupling 4.096V Signal
Coupling Input analog inputs LTC1405 also coupled through capacitor, though most cases simpler directly couple input ADC. Figure shows example where input signal centered around ground operates from single supply. Note that performance would improve operated from dual supply input directly coupled Figure With coupling resistance ground should roughly matched maintain offset accuracy.
+AIN LTC1405 -AIN
1405
Figure Coupling LTC1405. Note That Input Signal Almost Always Directly Coupled with Better Performance
LTC1405
APPLICATIO ATIO
Differential Operation
SFDR performance LTC1405 improved using center transformer drive inputs differentially. Though signal longer coupled, improvement dynamic performance makes this attractive solution some applications. Typical connections single dual supply systems shown Figures Good choices transformers Mini Circuits T1-1T (1:1 turns ratio) T4-6T (1:4 turns ratio). best results transformer should located close LTC1405 printed circuit board.
MINI CIRCUITS T1-1T +AIN 1000pF LTC1405 -AIN
1405 F08a
Figure Single Supply Transformer Coupled Input
MINI CIRCUITS T1-1T +AIN 1000pF LTC1405 -AIN
1405 F08b
Figure Dual Supply Transformer Coupled Input
Choosing Input Amplifier Choosing input amplifier easy requirements taken into consideration. First, limit magnitude voltage spike seen amplifier from charging sampling capacitor, choose amplifier that output impedance (<100) closed-loop bandwidth frequency. example, amplifier used gain unity-gain bandwidth 50MHz, then output impedance 50MHz must less than 100. second requirement that closed-loop bandwidth
must greater than 50MHz ensure adequate smallsignal settling full throughput rate. slower amps used, more settling time provided increasing time between conversions. best choice drive LTC1405 will depend application. Generally applications fall into categories: applications where dynamic specifications most critical time domain applications where accuracy settling time most critical. Input Filtering noise distortion input amplifier other circuitry must considered since they will LTC1405 noise distortion. small-signal bandwidth sample-and-hold circuit 100MHz. noise distortion products that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter sufficient many applications. example, Figure shows 1000pF capacitor from source resistor limit input bandwidth 5.3MHz. 1000pF capacitor also acts charge reservoir input sample-and-hold isolates amplifier driving from ADC's small current glitch. undersampling applications, input capacitor this large prohibitively limit input bandwidth. this case, large input capacitance possible. High quality capacitors resistors should used since these components distortion. silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors generate distortion from self-heating from damage that occur during soldering. Metal film surface mount resistors much less susceptible both problems.
1000pF +AIN LTC1405 -AIN
1405
Figure Input Filter
LTC1405
APPLICATIO ATIO
Digital Outputs Overflow (OF)
Figure shows ideal input/output characteristics LTC1405. output data two's complement binary input ranges both single dual supply operation. VREF/4.096. create straight binary output, invert (D11). overflow (OF) indicates when analog input outside input range converter. high when output code 1000 0000 0000 0111 1111 1111.
OVERFLOW 011.111 011.110 011.101
OUTPUT CODE
100.010 100.001 100.000 -(FS 1LSB) INPUT VOLTAGE
1405
1LSB
Figure LTC1405 Transfer Characteristics
Full-Scale Offset Adjustment applications where absolute accuracy important, offset full-scale errors adjusted zero. Offset error should adjusted before full-scale error. Figure shows method error adjustment dual supply, 4.096V application. zero offset error apply 0.5mV 0.5LSB) adjust until output code flickers between 0000 0000 0000 1111 1111 1111. full-scale adjustment, apply input voltage 2.0465V 1.5LSBs) adjust until output code flickers between 0111 1111 1110 0111 1111 1111. Digital Output Drivers LTC1405 output drivers interface logic operating from setting OVDD logic power supply. output desired, OVDD shorted share decoupling capacitor. Otherwise, OVDD requires decoupling capacitor. prevent digital
noise from affecting performance, load capacitance digital outputs should minimized. large capacitive loads required, (>30pF) external buffers resistors series with digital outputs suggested.
VREF SENSE
1405
+AIN LTC1405 -AIN
Figure Offset Full-Scale Adjust Circuit
Timing conversion start controlled rising edge pin. Once conversion started cannot stopped restarted until conversion cycle complete. Output data updated conversion, about 150ns after conversion begun. There additional cycle pipeline delay, data given conversion output full clock cycles plus 150ns after convert start. Thus output data latched third rising edge after rising edge that samples input. Clock Input LTC1405 only uses rising edge internal timing, doesn't necessarily need have duty cycle. optimal performance rise time should less than 5ns. available clock rise time slower than 5ns, locally sped with logic gate. With single supply operation clock driven with CMOS, CMOS logic levels. With dual power supplies clock should driven with CMOS levels. with fast ADCs, noise performance LTC1405 sensitive clock jitter when high speed inputs
LTC1405
APPLICATIO ATIO
20log tJ)dB
present. performance when performance limited jitter given where frequency input sine wave root-mean-square jitter clock, analog input aperture jitter. minimize clock jitter, clean clock source such crystal oscillator, treat clock signals sensitive analog traces dedicated packages with good supply bypassing clock drivers. Board Layout obtain best performance from LTC1405, printed circuit board with ground plane required. Layout printed circuit board should ensure that digital analog signal lines separated much possible. particular, care should taken digital track alongside analog signal track. analog ground plane separate from logic system ground should placed under around ADC. Pins (GND), (OGND) other analog grounds should connected this ground plane. single supply mode, (VSS) should also
1000pF ANALOG INPUT CIRCUITRY
+AIN -AIN VREF
ANALOG GROUND PLANE
1405
Figure Power Supply Grounding
PLACE NON-GROUND VIAS AWAY FROM GROUND PLANE BYPASS CAPACITORS
Figure Cross Section LTC1405 Printed Circuit Board
connected this ground plane. bypass capacitors LTC1405 should also connected this ground plane (Figure 12). digital system ground should connected analog ground plane only point, near OGND pin. analog ground plane should close possible. Care should taken avoid making holes analog ground plane under around part. accomplish this, recommend placing vias power signal traces outside area containing part decoupling capacitors (Figure 13). Supply Bypassing High quality, series resistance ceramic capacitors should used both pins, VREF. connected should also bypassed ground with 1µF. single supply operation should shorted ground plane close part possible. OVDD shorted (VDD) also requires decoupling capacitor ground. Surface mount capacitors such 0805ZC105KAT provide excellent bypassing small board space. traces connecting pins bypass capacitors must kept short should made wide possible.
LTC1405 OVDD OGND DIGITAL SYSTEM
LTC1405 BYPASS CAPACITOR ANALOG GROUND PLANE
1405
AVOID BREAKING GROUND PLANE THIS AREA
74ACT16373DL 470pF CLOCK
1405
0.1µF 0.1µF NC7S04M5 (J7) (SMB) 3201S-40G1 0.1µF
(MSB) AGND AVDD AGND VREF SENSE -AIN +AIN 0.1µF
OVDD
DVDD
DGND
APPLICATIO ATIO
AGND
GAIN
0.1µF
GAIN
MBR0520LT1
LTC1405
(J5) (SMB)
+AIN
(J6) (SMB)
-AIN
Figure LTC1405 Demo Board Schematic
LTC1405
OGND
OVDD
OGND
LTC1405
APPLICATIO ATIO
Figure Silkscreen Layer LTC1405/LTC1420 Demo Board
Figure Ground Plane Layer LTC1405/LTC1420 Demo Board
Figure Layer LTC1405/LTC1420 Demo Board
LTC1405
APPLICATIO ATIO
Figure Power Plane Layer LTC1405/LTC1420 Demo Board
Figure Bottom Layer LTC1405/LTC1420 Demo Board
LTC1405
TYPICAL APPLICATIO
Single Supply, 5Msps, 12-Bit with Logic Outputs
LTC1405 ANALOG INPUT (2.5V 1.024V) 1000pF +AIN -AIN SENSE VREF GAIN OVDD OGND 12-BIT PARALLEL DATA PLUS OVERFLOW 5MHz CLOCK
1405 TA03
Dual Supply, 5Msps, 12-Bit with 71.3dB SINAD
LTC1405 ANALOG INPUT (±2.048V) 1000pF, +AIN -AIN SENSE VREF GAIN OVDD OGND 12-BIT PARALLEL DATA PLUS OVERFLOW 5MHz CLOCK
1405 TA04
LTC1405
PACKAGE DESCRIPTIO
Dimensions inches (millimeters) unless otherwise specified. Package 28-Lead Plastic SSOP (Narrow 0.150)
(LTC 05-08-1641)
0.386 0.393* (9.804 9.982) 1615
0.033 (0.838)
0.229 0.244 (5.817 6.198)
0.150 0.157** (3.810 3.988)
0.015 0.004 (0.38 0.10) 0.0075 0.0098 (0.191 0.249) 0.016 0.050 (0.406 1.270) DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE 0.053 0.069 (1.351 1.748)
0.004 0.009 (0.102 0.249)
0.008 0.012 (0.203 0.305)
0.0250 (0.635)
GN28 (SSOP) 1098
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LTC1405
TYPICAL APPLICATIO
1.4MHz BOOST REGULATOR 4.7µH 3.3V 0.1µF 15µF SHDN LT1613 SHDN
100k 15µF
RELATED PARTS
PART NUMBER LTC1420 LTC1412 LTC1402 LTC1415 LTC1668 LT1019 DESCRIPTION 12-Bit, 10Msps, Sampling 12-Bit, 3Msps, Sampling with Parallel Output Serial 12-Bit, Msps Single 12-Bit, 1.25Msps with Parallel Output 16-Bit 50Msps Precision Bandgap Reference COMMENTS Compatible with LTC1405 Best Dynamic Performance, SINAD 72dB Nyquist 16-Pin Narrow SSOP Package, 72dB SINAD 55mW Power Dissipation, 72dB SINAD 87dB SFDR, 1.5LSB DNL, Power 0.05% Initial Accuracy, 5ppm/°C Drift
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
(408)432-1900 FAX: (408) 434-0507 www.linear-tech.com
Single 3.3V Supply, 5Msps, 12-Bit
LTC1405 ANALOG INPUT (2.048VP-P)
1000pF,
+AIN -AIN SENSE VREF
GAIN OVDD OGND
3.3V 12-BIT DATA 3.3V OVERFLOW 5MHz CLOCK
0.1µF
32.4k
1405 TA05
1405f LT/TP 0101 PRINTED
LINEAR TECHNOLOGY CORPORATION 2000
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