3.3V CMOS 12-BIT IDT74ALVCHR162269A 24-BIT REGISTERED EXCHANGER WITH 3

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3.3V CMOS 12-BIT IDT74ALVCHR162269A 24-BIT REGISTERED EXCHANGER WITH 3

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IDT74ALVCHR162269A 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
3.3V CMOS 12-BIT IDT74ALVCHR162269A 24-BIT REGISTERED EXCHANGER WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP, 0.40mm pitch TVSOP packages Extended commercial range 40°C 85°C 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin
DESCRIPTION:
This 12-bit 24-bit registered exchanger used applications which separate ports must multiplexed onto, demultiplexed from, single port. particularly suitable interface between synchronous DRAMs high-speed microprocessors. Data stored internal B-port registers low-to-high transition clock (CLK) input when appropriate clock-enable (CLKENA) inputs low. Proper control these inputs allows sequential 12-bit words presented 24-bit word B-port. data transfer B-to-A direction, single storage register provided. select line selects data outputs. register output permits fastest possible data transfer, thus extending period during which data valid bus. control terminals registered that transactions synchronous with CLK. Data flow controlled active-low output enables (OEA, OEB1 OEB2). ALVCHR162269A series resistors device output structure which will significantly reduce line noise when used with light loads. This driver been designed drive ±12mA designated threshold levels. ALVCHR162269A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
Drive Features ALVCHR162269A: Balanced Output Drivers: ±12mA switching noise
APPLICATIONS:
3.3V High Speed Systems 3.3V lower voltage computing systems
Functional Block Diagram
CLKENA
CLKENA
Channels
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4239/-
IDT74ALVCHR162269A 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
CONFIGURATION
ABSOLUTE MAXIMUM RATING
CLKENA
Unit
NEW16link
Symbol VTERM(2) VTERM(3) TSTG IOUT
Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each
Max. ±100
SO56-1 SO56-2 SO56-3
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25oC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NEW16link
NOTE: applicable device type.
CLKENA
SSOP/ TSSOP/TVSOP VIEW
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74ALVCHR162269A 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
DESCRIPTION
Names Ax(1:12)
1Bx(1:12) 2Bx(1:12)
Description Bidirectional Data Port Usually connected CPU's Address/Data bus.(1) Bidirectional Data Port Usually connected even path even bank memory. Bidirectional Data Port Usually connected path bank memory. Clock Input Clock Enable Input A-1B register. CLKENA1 during rising edge CLK, data will clocked into register A-1B (Active LOW). Clock Enable Input A-2B register. CLKENA2 during rising edge CLK, data will clocked into register A-2B (Active LOW). Port Selection. When HIGH during rising edge CLK, enables data transfer from port port. When during rising edge CLK, enables data transfer from port port. Synchronous Output Enable port (Active LOW) Synchronous Output Enable port (Active LOW) Synchronous Output Enable port (Active LOW)
CLKENA1 CLKENA2 OEB1 OEB2
NOTE: These pins have "Bus-Hold." other pins standard inputs, outputs, I/Os.
FUNCTION TABLES(1) OUTPUT ENABLE
Inputs OEBx Active Active Outputs
1Bx,
A-TO-B STORAGE (OEB
Inputs Outputs
1B0(2) 2B0(2)
Active Active
CLKENA1
CLKENA2
B-TO-A STORAGE (OEA
Inputs
Outputs A0(2) A0(2)
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition Output level before indicated steady-state input conditions were established.
IDT74ALVCHR162269A 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: 40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation 2.3V, 18mA 3.3V 3.6V input 0.6V, other inputs Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Min. Typ.(1) Max. Unit
NEW16link
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NEW16link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74ALVCHR162269A 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 2.7V 3.0V Output Voltage 2.3V 3.6V 2.3V 2.7V 3.0V 12mA 0.1mA 12mA Min. Max. 0.55 0.55
NEW16link
Unit
2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25oC
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
IDT74ALVCHR162269A 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
SWITCHING CHARACTERISTICS
2.5V 0.2V Symbol fCLOCK tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSK(o) Clock Frequency Propagation Delay Propagation Delay Output Enable Time Output Enable Time Output Disable Time Output Disable Time Set-Up Time, data before Set-Up Time, data before Set-Up Time, before Set-Up Time, CLKENA1 CLKENA2 before Set-Up Time, OEBx before Hold Time, data after Hold Time, data after Hold Time, after Hold Time, CLKENA1 CLKENA2 after Hold Time, OEBx after Pulse Width, HIGH Output Skew(2) Parameter Min. Max. 2.7V Min. Max. 3.3V 0.15V Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCHR162269A 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
NEW16link
PHAS INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
ALVC Link
TEST CIRCUITS OUTPUTS
Pulse Generator
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT ITCH NORM ALLY CLOSE tPZH OUTPUT ITCH NORM ALLY OPEN HIGH LOAD tPLZ DISABLE LOAD
LOAD Open
D.U.T.
ALVC Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
ALVC Link NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
NEW16link
Open
OUTPUT SKEW INPUT
tPLH1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT tPLH2
PLH2
Link
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCHR162269A 3.3V CMOS 12-BIT 24-BIT REGISTERED EXCHANGER
ORDERING INFORMATION
ALVC Bus-Hold Family Device Type Package Temp. Range
269A R162
Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 12-Bit 24-Bit Registered Exchanger with 3-State Outputs Double-Density with Resistors, ±12mA Bus-hold 40°C +85°C
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3.3V CMOS 12-BIT IDT74ALVCHR162269A 24-BIT REGISTERED EXCHANGER WITH 3

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