Data Sheet July 2005 FN957.10 4.5MHz, BiMOS Operational Amplifier
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CA3140, CA3140A
Data Sheet July 2005 FN957.10
4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output
CA3140A CA3140 integrated circuit operational amplifiers that combine advantages high voltage PMOS transistors with high voltage bipolar transistors single monolithic chip. CA3140A CA3140 BiMOS operational amplifiers feature gate protected MOSFET (PMOS) transistors input circuit provide very high input impedance, very input current, high speed performance. CA3140A CA3140 operate supply voltage from (either single dual supply). These operational amplifiers internally phase compensated achieve stable operation unity gain follower operation, additionally, have access terminal supplementary external capacitor additional frequency roll-off desired. Terminals also provided applications requiring input offset voltage nulling. PMOS field effect transistors input stage results common mode input voltage capability down 0.5V below negative supply terminal, important attribute single supply applications. output stage uses bipolar transistors includes built-in protection against damage from load terminal short circuiting either supply rail ground. CA3140A CA3140 intended operation supply voltages (±18V).
Features
MOSFET Input Stage Very High Input Impedance (ZIN) -1.5T (Typ) Very Input Current (Il) -10pA (Typ) ±15V Wide Common Mode Input Voltage Range (VlCR) Swung 0.5V Below Negative Supply Voltage Rail Output Swing Complements Input Common Mode Range Directly Replaces Industry Type Most Applications Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Ground-Referenced Single Supply Amplifiers Automobile Portable Instrumentation Sample Hold Amplifiers Long Duration Timers/Multivibrators (µseconds-Minutes-Hours) Photocurrent Instrumentation Peak Detectors Active Filters Comparators Interface Systems Other Supply Voltage Systems Standard Operational Amplifier Applications Function Generators Tone Controls Power Supplies Portable Instruments Intrusion Alarm Systems
Pinout
CA3140 (PDIP, SOIC) VIEW
OFFSET NULL INV. INPUT NON-INV. INPUT STROBE OUTPUT OFFSET NULL
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Harris Corporation 1998, Copyright Intersil Americas Inc. 2002, 2004, 2005. Rights Reserved other trademarks mentioned property their respective owners.
CA3140, CA3140A
Ordering Information
PART NUMBER (BRAND) CA3140AE CA3140AEZ* (See Note) CA3140AM (3140A) CA3140AM96 (3140A) CA3140AMZ (3140A) (See Note) CA3140AMZ96 (3140A) (See Note) CA3140E CA3140EZ* (See Note) CA3140M (3140) CA3140M96 (3140) CA3140MZ (3140) (See Note) CA3140MZ96 (3140) (See Note) TEMP. RANGE (°C) PACKAGE PDIP PDIP (Pb-free) SOIC PKG. DWG. E8.3 E8.3 M8.15
SOIC Tape Reel SOIC (Pb-free) M8.15
SOIC Tape Reel (Pb-free) PDIP PDIP (Pb-free) SOIC E8.3 E8.3 M8.15
SOIC Tape Reel SOIC (Pb-free) M8.15
SOIC Tape Reel (Pb-free)
*Pb-free PDIPs used through hole wave solder processing only. They intended Reflow solder processing applications. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD020.
FN957.10 July 2005
CA3140, CA3140A
Absolute Maximum Ratings
Supply Voltage (Between Terminals) Differential Mode Input Voltage Input Voltage +8V) -0.5V) Input Terminal Current Output Short Circuit Duration (Note Indefinite Operating Conditions Temperature Range -55oC 125oC
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) PDIP Package*. SOIC Package Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only) *Pb-free PDIPs used through hole wave solder processing only. They intended Reflow solder processing applications.
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: measured with component mounted effective thermal conductivity test board free air. Tech Brief TB379 details Short circuit applied ground either supply.
Electrical Specifications
VSUPPLY ±15V, 25oC TYPICAL VALUES
PARAMETER Input Offset Voltage Adjustment Resistor
SYMBOL
TEST CONDITIONS Typical Value Resistor Between Terminals Adjust
CA3140
CA3140A
UNITS
Input Resistance Input Capacitance Output Resistance Equivalent Wideband Input Noise Voltage (See Figure Equivalent Input Noise Voltage (See Figure
140kHz, 1kHz 10kHz
0.08
nV/Hz nV/Hz V/µs
Short Circuit Current Opposite Supply
IOM+ IOM-
Source Sink
Gain-Bandwidth Product, (See Figures Slew Rate, (See Figure Sink Current From Terminal Terminal Swing Output Transient Response (See Figure
100pF 100pF Voltage Follower
Rise Time Overshoot 10mV
0.08
Settling Time 10VP-P, (See Figure
Electrical Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Current
Equipment Design, VSUPPLY ±15V, 25oC, Unless Otherwise Specified CA3140 SYMBOL |VIO| |IIO| CA3140A UNITS
FN957.10 July 2005
CA3140, CA3140A
Electrical Specifications
PARAMETER Large Signal Voltage Gain (Note (See Figures Common Mode Rejection Ratio (See Figure Common Mode Input Voltage Range (See Figure Power-Supply Rejection Ratio, VIO/VS (See Figure Output Voltage (Note (See Figures Supply Current (See Figure Device Dissipation Input Offset Voltage Temperature Drift NOTES: 26VP-P +12V, -14V Equipment Design, VSUPPLY ±15V, 25oC, Unless Otherwise Specified (Continued) CA3140 SYMBOL CMRR VICR PSRR VOM+ VOMI+ VIO/T -15.5 +12.5 -14.4 CA3140A -15.5 +12.5 -14.4 UNITS kV/V µV/V µV/V µV/oC
Electrical Specifications
Design Guidance 25oC TYPICAL VALUES
PARAMETER Input Offset Voltage Input Offset Current Input Current Input Resistance Large Signal Voltage Gain (See Figures
SYMBOL |VIO| |IIO|
CA3140
CA3140A -0.5 0.13
UNITS kV/V µV/V µV/V V/µs
Common Mode Rejection Ratio
CMRR
Common Mode Input Voltage Range (See Figure
VICR
-0.5
Power Supply Rejection Ratio
PSRR VIO/VS VOM+ VOM-
0.13
Maximum Output Voltage (See Figures
Maximum Output Current:
Source Sink
IOM+
Slew Rate (See Figure Gain-Bandwidth Product (See Figure Supply Current (See Figure Device Dissipation Sink Current from Terminal Terminal Swing Output
FN957.10 July 2005
CA3140, CA3140A Block Diagram
BIAS CIRCUIT CURRENT SOURCES REGULATOR INPUT 200µA 1.6mA 200µA 10,000 12pF STROBE
OUTPUT
OFFSET NULL
Schematic Diagram
BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK
OUTPUT INVERTING INPUT NON-INVERTING INPUT
12pF
OFFSET NULL
STROBE
NOTE:
resistance values ohms.
FN957.10 July 2005
CA3140, CA3140A Application Information
Circuit Description
shown block diagram, input terminals operated down 0.5V below negative supply rail. class amplifier stages provide voltage gain, unique class amplifier stage provides current gain necessary drive low-impedance loads. biasing circuit provides control cascoded constant current flow circuits first second stages. CA3140 includes chip phase compensating capacitor that sufficient unity gain voltage follower configuration. When CA3140 operating such that output Terminal sinking current bus, transistor current sinking element. Transistor mirror connected with current Q21, R12, Q20. Transistor Q20, turn, biased current flow through R13, zener R14. dynamic current sink controlled voltage level sensing. purposes explanation, assumed that output Terminal quiescently established potential midpoint between supply rails. When output current sinking mode operation required, collector potential transistor driven below quiescent level, thereby causing Q17, decrease output voltage Terminal Thus, gate terminal PMOS transistor displaced toward bus, thereby reducing channel resistance Q21. consequence, there incremental increase current flow through Q20, R12, Q21, base Q16. result, sinks current from Terminal direct response incremental change output voltage caused Q18. This sink current flows regardless load; excess current internally supplied emitter-follower Q18. Short circuit protection output circuit provided Q19, which driven into conduction high voltage drop developed across under output short circuit conditions. Under these conditions, collector diverts current from reduce base current drive from Q17, thereby limiting current flow short circuited load terminal.
Input Stage
schematic diagram consists differential input stage using PMOS field-effect transistors (Q9, Q10) working into mirror pair bipolar transistors (Q11, Q12) functioning load resistors together with resistors through mirror pair transistors also function differential-to-single-ended converter provide base current drive second stage bipolar transistor (Q13). Offset nulling, when desired, effected with potentiometer connected across Terminals with slider connected Terminal Cascode-connected bipolar transistors constant current source input stage. base biasing circuit constant current source described subsequently. small diodes provide gate oxide protection against high voltage transients, e.g., static electricity.
Bias Circuit
Quiescent current stages (except dynamic current sink) CA3140 dependent upon bias current flow function bias circuit establish maintain constant current flow through diode connected transistor mirror connected parallel with base emitter junctions considered current sampling diode that senses emitter current automatically adjusts base current (via maintain constant current through base currents also determined constant current flow Furthermore, current diode connected transistor establishes currents transistors Q15.
Second Stage
Most voltage gain CA3140 provided second amplifier stage, consisting bipolar transistor cascode connected load resistance provided bipolar transistors On-chip phase compensation, sufficient majority applications provided Additional Miller-Effect compensation (roll off) accomplished, when desired, simply connecting small capacitor between Terminals Terminal also used strobe output stage into quiescence. When terminal tied negative supply rail (Terminal mechanical electrical means, output Terminal swings low, i.e., approximately Terminal potential.
Typical Applications
Wide dynamic range input output characteristics with most desirable high input impedance characteristics achieved CA3140 unique design based upon PMOS Bipolar process. Input common mode voltage range output swing capabilities complementary, allowing operation with single supply down wide dynamic range these parameters also means that this device suitable many single supply applications, such example, where input driven below potential Terminal phase sense output signal must maintained most important consideration comparator applications.
Output Stage
CA3140 Series circuits employ broad band output stage that sink loads negative supply complement capability PMOS input stage when operating near negative rail. Quiescent current emitter-follower cascade circuit (Q17, Q18) established transistors (Q14, Q15) whose base currents "mirrored" current flowing through diode bias circuit section. When CA3140 operating such that output Terminal sourcing current, transistor functions emitter-follower source current from (Terminal R11. Under these conditions, collector potential sufficiently high permit necessary flow base current emitter follower which, turn, drives Q18.
FN957.10 July 2005
CA3140, CA3140A
Output Circuit Considerations
Excellent interfacing with circuitry easily achieved with single 6.2V zener diode connected Terminal shown Figure This connection assures that maximum output signal swing will more positive than zener voltage minus base-to-emitter voltage drops within CA3140. These voltages independent operating supply voltage.
CA3140 6.2V LOGIC SUPPLY TYPICAL GATE
level shifting circuitry usually associated with series operational amplifiers. Figure shows some typical configurations. Note that series resistor, used both cases limit drive available driven device. Moreover, recommended that series diode shunt diode used thyristor input prevent large negative transient surges that appear gate thyristors, from damaging integrated circuit.
Offset Voltage Nulling
input offset voltage nulled connecting potentiometer between Terminals returning wiper terminal Figure This technique, however, gives more adjustment range than required therefore, considerable portion potentiometer rotation fully utilized. Typical values series resistors that placed either potentiometer, Figure optimize utilization range given Electrical Specifications table. alternate system shown Figure This circuit uses only additional resistor approximately value shown table. potentiometers, which resistance does drop either rotation, value resistance lower than values shown table should used.
FIGURE ZENER CLAMPING DIODE CONNECTED TERMINALS LIMIT CA3140 OUTPUT SWING LEVELS
OUTPUT STAGE TRANSISTOR (Q15, Q16) SATURATION VOLTAGE (mV) 1000 SUPPLY VOLTAGE (V-) 25oC
SUPPLY VOLTAGE (V+)
+15V +30V
Voltage Operation
Operation total supply voltages possible with CA3140. current regulator based upon PMOS threshold voltage maintains reasonable constant operating current hence consistent performance down these lower voltages.
0.01
LOAD (SINKING) CURRENT (mA)
FIGURE VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15 Q16) LOAD CURRENT
Figure shows output current sinking capabilities CA3140 various supply voltages. Output voltage swing negative supply rail permits this device operate both power transistors thyristors directly without need
CA3140 CA3140
voltage limitation occurs when upper extreme input common mode voltage range extends down voltage Terminal This limit reached total supply voltage just below output voltage range also begins extend down negative supply rail, slightly higher than that input. Figure shows these characteristics shows that with dual supplies, lower extreme input common mode voltage range below ground potential.
CA3140
FIGURE BASIC
FIGURE IMPROVED RESOLUTION
FIGURE SIMPLER IMPROVED RESOLUTION
FIGURE THREE OFFSET VOLTAGE NULLING METHODS
FN957.10 July 2005
CA3140, CA3140A
LOAD LOAD 120VAC CA3140
LOAD
CA3140
FIGURE METHODS UTILIZING VCE(SAT) SINKING CURRENT CAPABILITY CA3140 SERIES
FOLLOWER +15V CA3140 LOAD RESISTANCE (RL) LOAD CAPACITANCE (CL) 100pF SUPPLY VOLTAGE: ±15V 25oC INPUT VOLTAGE 10mV 10mV 1N914 1N914 4.99k -15V SETTLING POINT FOLLOWER INVERTING 0.1µF 5.11k CA3140 100pF 10mV 10mV 0.1µF -15V 100pF 0.1µF SIMULATED LOAD
0.05µF INVERTING +15V 0.1µF SIMULATED LOAD
SETTLING TIME (µs)
FIGURE WAVEFORM
FIGURE TEST CIRCUITS FIGURE SETTLING TIME INPUT VOLTAGE
Bandwidth Slew Rate
those cases where bandwidth reduction desired, example, broadband noise reduction, external capacitor connected between Terminals reduce open loop -3dB bandwidth. slew rate will, however, also proportionally reduced using this additional capacitor. Thus, reduction bandwidth this technique will also reduce slew rate about 20%. Figure shows typical settling time required reach 10mV final value various levels large signal inputs voltage follower inverting unity gain amplifiers.
exceptionally fast settling time characteristics largely high combination high gain wide bandwidth CA3140; shown Figure
Input Circuit Considerations
mentioned previously, amplifier inputs driven below Terminal potential, series current limiting resistor recommended limit maximum input terminal current less than prevent damage input protection circuitry. Moreover, some current limiting resistance should provided between inverting input output when
FN957.10 July 2005
CA3140, CA3140A
CA3140 used unity gain voltage follower. This resistance prevents possibility extremely large input signal transients from forcing signal through input protection network directly driving internal constant current source which could result positive feedback output terminal. 3.9k resistor sufficient. typical input current order 10pA when inputs centered nominal device dissipation. output supplies load current, device dissipation will increase, raising chip temperature resulting increased input current. Figure shows typical input terminal current versus ambient temperature CA3140. well known that MOSFET devices exhibit slight changes characteristics (for example, small changes
OPEN LOOP PHASE (DEGREES)
input offset voltage) application large differential input voltages that sustained over long periods elevated temperatures. Both applied voltage temperature accelerate these changes. process reversible offset voltage shifts opposite polarity reverse offset. Figure shows typical offset voltage change function various stress voltages maximum rating 125oC (for metal can); lower temperatures (metal plastic), example, 85oC, this change voltage considerably less. typical linear applications, where differential voltage small symmetrical, these incremental changes about same magnitude those encountered operational amplifier employing bipolar transistor input stage.
OPEN LOOP VOLTAGE GAIN (dB)
SUPPLY VOLTAGE: ±15V 25oC 100pF
-105 -120 -135 -150
SUPPLY VOLTAGE: ±15V
INPUT CURRENT (pA)
FREQUENCY (Hz)
TEMPERATURE (oC)
FIGURE OPEN LOOP VOLTAGE GAIN PHASE FREQUENCY
FIGURE INPUT CURRENT TEMPERATURE
INPUT OUTPUT VOLTAGE EXCURSIONS FROM TERMINAL (V+)
-0.5 -1.0 -1.5 -2.0 -2.5 -3.0 +VICR 125oC +VICR 25oC +VICR -55oC +VOUT 125oC +VOUT 25oC +VOUT -55oC
INPUT OUTPUT VOLTAGE EXCURSIONS FROM TERMINAL (V-)
-0.5 -1.0 -1.5 -VOUT -55oC 125oC -VICR 125oC -VICR 25oC -VICR -55oC
SUPPLY VOLTAGE (V+,
SUPPLY VOLTAGE (V+,
FIGURE OUTPUT VOLTAGE SWING CAPABILITY COMMON MODE INPUT VOLTAGE RANGE SUPPLY VOLTAGE
FN957.10 July 2005
CA3140, CA3140A
OFFSET VOLTAGE SHIFT (mV) 1000 1500 2000 2500 3000 3500 4000 4500 TIME (HOURS) DIFFERENTIAL VOLTAGE (ACROSS TERMINALS OUTPUT VOLTAGE 125oC METAL PACKAGES DIFFERENTIAL VOLTAGE (ACROSS TERMINALS OUTPUT STAGE TOGGLED
placed across input CA3080A give logarithmic analog indication function generator's frequency. Analog frequency readout readily accomplished means described above because output current CA3080A varies approximately decade each 60mV change applied voltage, VABC (voltage between Terminals CA3080A function generator). Therefore, decades represent 360mV change VABC Now, only reference voltage must established lower limit meter. three remaining transistors from CA3086 Array used sweep generator used this reference voltage. addition, this reference generator arrangement tends track ambient temperature variations, thus compensates effects normal negative temperature coefficient CA3080A VABC terminal voltage. Another output voltage from reference generator used insure temperature tracking lower Frequency Adjustment Potentiometer. large series resistance simulates current source, assuring similar temperature coefficients both ends Frequency Adjustment Control. calibrate this circuit, Frequency Adjustment Potentiometer end. Then adjust Minimum Frequency Calibration Control lowest frequency. establish upper frequency limit, Frequency Adjustment Potentiometer upper then adjust Maximum Frequency Calibration Control maximum frequency. Because there interaction among these controls, repetition adjustment procedure necessary. adjustments used meter. meter sensitivity control sets meter scale width each decade, while meter position control adjusts pointer scale with negligible effect sensitivity adjustment. Thus, meter sensitivity adjustment control calibrates meter that deflects full scale each decade change frequency.
FIGURE TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT OPERATING LIFE
Super Sweep Function Generator
function generator having wide tuning range shown Figure 1,000,000/1 adjustment range accomplished single variable potentiometer auxiliary sweeping signal. CA3140 functions noninverting readout amplifier triangular signal developed across integrating capacitor network connected output CA3080A current source. Buffered triangular output signals then applied second CA3080 functioning high speed hysteresis switch. Output from switch returned directly back input CA3080A current source, thereby, completing positive feedback loop triangular output level determined four 1N914 level limiting diodes second CA3080 resistor divider network connected Terminal (input) CA3080. These diodes establish input trip level this switching stage and, therefore, indirectly determine amplitude output triangle. Compensation propagation delays around entire loop provided adjustment input CA3080. This adjustment, which provides constant generator amplitude output, most easily made while generator sweeping. High frequency ramp linearity adjusted single 60pF capacitor output CA3080A. must emphasized that only CA3080A characterized maximum output linearity current generator function.
Sine Wave Shaper
circuit shown Figure uses CA3140 voltage follower combination with diodes from CA3019 Array convert triangular signal from function generator sine-wave output signal having typically less than THD. basic zero crossing slope established potentiometer connected between Terminals CA3140 9.1k resistor potentiometer from Terminal ground. break points established diodes through Positive feedback establishes zero slope maximum minimum levels sine wave. This technique necessary because voltage follower configuration approaches unity gain rather than zero gain required shape sine wave extremes.
Meter Driver Buffer Amplifier
Figure shows CA3140 connected meter driver buffer amplifier. driving impedance required CA3080A current source assure smooth operation Frequency Adjustment Control. This low-driving impedance requirement easily using CA3140 connected voltage follower. Moreover, meter
FN957.10 July 2005
CA3140, CA3140A
CENTERING -15V EXTERNAL OUTPUT
+15V
7.5k SYMMETRY -15V +15V 100k FROM BUFFER METER DRIVER (OPTIONAL) -15V
+15V 7-60 HIGH FREQ. SHAPE -15V
+15V
CA3140
HIGH FREQUENCY LEVEL 910k 7-60pF
EXTERNAL OUTPUT 2.7k -15V OUTPUT AMPLIFIER
CA3080A
-15V
CA3080
+15V
FREQUENCY ADJUSTMENT
5.1k
SINE WAVE SHAPER
THIS NETWORK USED WHEN OPTIONAL BUFFER CIRCUIT USED
OUTPUT AMPLIFIER
1N914
FIGURE 10A. CIRCUIT
FREQUENCY ADJUSTMENT
Trace: Output junction resistors; 5V/Div., 500ms/Div. Center Trace: External output triangular function generator; 2V/Div., 500ms/Div. Bottom Trace: Output "Log" generator; 10V/Div., 500ms/Div. FIGURE 10B. FIGURE FUNCTION GENERATOR SWEEPING
METER DRIVER BUFFER AMPLIFIER FUNCTION GENERATOR WIDEBAND LINE DRIVER +15V POWER SUPPLY ±15V -15V
SINE WAVE SHAPER
GATE LEVEL SWEEP ADJUST INT. COARSE RATE VEXT. EXTERNAL INPUT
FINE RATE
SWEEP GENERATOR
1V/Div., 1s/Div. Three tone test signals, highest frequency 0.5MHz. Note slight asymmetry three second/cycle signal. This asymmetry slightly different positive negative integration from CA3080A from board component leakages 100pA level. FIGURE 10C. FUNCTION GENERATOR WITH FIXED FREQUENCIES
SWEEP LENGTH
FIGURE 10D. INTERCONNECTIONS
FIGURE FUNCTION GENERATOR
FN957.10 July 2005
CA3140, CA3140A
FREQUENCY CALIBRATION MAXIMUM 620k CA3140 4.7k +15V 0.1µF FREQUENCY 2.4k CALIBRATION MINIMUM METER POSITION ADJUSTMENT 3.6k
500k FREQUENCY ADJUSTMENT SWEEP
CA3080A FUNCTION CA3080A GENERATOR (FIGURE METER SENSITIVITY ADJUSTMENT 200µA METER
+15V
-15V 0.1µF
5.1k
5.6k 7.5k SUBSTRATE CA3019 WIDEBAND OUTPUT AMPLIFIER EXTERNAL OUTPUT
CA3140
0.1µF +15V -15V 9.1k
-15V
CA3086
-15V
CA3019 DIODE ARRAY
FIGURE METER DRIVER BUFFER AMPLIFIER
FIGURE SINE WAVE SHAPER
750k "LOG" SAWTOOTH 1N914 SAWTOOTH SYMMETRY 100k 100k FINE RATE 8.2k
1N914 0.47µF 0.047µF 4700pF 470pF
+15V SAWTOOTH RAMP LEVEL (-14.5V)
COARSE RATE
+15V
SAWTOOTH "LOG"+15V TRIANGLE RATE ADJUST -15V 100k OUTPUT AMPLIFIER
+15V
CA3140
GATE PULSE OUTPUT
CA3140
-15V
-15V
EXTERNAL OUTPUT
FUNCTION GENERATOR "SWEEP SWEEP WIDTH +15V
LOGVIO
CA3140
6.8k
-15V
TRIANGLE
TRANSISTORS FROM CA3086 ARRAY
SAWTOOTH "LOG"
FIGURE SWEEPING GENERATOR
FN957.10 July 2005
CA3140, CA3140A
This circuit adjusted most easily with distortion analyzer, good first approximation made comparing output signal with that sine wave generator. initial slope adjusted with potentiometer followed adjustment final slope established adjusting thereby adding additional segments that contributed these diodes. Because there some interaction among these controls, repetition adjustment procedure necessary. Sweeping Generator Figure shows sweeping generator. Three CA3140s used this circuit. CA3140 used integrator, second device used hysteresis switch that determines starting stopping points sweep. third CA3140 used logarithmic shaping network function. Rates slopes, well sawtooth, triangle, logarithmic sweeps generated this circuit. Wideband Output Amplifier Figure shows high slew rate, wideband amplifier suitable transmission line driver. This circuit, when used conjunction with function generator sine wave shaper circuits shown Figures provides 18VP-P output open circuited, 9VP-P output when terminated slew rate required this amplifier 28V/µs (18VP-P 0.5MHz).
+15V SIGNAL LEVEL ADJUSTMENT 2.5k
REFERENCE VOLTAGE INPUT
VOLTAGE ADJUSTMENT
REGULATED OUTPUT
CA3140
FIGURE BASIC SINGLE SUPPLY VOLTAGE REGULATOR SHOWING VOLTAGE FOLLOWER CONFIGURATION
Essentially, regulators, shown Figures connected inverting power operational amplifiers with gain 3.2. reference input yields maximum output voltage slightly greater than 25V. voltage follower, when reference input goes output will Because offset voltage also multiplied gain factor, potentiometer needed null offset voltage. Series pass transistors with high ICBO levels will also prevent output voltage from reaching zero because there finite voltage drop (VCESAT) across output CA3140 (see Figure This saturation voltage level indeed lowest voltage obtainable. high impedance presented Terminal advantageous effecting current limiting. Thus, only small signal transistor required current-limit sensing amplifier. Resistive decoupling provided this transistor minimize damage CA3140 event unusual input output transients supply rail. Figures show circuits which D2201 high speed diode used current sensor. This diode chosen slightly higher forward voltage drop characteristic, thus giving greater sensitivity. must emphasized that heat sinking this diode essential minimize variation current trip point internal heating diode. That forward drop represents watt which result significant regenerative changes current trip point diode temperature rises. Placing small signal reference amplifier proximity current sensing diode also helps minimize variability trip level negative temperature coefficient diode. spite those limitations, current limiting point easily adjusted over range from 10mA with single adjustment potentiometer. temperature stability current limiting system serious consideration, more usual current sampling resistor type circuitry should employed. power Darlington transistor metal with heatsink), used series pass element conventional current limiting system, Figure because high power Darlington dissipation will encountered output voltage high currents.
50µF
2N3053
CA3140
1N914 1N914
OUTPUT LEVEL ADJUSTMENT
50µF
+15V -15V
2.4pF
2N4037 -15V
1.8k
NOMINAL BANDWIDTH 10MHz 35ns
FIGURE WIDEBAND OUTPUT AMPLIFIER
Power Supplies High input impedance, common mode capability down negative supply high output drive current capability factors design wide range output voltage supplies that single input voltage provide regulated output voltage that adjusted from essentially 24V. Unlike many regulator systems using comparators having bipolar transistor input stage, high impedance reference voltage divider from single supply used connection with CA3140 (see Figure 15).
FN957.10 July 2005
CA3140, CA3140A
small heat sink VERSAWATT transistor used series pass element fold back current system, Figure since dissipation levels will only approach 10W. this system, D2201 diode used current sampling. Foldback provided 100k divider network connected base current sensing transistor. Both regulators provide better than 0.02% load regulation. Because there constant loop gain voltage settings,
2N6385 CURRENT POWER DARLINGTON LIMITING ADJUST D2201 2.7k 10µF INPUT 2.2k 0.01µF CA3086 NOISE OUTPUT <200µVRMS (MEASUREMENT BANDWIDTH ~10MHz) LINE REGULATION 0.1%/V LOAD REGULATION LOAD FULL LOAD) <0.02% NOISE OUTPUT <200µVRMS (MEASUREMENT BANDWIDTH ~10MHz) LINE REGULATION 0.1%/V LOAD REGULATION LOAD FULL LOAD) <0.02% CA3086 CA3140 100k VOLTAGE ADJUST 100k INPUT 2.2k 0.01µF 2.7k 10µF 56pF 180k CA3140 100k VOLTAGE ADJUST 100k 2N2102
regulation also remains constant. Line regulation 0.1% volt. noise voltage less than 200µV read with meter having 10MHz bandwidth. Figure shows turn turn characteristics both regulators. slow turn rise slow rate rise reference voltage. Figure shows transient response regulator with switching load output.
"FOLDBACK" CURRENT LIMITER 2N5294 D2201 OUTPUT "FOLDS BACK" 40mA
+30V
OUTPUT
+30V
100k
100k
2N2102 56pF 180k
250µF
250µF
FIGURE REGULATED POWER SUPPLY
FIGURE REGULATED POWER SUPPLY WITH "FOLDBACK" CURRENT LIMITING
5V/Div., 1s/Div.
Trace: Output Voltage; 200mV/Div., 5µs/Div. Bottom Trace: Collector load switching transistor, load 5V/Div., 5µs/Div. FIGURE 18B. TRANSIENT RESPONSE
FIGURE 18A. SUPPLY TURN-ON TURNOFF CHARACTERISTICS
FIGURE WAVEFORMS DYNAMIC CHARACTERISTICS POWER SUPPLY CURRENTS SHOWN FIGURES
FN957.10 July 2005
CA3140, CA3140A
Tone Control Circuits
High slew rate, wide bandwidth, high output voltage capability high input impedance characteristics required tone control amplifiers. tone control circuits that exploit these characteristics CA3140 shown Figures first circuit, shown Figure Baxandall tone control circuit which provides unity gain midband uses standard linear potentiometers. high input impedance CA3140 makes possible lowcost, low-value, small size capacitors, well reduced load driving stage. Bass treble boost ±15dB 100Hz 10kHz, respectively. Full peak-to-peak output available least 20kHz high slew rate CA3140. amplifier gain down from "flat" position 70kHz. Figure shows another tone control circuit with similar boost specifications. wideband gain this circuit equal ultimate boost plus one, which this case gain eleven. 20dB boost cut, input loading this circuit essentially equal value resistance from Terminal ground. detailed analysis this circuit given Operational Transconductance Amplifier (OTA) With Power Capability" Kaplan Wittlinger, IEEE Transactions Broadcast Television Receivers, Vol. BTR-18, August, 1972.
NOTES: 20dB Flat Position Gain.
CA3140 0.1µF
SINGLE SUPPLY +30V 2.2M 0.005µF
±15dB Bass Treble Boost 100Hz 10kHz, respectively. 25VP-P output 20kHz. -3dB 24kHz from 1kHz reference.
DUAL SUPPLIES +15V 0.005µF 5.1M CA3140 0.1µF
BOOST 0.012µF 2.2M
TREBLE 200k (LINEAR) 0.001µF 100pF
0.1µF -15V
0.022µF
0.0022µF
100k (LOG) BOOST BASS TONE CONTROL NETWORK
TONE CONTROL NETWORK
FIGURE TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)
SINGLE SUPPLY BOOST 0.047µF BASS (LINEAR) 240k 240k 2.2M 2.2M +32V +15V CA3140 0.047µF 20pF (LINEAR) BOOST TREBLE TONE CONTROL NETWORK TONE CONTROL NETWORK CA3140 0.1µF
DUAL SUPPLIES
-15V 0.1µF
±15dB Bass Treble Boost 100Hz 10kHz, Respectively. 25VP-P Output 20kHz. -3dB 70kHz from 1kHz Reference. Flat Position Gain.
FIGURE BAXANDALL TONE CONTROL CIRCUIT USING CA3140 SERIES
FN957.10 July 2005
CA3140, CA3140A
Wien Bridge Oscillator
Another application CA3140 that makes excellent high input impedance, high slew rate, high voltage qualities Wien Bridge sine wave oscillator. basic Wien Bridge oscillator shown Figure When frequency equation reduces familiar 1/(2RC) gain required oscillation, AOSC equal Note that increased factor four reduced factor four, gain required oscillation becomes 1.5, thus permitting potentially higher operating frequency closer gain bandwidth product CA3140.
1000pF 1000 +15V CA3140 0.1µF SUBSTRATE CA3019 0.1µF -15V 0.1µF 7.5k OUTPUT 19VP-P 22VP-P <0.3%
CA3109 DIODE ARRAY
NOTES:
OUTPUT
50Hz, 100Hz, 1kHz, 10kHz, 30kHz,
3.3M 1.6M 160M 5.1M
3.6k
FIGURE WIEN BRIDGE OSCILLATOR CIRCUIT USING CA3140
Simple Sample-and-Hold System Figure shows very simple sample-and-hold system using CA3140 readout amplifier storage capacitor. CA3080A serves both input buffer amplifier feed-through transmission switch (see Note 13). System offset nulling accomplished with CA3140 offset nulling terminals. typical simulated load 30pF shown schematic.
STROBE 1N914 +15V 1N914 INPUT CA3140 CA3080A +15V 0.1µF 3.5k HOLD SAMPLE
FIGURE BASIC WIEN BRIDGE OSCILLATOR CIRCUIT USING OPERATIONAL AMPLIFIER
Oscillator stabilization takes many forms. must precisely set, otherwise amplitude will either diminish reach some form limiting with high levels distortion. element, commonly replaced with some variable resistance element. Thus, through some control means, value adjusted maintain constant oscillator output. channel resistance, thermistor, lamp bulb, other device whose resistance increases output amplitude increased elements often utilized. Figure shows another means stabilizing oscillator with zener diode shunting feedback resistor Figure 21). output signal amplitude increases, zener diode impedance decreases resulting more feedback with consequent reduction gain; thus stabilizing amplitude output signal. Furthermore, this combination monolithic zener diode bridge rectifier circuit tends provide zero temperature coefficient this regulating system. Because this bridge rectifier system time constant, i.e., thermal time constant lamp bulb, time constant filters often used detector networks, there lower frequency limit. example, with polycarbonate capacitors frequency determining network, operating frequency 0.007Hz. frequency increased, output amplitude must reduced prevent output signal from becoming slewrate limited. output frequency 180kHz will reach slew rate approximately 9V/µs when amplitude 16VP-P.
0.1µF
-15V 200pF
100k -15V
200pF
0.1µF 30pF SIMULATED LOAD REQUIRED
FIGURE SAMPLE HOLD CIRCUIT
this circuit, storage compensation capacitance (C1) only 200pF. Larger value capacitors provide longer "hold" periods with slower slew rates. slew rate
0.5mA 200pF 2.5V NOTE: AN6668 "Applications CA3080 3080A High Performance Operational Transconductance Amplifiers".
FN957.10 July 2005
CA3140, CA3140A
Pulse "droop" during hold interval 170pA/200pF which 0.85µV/µs; (i.e., 170pA/200pF). this case, 170pA represents typical leakage current CA3080A when strobed off. were increased 2000pF, "hold-droop" rate will decrease 0.085µV/µs, slew rate would decrease 0.25V/µs. parallel diode network connected between Terminal CA3080A Terminal CA3140 prevents large input signal feedthrough across input terminals CA3080A 200pF storage capacitor when CA3080A strobed off. Figure shows dynamic characteristic waveforms this sample-and-hold system.
Current Amplifier
input terminal current needed drive CA3140 makes ideal current amplifier applications such shown Figure (see Note 14). this circuit, current supplied input potential power supply load resistor This load current increased multiplication factor R2/R1, when load current monitored power supply meter Thus, load current 100nA, with values shown, load current presented supply will 100µA; much easier current measure many systems.
+15V POWER SUPPLY 0.1µF CA3140 0.1µF
100k
Trace: Output; 50mV/Div., 200ns/Div. Bottom Trace: Input; 50mV/Div., 200ns/Div.
4.3k -15V
FIGURE BASIC CURRENT AMPLIFIER CURRENT MEASUREMENT SYSTEMS
Note that input output voltages transferred same potential only output current multiplied scale factor. dotted components show method decoupling circuit from effects high output load capacitance potential oscillation this situation. Essentially, necessary high frequency feedback provided capacitor with dotted series resistor providing load decoupling. Full Wave Rectifier Figure shows single supply, absolute value, ideal fullwave rectifier with associated waveforms. During positive excursions, input signal through feedback network directly output. Simultaneously, positive excursion input signal also drives output terminal (No. inverting amplifier negative going excursion such that 1N914 diode effectively disconnects amplifier from signal path. During negative going excursion input signal, CA3140 functions normal inverting amplifier with gain equal -R2/R1. When equality equations shown Figure satisfied, full wave output symmetrical.
NOTE: "Operational Amplifiers Design Applications", Graeme, McGraw-Hill Book Company, page 308, "Negative Immittance Converter Circuits".
Trace: Output Signal; 5V/Div, 2µs/Div. Center Trace: Difference Input Output Signals through Tektronix Amplifier 7A13; 5mV/Div., 2µs/Div. Bottom Trace: Input Signal; 5V/Div., 2µs/Div. LARGE SIGNAL RESPONSE SETTLING TIME
SAMPLING RESPONSE Trace: Output; 100mV/Div., 500ns/Div. Bottom Trace: Input; 20V/Div., 500ns/Div. FIGURE SAMPLE HOLD SYSTEM DYNAMIC CHARACTERISTICS WAVEFORMS
FN957.10 July 2005
CA3140, CA3140A
+15V 0.1µF 0.1µF INPUT 100k OFFSET ADJUST PEAK ADJUST CA3140 1N914 100pF SIMULATED LOAD +15V
CA3140
0.1µF -15V 0.05µF
(-3dB) 4.5MHz 9V/µs
GAIN -10k 0.75
FIGURE 28A. TEST CIRCUIT
20VP-P Input (-3dB) 290kHz, Output (Avg) 3.2V
OUTPUT INPUT
Trace: Output; 50mV/Div., 200ns/Div. Bottom Trace: Input; 50mV/Div., 200ns/Div. FIGURE 28B. SMALL SIGNAL RESPONSE
FIGURE SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
+15V CA3140 0.01µF NOISE VOLTAGE OUTPUT
0.01µF -15V
30.1k
(Measurement made with Tektronix 7A13 differential amplifier.) Trace: Output Signal; 5V/Div., 5µs/Div. Center Trace: Difference Signal; 5mV/Div., 5µs/Div.
(-3dB) 140kHz TOTAL NOISE VOLTAGE (REFERRED INPUT) 48µV (TYP)
Bottom Trace: Input Signal; 5V/Div., 5µs/Div. FIGURE 28C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING SETTLING TIME FIGURE SPLIT SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT ASSOCIATED WAVEFORMS
FIGURE TEST CIRCUIT AMPLIFIER (30dB GAIN) USED WIDEBAND NOISE MEASUREMENT
FN957.10 July 2005
CA3140, CA3140A Typical Performance Curves
GAIN BANDWIDTH PRODUCT (MHz) 100pF 25oC 125oC
OPEN-LOOP VOLTAGE GAIN (dB)
-55oC SUPPLY VOLTAGE 25oC 125oC
-55oC
SUPPLY VOLTAGE
FIGURE OPEN-LOOP VOLTAGE GAIN SUPPLY VOLTAGE TEMPERATURE
FIGURE GAIN BANDWIDTH PRODUCT SUPPLY VOLTAGE TEMPERATURE
QUIESCENT SUPPLY CURRENT (mA) -55oC
100pF
25oC 125oC SLEW RATE (V/µs) SUPPLY VOLTAGE -55oC
25oC 125oC
SUPPLY VOLTAGE
FIGURE SLEW RATE SUPPLY VOLTAGE TEMPERATURE
SUPPLY VOLTAGE: ±15V 25oC OUTPUT SWING (VP-P)
FIGURE QUIESCENT SUPPLY CURRENT SUPPLY VOLTAGE TEMPERATURE
COMMON-MODE REJECTION RATIO (dB) SUPPLY VOLTAGE: ±15V 25oC
100K FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE MAXIMUM OUTPUT VOLTAGE SWING FREQUENCY
FIGURE COMMON MODE REJECTION RATIO FREQUENCY
FN957.10 July 2005
CA3140, CA3140A Typical Performance Curves
1000 EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz) SUPPLY VOLTAGE: ±15V 25oC POWER SUPPLY REJECTION RATIO (dB) +PSRR
(Continued)
SUPPLY VOLTAGE: ±15V 25oC
-PSRR
POWER SUPPLY REJECTION RATIO (PSRR) VIO/VS FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE EQUIVALENT INPUT NOISE VOLTAGE FREQUENCY
FIGURE POWER SUPPLY REJECTION RATIO FREQUENCY
FN957.10 July 2005
CA3140, CA3140A Metallization Mask Layout
58-66 (1.473-1.676)
4-10 (0.102-0.254) 62-70 (1.575-1.778)
Dimensions parenthesis millimeters derived from basic inch dimensions indicated. Grid graduations mils (10-3 inch). photographs dimensions represent chip when part wafer. When wafer into chips, cleavage angles instead with respect face chip. Therefore, isolated chip actually mils (0.17mm) larger both dimensions.
FN957.10 July 2005
CA3140, CA3140A Dual-In-Line Plastic Packages (PDIP)
INDEX AREA
E8.3 (JEDEC MS-001-BA ISSUE
LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES Rev. 12/93
0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
BASE PLANE SEATING PLANE 0.010 (0.25)
NOTES: Controlling Dimensions: INCH. case conflict between English Metric dimensions, inch dimensions control. Dimensioning tolerancing ANSI Y14.5M-1982. Symbols defined Series Symbol List" Section Publication Dimensions measured with package seated JEDEC seating plane gauge GS-3. dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010 inch (0.25mm). measured with leads constrained perpendicular datum measured lead tips with leads unconstrained. must zero greater. maximum dimensions include dambar protrusions. Dambar protrusions shall exceed 0.010 inch (0.25mm). maximum number terminal positions. Corner leads E8.3, E16.3, E18.3, E28.3, E42.6 will have dimension 0.030 0.045 inch (0.76 1.14mm).
0.100 0.300 0.115 0.430 0.150
2.54 7.62 10.92 3.81
2.93
FN957.10 July 2005
CA3140, CA3140A Small Outline Plastic Packages (SOIC)
INDEX AREA SEATING PLANE 0.25(0.010)
M8.15 (JEDEC MS-012-AA ISSUE
LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 1.35 0.10 0.33 0.19 4.80 3.80 1.75 0.25 0.51 0.25 5.00 4.00 NOTES Rev. 12/93
0.0532 0.0040 0.013 0.0075 0.1890 0.1497
0.0688 0.0098 0.020 0.0098 0.1968 0.1574
0.10(0.004)
0.050 0.2284 0.0099 0.016 0.2440 0.0196 0.050
1.27 5.80 0.25 0.40 6.20 0.50 1.27
0.25(0.010)
NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch). Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact.
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FN957.10 July 2005
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