Field-Programmable Microcontroller Peripherals with Supervisory Functi
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ZPSD7XX(V) Family
Field-Programmable Microcontroller Peripherals with Supervisory Functions
ZPSD7XX(V) series first family Field Programmable Microcontroller Peripherals that includes Supervisory Control Functions Zero-Power CMOS Technology. ZPSD7XX(V) devices used rapidly implement highly integrated embedded Low-Power control system. ZPSD7XX(V) devices integrate many peripheral functions inherent microcontroller based applications including: EPROM, SRAM, programmable logic, reconfigurable ports, programmable power management, voltage monitor, WatchDog timer. ZPSD7XX(V) family provides complete solution microcontroller support protection. ZPSD7XX(V) family developed around innovative "microcontroller-macrocell" logic architecture called Microcell. MicroCell specifically created address unique requirements embedded system designs. allows direct connection between system address/data registers which greatly simplifies communication between supporting devices. addition MicroCell based PLD, ZPSD7XX(V) offers Supervisory functions needed monitor embedded system performance. These functions include programmable voltage monitor, WatchDog timer, reset pulse generator automatic battery backup on-board SRAM. Since Supervisory functions fully programmable, ZPSD7XX(V) offers flexibility using standard, shelf product variety designs under different voltage, reset clock frequency requirements.
Features
simple, programmable interface microcontrollers using either multiplexed
non-multiplexed busses. interface logic directly decodes microcontroller control signals. Microcontroller families supported include Intel 8031, 80196, 80186, 80C251 80386EX; Motorola 68HC11, 68HC16, 68HC12 683XX; Philips 8031 8051XA; National 16000; Zilog Neuron 3150.
Four Zero-Power PLDs (ZPLDs) with Output MicroCells Input MicroCells,
inputs product terms. ZPSD7XX(V) PLDs used efficiently implement variety logic functions including state machines address decoders internal external control. also provides seven external chip select outputs generates control WatchDog timer.
Embedded Input Output MicroCells enable efficient implementation user
defined system logic functions that require both microcontroller software hardware interaction.
Return Main Menu
ZPSD7XX(V) Family
Features
(cont.)
ZPSD7XX(V) provides supervisory functions required microcontroller
based system. supervisory features include: System power supply monitoring with configurable trip points. User programmable WatchDog Timer, controlled PPLD product terms. Reset generation based input from: Voltage comparator with programmable internal external trip point. Push button system reset input. WatchDog Timer time out. Automatic battery-backup internal SRAM Write protect internal SRAM external battery back device. Reset input debounce filter. Programmable reset pulse width generator.
Zero-Power Technology that reduces device standby current typical. Twenty seven individually configurable Port pins. Ports used
I/Os, ZPLD I/Os, latched address outputs special function I/Os. Sixteen port pins configured open drain outputs.
Internal EPROM densities Kbit, Kbit Mbit, configurable eight
sixteen-bit widths. EPROM divided into eight equal-size blocks, accessible user-specified addresses. access time includes address latching ZPLD decoding. EPROM includes power option.
Internal Kbit SRAM configured eight sixteen-bit data widths. SRAM
retains data power lost automatically switching standby power.
page register expands microcontroller address space factor sixteen. security prevents copying ZPSD7XX(V) configuration ZPLD logic well
EPROM contents device programmers.
programmable Power Management Unit (PMU) supports separate, low-power
modes allowing operations with little VCC). device automatically detect lack microcontroller activity into power down mode.
devices available EPROM versions. ceramic package ideal
prototyping low-volume production, versions high-volume, low-cost applications.
Package choices include plastic ceramic chip carriers. ZPSD7XX(V) family development supported based PSDsoftdesign
system. software MS-Windows® Windows compatible. suite includes PSDabel(ABEL® specify ZPLD logic, efficient fitter. tool also includes PSDsilosIII simulator from SIMUCADTM. MagicPro® programmer engineering development tool program device.
Please refer revision block this document updated information.
ZPSD7XX(V) Family
ZPSD7XX(V) Architectural Overview
Figure ZPSD7XX(V) Block Diagram
ADDRESS 16-BIT DATA /CONTROL
EPROM
PAGE ZPLD INPUT EIGHT BLOCKS
256K MBIT EPROM
BATTERY BACK-UP INCLUDING ZERO-POWER FEATURES VSTDBY (PC2)
DECODE ZPLD
SRAM
BITS BATTERY BACK
AD0-AD15
ADDRESS/DATA
PERIPHERAL SELECTS DECODE PROGRAMMABLE PORT PA0-PA7
EXTERNAL ZPLD
CONTROL
CONTROL INTERFACE
CHIP SELECT ALLOCATOR
EXTERNAL CHIP SELECTS DIRECT MICROCELLS ACCESS FROM DATA
PROGRAMMABLE PORT
PB0-PB7
GENERAL ZPLD
CLKIN ZPLD INPUT SECURITY FEATURE ALLOC.
OUTPUT MICROCELLS
MICROCELL ALLOCATOR PORTS
PROGRAMMABLE PORT
PD0-PD2
NIBBLE
INPUT MICROCELLS (PORT A,B,C)
PROGRAMMABLE PORT
PC0-PC1 PC3-PC7
DIRECT MICROCELL OUTPUT DATA OUTPUT MICROCELL FEEDBACK INPUT MICROCELL INPUT PORTS
PERIPHERAL ZPLD
WATCHDOG TIMER
POWER MONITOR
VSTBY
RESET PULSE GENERATOR RESET WDOG GRESET ERESET SUPERV
ZPSD7XX(V) Family
ZPSD7XX(V) family Field Programmable Microcontroller Peripherals combines supervisory control functions, memory, innovative system architecture provide user-programmable, feature rich, low-power solution microcontroller system design. user programmable supervisory functions integrated inside ZPSD7XX(V) protect embedded systems from failure sudden loss power, power supply glitches, signal corruption, memory loss. high level integration ZPSD7XX(V) device dramatically reduces number discrete components greatly simplifying embedded system development. ZPSD7XX(V) family supported Windows-based PSDsoft Development System. PSDsoft design flow shown Figure ZPLD design entry done using PSDabel, which creates minimized logic implementation, provides logic simulation ZPLDs. ZPSD7XX(V) Interface, Port configuration, Supervisory Function settings entered PSDconfiguration. PSDcompiler, comprised fitter address translator, generates object file from PSDabel, PSDconfiguration code files. object file then downloaded programmer (MagicPro III, Data I/O, other third party programmer device programming) PSDsimulator (PSDsilos Logic simulator) device-level simulation.
General Information
Development System
Figure PSDsoft Development Tools
PSDabel
ZPLD DESCRIPTION GENERATE ABEL FILE DESIGN TEMPLATE
PSDconfiguration
CONFIGURE INTERFACE
PSDcompiler
FITTER ZPLD FITTING ADDRESS TRANSLATOR EPROM MAPPING PROGRAM CODE FILE
THIRD PARTY PROGRAMMERS .OBJ FILE
PSDsimulator
PSDsilos CHIP SIMULATION
PSDprogrammer
Magic Pro® PROGRAMMER CHIP PROGRAMMING
ZPSD7XX(V) Family
ZPSD7XX(V) window package versions ideal general purpose embedded systems development. ZPSD7XX(V) versions deliver lowest cost ZPSD7XX(V) solution.
Device Versions
ZPSD7XX(V) Family
There devices ZPSD7XX(V) family. part classifications based EPROM size data width operating voltage range. features each part listed Tables
Table ZPSD7XX Product Matrix Part
ZPSD712S0 ZPSD701S5 ZPSD711S5 ZPSD702S5 ZPSD712S5 ZPSD703S5 ZPSD713S5
Width
x8/x16 x8/x16 x8/x16
Pins
EPROM
1024 1024
SRAM
Operating Voltage
Table ZPSD7XX(V) Product Matrix Part
ZPSD703S3V ZPSD713S3V
Width
x8/x16
Pins
EPROM
1024 1024
SRAM
Operating Voltage
Table ZPSD7XX(V) Product Matrix Part
ZPSD711S2V ZPSD712S2V ZPSD703S2V ZPSD713S2V
Width
x8/x16
Pins
EPROM
1024 1024
SRAM
Operating Voltage
3.0V
ZPSD7XX(V) Family
following table describes names functions ZPSD7XX(V). Pins that have multiple names and/or functions defined configuration.
Table ZPSD7XX(V) Descriptions
Name
ADIO0-7
30-37
Type
Function Description
Address/Data Port, interface Microcontroller Input pins multiplexed order address/data byte. latches address A0-7. drives data only read active internal functional blocks selected. Address A0-7 inputs non-multiplexed 80C251 mode A4/D0-A11/D7 inputs 80C51XA mode Address latched address) inputs ZPLD Address/Data Port, interface Microcontroller Address A8-15 inputs 8-bit data mode, multiplexed high order address/data byte inputs 16-bit data mode. latches address A8-15. drives data only read active internal functional blocks selected. Address A8-15 inputs non-multiplexed mode AD8-AD15 inputs 80C251 mode A12-A19 A12/D8 A19/D15 inputs 80C51XA mode Address latched address) inputs ZPLD Write Input with multiple configurations. Depending interface selected, this active write input read/write pin, write cycle data only, write byte, active Control signal (CNTL0) input ZPLD Read Data Strobe Input with multiple configurations. Depending interface selected, this active read input clock input. During write cycle, high During read cycle, high high Data Strobe, active Strobe data byte, 16-bit data mode, active PSEN Program Select Enable, active read cycle (80C251 configuration) Control signal (CNTL1) input ZPLD Read other Control input with multiple configurations. Depending interface selected, this PSEN Program Select enable, active code fetch cycle High byte enable, 16-bit data Strobe high data byte, 16-bit data mode, active SIZ0 Byte enable input Control signal (CNTL2) input general input ZPLD
ADIO8-15
39-46
CNTL0) (WR, R_W, WRL)
CNTL1 (RD, LDS, PSEN)
CNTL2 (PSEN, BHE, UDS, SIZ0)
ZPSD7XX(V) Family
Table ZPSD7XX(V) Descriptions
(cont.)
Name
Reset
Type
Function Description
Active input. Resets Ports, ZPLD MicroCells some Configuration Registers. Must active power Port This port configurable multiple functions: standard output input port External chip select (ECSPLD) output, input GPLD Latched address outputs (see Table Address A0-3 inputs 80C51XA mode Data Port (D0-3) non-multiplexed configuration Peripheral mode Port This port configurable multiple functions: standard output input port GPLD MicroCell (McellAB) output input Latched address outputs (see Table Data Port non-multiplexed configuration Peripheral mode Port This port configurable multiple functions: standard output input port External chip select (ECSPLD) output, input GPLD Latched address outputs (see Table Data Port (D8-11) non-multiplexed configuration with 16-bit data Port This port configurable multiple functions: standard output input port GPLD MicroCell (McellAB) output input Latched address outputs (see Table Data Port (D12 -15) non-multiplexed configuration with 16-bit data
CMOS Open Drain
CMOS Open Drain
This port configurable multiple functions: standard output input port CMOS GPLD MicroCell (McellC) output input only Write strobe (WRH) input high byte. Open Active 16-bit with Drain Supervisory Function (pin PC1-PC6), Table
ZPSD7XX(V) Family
Table ZPSD7XX(V) Descriptions
(cont.)
Name
(ALE)
Type
Function Description
Port configured input latches addresses ADIO0 pins GPLD input ECSPLD output Port configured GPLD input External chip select (ECSPLD) output CLKIN clock input clock input GPLD MicroCells, power down counter GPLD Array Port configured GPLD input External (ECSPLD) output input When low, enables EPROM/SRAM. When high, EPROM/SRAM disabled conserve power Power pins Ground pins
(CLKIN)
(CSI)
Table ZPSD7XX(V) Supervisory Pins
Name
(RST_OUT) (VSTBY) (CEOUT)
Type
Function Description
Active reset output. SRAM Standby Voltage (battery) input. Chip select output that used external non-volatile writable memory. This chip select becomes inactive automatically when ZPSD7XX(V) switched standby voltage. conserve power external battery backup SRAM prevent unwanted writes external EEPROM, SRAM, FLASH. driven high when ZPSD7XX(V) switched over Standby Voltage. Active high reset output. External Reference voltage input Voltage Comparator.
(VSTBYON) (RST_OUT) (VTP)
ZPSD7XX(V) Family
Port Latched Address Output Assignments*
Table Latched Address Outputs Microcontroller
8051XA (8-Bit) 80C251 (Page Mode) Other 8-Bit Multiplexed 8051XA (16-Bit) Other 16-Bit Multiplexed 8-bit Non-Multiplexed
Applicable
Port (3:0)
Address [3:0] Address [3:0]
Port (7:4)
Address [7:4] Address [7:4] Address [7:4] Address [7:4]
Port (3:0)
Address [11:8] Address [11:8] Address [3:0] Address [11:8] Address [11:8]
Port (7:4)
Address [15:12] Address [7:4] Address [15:12] Address [15:12]
Address [3:0]
Address [7:4]
Refer Port Section enable Latched Address Output function.
ZPSD7XX(V) Register Description Address Offset
Tables show offset address ZPSD7XX(V) registers relative CSIOP base address. CSIOP space bytes address that allocated user internal ZPSD7XX(V) registers. Some Motorola 16-bit microcontrollers, including M68HC16, M68302 M683XX, have different data byte orientation requiring separate address offset maps. Table shows CSIOP address offsets MCUs except those from Motorola 16-bit mode. Table shows address offsets Motorola MCUs 16-bit mode.
ZPSD7XX(V) Family
ZPSD7XX(V) Register Description Address Offset (cont.)
Table Register Address Offset Register Name
Data Control Data
Port Port Port Port Other*
Description
Reads Port input, input mode Selects mode between Address Stores data output Port pins, output mode Configures Port input output Configures Port between CMOS, Open Drain Slew Rate Reads Input MicroCell Reads status output enable Port driver Read reads output MicroCells (McellC, McellAB) Write loads Microcell Flip-Flops
Direction Drive
Input MicroCell Enable
Output MicroCell
PMMR0 PMMR1 Page Status
Power Management Register Power Management Register Page Register 8031/PIO Configuration Register Read only Supervisory register. Indicates status source reset reference voltage level. Write only. write register clears reset status bits Status Register. Read only. Indicates status Supervisory pins. Read only. Indicates configuration WatchDog Timer. Contains WatchDog Timer count bits Contains WatchDog Timer count clock source reset pulse width.
Reset-Clr
Supv-Pins
WD-Conf
WD-Count WD-Misc
*Other registers that part ports.
ZPSD7XX(V) Family
ZPSD7XX(V) Register Description Address Offset
(cont.)
Table Register Address Offset 16-Bit Motorola Microcontrollers 16-Bit Mode Register Name
Data Control Data Direction Drive
Port Port Port Port Other*
Description
Reads Port input, input mode Selects mode between Address Stores data output Port pins, output mode Configures Port input output Configures Port between CMOS, Open Drain Slew rate Reads Input MicroCell Reads status output enable Port driver Read reads output MicroCells (McellC, McellAB) Write loads Microcell Flip-Flops
Input MicroCell Enable
Output MicroCell
PMMR0 PMMR1 Page Status
Power Management Register Power Management Register Page Register 8031/PIO Configuration Register Read only Supervisory register. Indicates status source reset reference voltage level. Write only. write register clears reset status bits Status Register. Read only. Indicates status Supervisory pins. Read only. Indicates configuration WatchDog Timer. Contains WatchDog Timer count bits Contains WatchDog Timer count clock source reset pulse width.
Reset-Clr
Supv-Pins
WD-Conf
WD-Count WD-Misc
*Other registers that part ports.
ZPSD7XX(V) Family
ZPSD7XX(V) devices consist several major functional blocks. Figure shows architecture ZPSD7XX(V) family. functions each block described briefly following sections. Many blocks perform multiple functions, user configurable.
ZPSD7XX(V) Architectural Overview
Zero-Power PLDs
device contains four ZPLD blocks each optimized different function shown Table functional partitioning ZPLDs reduces power consumption, optimizes cost/performance ease design entry. Decode (DPLD) used decode generate chip selects ZPSD7XX(V) internal memory, registers peripheral mode. External Chip Select (ECSPLD) optimized generate chip selects devices external ZPSD7XX(V). General Purpose (GPLD) implement user defined logic functions. DPLD ECSPLD have combinatorial outputs while GPLD Output MicroCells. ZPSD7XX(V) also Input MicroCells that configured inputs PLD. ZPLDs receive their inputs from ZPLD Input differentiated their output destinations, number product terms, MicroCells. Peripheral (PPLD) dedicated generate control signals WatchDog timer. ZPLDs designed consume power using Zero-Power design techniques. speed power consumption ZPLD controlled Turbo PMMR0 Register that microcontroller.
Table Name
Decode External Chip Select General Peripheral
Abbreviation
DPLD ECSPLD GPLD PPLD
Inputs
Outputs
Product Terms
Ports
ZPSD7XX(V) pins divided among four ports. Each individually configured provide many functions. Ports configured standard ports, ZPLD I/O, latched address outputs microcontrollers using multiplexed address/data busses. Ports also configured data port microcontrollers with non-multiplexed bus. these modes, Port connected D0-7 Port D8-15.
ZPSD7XX(V) Family
ZPSD7XX(V) Architectural Overview
(cont.)
Supervisory Functions
ZPSD7XX(V) provides supervisory functions required embedded system. voltage comparator monitors system power supply generates reset drops below internal external reference voltages (hysterisis included). polarity duration reset output signal programmable. noise filter reset input provided debounce source (pushbutton other). internal ZPSD7XX(V) SRAM automatically switched standby voltage drops below standby voltage value. When switchover occurs, internal SRAM write protected single user defined chip select output immediately goes inactive. This special chip select supports additional external battery backup SRAM ensure power consumption during fault) provides protection against inadvertent writes external FLASH EEPROM. WatchDog timer provided monitor software integrity. Normal program flow will continually reset WatchDog timer. However, program flow malfunctions hangs timer will timeout reset system. This 9-bit WatchDog timer programmable supply independent clock source.
Microcontroller Interface
ZPSD7XX(V) easily interfaces with most popular eight sixteen-bit microcontrollers with either multiplexed non-multiplexed address/data busses. device configured respond microcontroller control signals which also used inputs ZPLDs.
Memory
ZPSD7XX(V) contains EPROM SRAM. EPROM densities available Kbit, Kbit Mbit. memory space divided into eight equally-sized blocks. Each block located different address space defined user. access time EPROM includes address latching DPLD decoding. Kbit SRAM used scratch memory extension microcontroller SRAM. SRAM data retained event system power down, provided backup battery connected Vstby (PC2). Switching from supply standby power occurs automatically when drops below Vstby voltage.
Page Register
four-bit Page Register expands address range microcontroller sixteen times. paged address used part address space access external memory peripherals internal EPROM, SRAM I/O.
Power Management Unit
Power Management Unit (PMU) ZPSD7XX(V) enables user control power consumption selected functional blocks based system requirements. includes Automatic Power Down unit (APD) that will turn device functions microcontroller inactivity modes: Power Down mode Sleep mode. Other power saving features, such CMiser Turbo bits PMU, allow EPROM/SRAM/ZPLD operate slower rate conserve power.
ZPSD7XX(V) Family
ZPSD7XX(V) consists five major functional blocks:
ZPSD7XX(V) Functional Blocks
ZPLD Block Interface Ports Memory Block Power Management Unit Supervisory Function
functions each block described following sections. Many blocks perform multiple functions, user configurable.
ZPLDs
Zero-Power PLDs (ZPLDs) bring programmable logic functionality ZPSD7XX(V). After specifying logic PLDs using PSDabel tool PSDsoft, logic configuration programmed into device available when power applied. ZPLDs (DPLD, ECSPLD, GPLD, PPLD) consist array. GPLD architecture includes Output MicroCells addition array. There Input MicroCells that configured inputs ZPLD. Figure shows organization ZPLD. array used form product terms specified using PSDabel tool PSDsoft development system. When inputs used term true, output active. GPLD Input consists signals shown Table Both true complement value inputs available array. DPLD ECSPLD Input Busses consists fewer inputs subset inputs.
Table GPLD Inputs Input Source
Address Control Signals Power Down Ports Inputs (Input MicroCells) Port Inputs Page Register Port MicroCell Feedback Port MicroCell Feedback Supervisory Function WatchDog Time Supervisory Function Global Reset Expanded Reset Supervisory Clock 2KHz Internal Oscillator CLKIN/8192 *NOTE:
Input Name
[15:0]* CNTL [2:0] [7:0], [7:0], [7:0] [2:0] [3:0] MCELLAB.FB [7:4] MCELLC.FB [7:0] WDOG_ON GRESET ERESET Superv_CLK
Number Signals
address inputs A[19:4] 80C51XA mode.
ZPSD7XX(V) Family
ZPLDs
(cont.)
Figure Block Diagram
DECODE ZPLD
EPROM SELECTS
SRAM SELECT CSIOP SELECT PERIPHERAL SELECTS
EXTERNAL ZPLD
ZPLD INPUT CHIP SELECT ALLOCATOR EXTERNAL CHIP SELECTS PORT DIRECT MICRO CELL ACCESS FROM DATA
GENERAL ZPLD
ALLOC.
OUTPUT MICROCELL
MICROCELL ALLOCATOR PORTS MCELL PORT MCELL PORT
NIBBLE
INPUT MICROCELL (PORT A,B,C)
DIRECT MICROCELL OUTPUT DATA OUTPUT MICROCELL FEEDBACK, INPUT MICROCELL INPUT PORTS PORT INPUTS WDOG GRESET ERESET SUPERV
PERIPHERAL ZPLD
WDOG WDOG
ZPSD7XX(V) Family
ZPLDs minimize power consumption switching when inputs remain unchanged extended time about 70ns. Setting Turbo mode (Bit PMMR0 register) automatically places ZPLDs into standby inputs changing. Turbo mode increases propagation delays while reducing power consumption. Refer Power Management Unit Turbo Bit. Power further reduced PSDsoft development tools which disables unused product terms. Each four ZPLDs unique characteristics suited applications. They described following sections.
ZPLDs
(cont.)
Decode ZPLD
Decode ZPLD (DPLD), shown Figure used select internal ZPSD7XX(V) functions: EPROM blocks, SRAM, Registers (CSIOP) Port Peripheral Mode. select signals active high have product term, except which two. CSIOP select line ZPSD7XX(V) internal registers that occupies bytes memory space. second level decoder selects register based address inputs A[7-0]. Each EPROM block chip select. chip select eighth EPROM block product terms, ES7A ES7B. This allows eighth block reside memory spaces, where ES7B typically select reset vectors configuration bytes that stored address space. PSEL used inputs Port control port's Peripheral mode operation. Usually PSEL defined term address inputs. This mode explained Port section.
Table DPLD Inputs Input Source
Address Ports Port Page Register Control Signal Supervisory Function Supervisory Function *NOTE:
Input Name
A[15:0]* [7:0], [7:0], [7:0] [3:0] CNTL1 (Read) GRESET ERESET WDOG_ON
Number Bits
address inputs [19:4] 80C51XA mode. A[3:0] assigned Port
(cont.)
ZPLDs
(INPUTS) (16) ES7A (24)
PORTS (PORT A,B,C)
Figure DPLD Logic Array
PGR0 -PGR3
A[15:0]
EPROM BLOCK SELECTS
READ
CNTL1
ES7B CSIOP PSEL0 PSEL1 PERIPHERAL MODE SELECT SELECT DECODER SELECT
GRESET ERESET
WDOG
ZPSD7XX(V) Family
*NOTE:
address inputs [19:4] 80C51XA mode, [3:0] assigned Port
ZPSD7XX(V) Family
ZPLDs
(cont.)
External Chip Select
External Chip Select (ECSPLD) provides means select external devices. output buffer ECSPLD configured operate high slew rate writing corresponding Drive Register. slew rate measurement rise fall times output. higher slew rate means faster output response while lower slew rate slower response. Refer Table Section setting Drive Register. Faster transitions more likely cause line reflections system noise than slower rates. Adjusting slew rate allows trade-off between greater speed noise sensitivity. selection should based performance requirements system noise characteristics. corresponding bits Drive Register (for normal speed) (for fast drive). default value zero. ECSPLD inputs shown Table outputs combinatorial, either polarity, have product term each shown Figure
Table ECSPLD Inputs Input Source
Address Control Signals Power Down Signal Page Register
Input Name
A[15:0]* CNTL[2:0] PDN** PGR[3:0]
Number Bits
**In 80C51XA mode, address inputs A[19:4] **APD output. When high, ZPSD7XX(V) power down mode seven ECSPLD outputs driven device through Ports shown Table MicroCell Allocator. Port selection specified PSDabel file assigned PSDcompiler.
Table ECSPLD Output Port Assignments ECSPLD Output
ECS0 ECS1 ECS2 ECS3 ECS4 ECS5 ECS6
Port Assignments
PA0, PA1, PA2, PA3, PD0* PD1* PD2*
*Port output enable (.oe) product terms ECS4-6 outputs.
ZPSD7XX(V) Family
ZPLDs
(cont.)
Figure ECSPLD Logic Array
ECS0 (INPUTS) 15:0] (16) POLARITY ECS1 PGR[ 3:0] POLARITY
CNTRL 2:0] READ/WRITE CONTROL SIGNALS OUTPUT ECS6
POLARITY
80C51XA mode, these address inputs A[19:4].
General
General (GPLD) used implement system logic such loadable counters, system mailboxes handshaking protocols. addition GPLD implement random logic state machine functions. GPLD Output Input MicroCells. GPLD, Output Input MicroCells architectures appear Figure along with Port. MicroCells configured using PSDsoft development system. Like other ZPLDs, GPLD array which generate product terms, maximum nine product terms each twelve MicroCells. Input Output MicroCells connected ZPSD7XX(V) internal data directly accessed microcontroller. This enables software load data into Output MicroCells read data from both Input Output MicroCells. This feature allows efficient implementation system logic eliminates need connect data logic array required most standard ZPLD macrocell architectures.
ZPLD INPUT
ARRAY
GPLD OUTPUT COMB. SELECT MICRO CELL PORT ALLOCATOR CLEAR INPUT D/T/JK SELECT CLOCK GLOBAL CLOCK SELECT
ZPLD INPUT
PRODUCT TERMS FROM OTHER MICRO CELLS ADDRESS DATA CONTROL OTHER PORTS
(cont.)
ZPLDs
ZPSD7XX(V) Family
GPLD MICROCELLS PORTS
LATCHED ADDRESS DATA RESET PRODUCT TERM ALLOCATOR LOAD DATA WRITE CONTROL
PRODUCT TERMS MICRO CELL
Figure GPLD Port
GPLD OUTPUT
POLARITY SELECT
CLOCK SELECT
OUTPUT ENABLE (OE) MICRO CELL FEEDBACK PORT INPUT INPUT LATCH GATE/CLOCK G/CK
INPUT MICROCELLS
ZPSD7XX(V) Family
ZPLDs
(cont.)
Output MicroCell
Eight Output MicroCells connected Port pins named McellC0-7. remaining four Micro-Cells connected Port Port named McellAB4-7. McellAB output assigned specific PSDabel, MicroCell Allocator will assign either Port Table shows MicroCells Port assignment.
Table Output MicroCell Port Data Assignments Native Product Terms
Output Port MicroCell Assignment
McellC0 McellC1 McellC2 McellC3 McellC4 McellC5 McellC6 McellC7 McellAB4 McellAB5 McellAB6 McellAB7 Port Port Port Port Port Port Port Port Port Port Port Port
Borrowed Product Terms
Data Data Loading Loading Reading Reading 8-Bit Mode 16-Bit Mode
Product Term Allocator
MicroCells have same basic cell architecture except McellC four native product terms McellAB three product terms. GPLD also Product Term Allocator with which PSDcompiler automatically borrow product terms from MicroCell another. McellC borrow five product terms from other MicroCells total nine product terms. McellAB three native product terms borrow product terms. Borrowing allows MicroCell outputs needing more product terms unused product terms others. architecture Output MicroCells, shown Figure consists native product terms borrowed product terms from other MicroCells. polarity product term input controlled gate. MicroCell implement either sequential logic, using Flip-Flop element, combinatorial functions. multiplexor selects combinatorial sequential logic MicroCell output. multiplexor output drive Port also feedback path array inputs.
Micro Cell Flip-Flop Type
Flip-Flop MicroCell configured Toggle, type using PSDabel PSDsoft. flip-flop Clock, Preset Clear inputs driven from product term array. Alternatively, device clock input (CLKIN) used flip-flop. Preset Clear active high inputs; Flip-Flop clocked rising edge clock input.
(cont.)
ZPLDs
ARRAY
ZPLD INPUT
MICROCELL INTERNAL DATA 15:8] 7:0] ALLOCATOR ENABLE (.OE) PRESET(.PR) POLARITY SELECT PROGRAMMABLE (D/T/JK /SR) CLKIN (NOTE PORT DRIVER CLEAR (.RE) MICROCELL ALLOCATOR (NOTE COMB/REG SELECT DIRECTION REGISTER
ZPSD7XX(V) Family
Figure GPLD Output MicroCell
FEEDBACK (.FB) PORT INPUT INPUT MICROCELL
NOTES: MCELL local product terms. MCELL local product terms. Max. total product terms Allocator MCELL only.
ZPSD7XX(V) Family
ZPLDs
(cont.)
Loading Reading Micro Cells
GPLD MicroCells occupy memory location address space defined CSIOP (refer section). Flip-Flops each MicroCells loaded from data microcontroller write cycle MicroCell (see Port section MicroCell Addresses). data that associates with MicroCell will load Flip-Flop, data will load Flip-Flop. loading cycle takes priority over other Flip-Flop inputs that include Preset, Clear clock. Table data bits that connected MicroCells. ability load flip-flops read them back useful such applications loadable counters, shift registers, mailboxes handshaking protocols.
Table MicroCell Flip-Flop Loading
Normal Flip-Flop Function
NOTE: when writes MicroCell address
Output Enable
MicroCell connected ZPSD7XX(V) output. output enable each Port output driver controlled single product term (.oe) from array ORed with Direction Register output. Upon power output enable (.oe) equation defined declared ZPLD output PSDsoft, enabled. MicroCell output declared internal node Port output PSDabel file, then Port used other functions. internal node feedback routed input array.
Input MicroCell
Input MicroCells shown Figure used latch, register pass incoming Port signals prior driving them onto ZPLD Input bus. outputs these MicroCells also read microcontroller through internal Data Bus. GPLD Input MicroCells, each Ports Input MicroCells individually configurable. enable/clock latch flip-flop driven multiplexor whose inputs product term from GPLD array address strobe (ALE). Each product term output used latch/clock four Input MicroCells. Port inputs [3:0] controlled product term [7:4] controlled another one. Input MicroCell configurations specified equations written PSDabel. Outputs MicroCells read microcontroller "Input MicroCell" buffer. Port section read MicroCells. Input MicroCells latch higher address bits (A31 A16). latched addresses routed ZPLD inputs. Input Micro-Cell particularly useful handshaking communication applications where MCUs wish pass data between each other through commonly accessible storage. Figure shows typical configuration where Master writes Port Data Register that read Slave activation "Slave-Read" output enable product term. Slave write Port Input MicroCells activating Slave-WR product term. Master then read Input MicroCells. Slave-Read Slave-WR signals product terms that derived from Slave signals Slave_CS.
(cont.)
ZPLDs
ARRAY
ZPLD INPUT
INTERNAL DATA 7:0] INPUT MICROCELL DIRECTION REGISTER ENABLE
ZPSD7XX(V) Family
Figure Input MicroCell
OUTPUT MICROCELLS MICROCELL
NOTE
PORT DRIVER
FEEDBACK LATCH INPUT MICROCELL
NOTE:
controls input MicroCells. (Input MicroCells [3:0] [7:4]
(cont.)
ZPLDs
ZPSD7XX(V)
SLAVE SLAVE READ PORT DATA REGISTER GPLD 7:0] PORT
SLAVE
MASTER
SLAVE PORT INPUT MICRO CELL
Figure Handshaking Communication Using Input MicroCells
7:0]
ZPSD7XX(V) Family
ZPSD7XX(V) Family
ZPLDs
(cont.)
Peripheral
Peripheral (PPLD), shown Figure controls operation WatchDog Timer Supervisory Function. input PPLD consists same signals that shared with GPLD (refer Table PPLD provides active high outputs, each consists product term:
WDOG_EN
WatchDog Timer enabled either trailing edge reset generated Supervisory Function, active high WDOG_EN pulse. WDOG_EN product term defined become active when microcontroller writes certain address. WDOG_EN signal activated only after external reset (ERESET) expires.
WDOG_CLR
This active high pulse that re-loads counter WatchDog Timer prevents WatchDog from generating timeout. WDOG_CLR product term defined become active when microcontroller writes specific address.
Figure PPLD Logic Array
ZPLD INPUT WDOG WDOG WDOG SUPERV- WATCHDOG TIMER SUPERVISORY FUNCTION
GRESET ERESET
ZPSD7XX(V) Family
"no-glue logic" ZPSD7XX(V) Microcontroller Interface directly connected most popular microcontrollers. Some these microcontrollers with their types control signals shown Table interface type specified using PSDsoft tools.
Interface
Table 13.Microcontroller Busses Control Signals
8031 68330 80198 68HC11 80C51XA 80C251 80C251 Neuron 3150 80196 80196 68HC12*** 68302 68330 68332 80C51XA 68LC302 80186 80C166
Data
CNTL0
CNTL1
PSEN
CNTL2
PSEN
PD0**
ADIO0
LSTRB A0/BLE A4/D0
PA3-PA0
PSEN
PSEN
SIZ0 PSEN
***Not used CNTL2 configured GPLD input. Other used pins (PC7, PD0, PA3-0) configured other functions. ***ALE/AS input optional microcontrollers with non-multiplexed bus. ***This configuration 68HC12 with non-mux bus.
Table shows names ZPSD7XX(V) interface control pins their functions. control pins have multiple functions configured interface many microcontrollers. Depending microcontroller, some control input pins required used GPLD input other functions. Specific examples interfaces different microcontrollers provided following sections. microcontrollers that have more than address lines, Port pins used additional address inputs
ZPSD7XX(V) Family
Interface
(cont.)
ZPSD7XX(V) Interface Multiplexed
Figure shows example system using microcontroller with multiplexed ZPSD7XX(V). ADIO port ZPSD7XX(V) connected directly microcontroller address/data bus. multiplexed only byte (eight-bit data) both bytes (sixteen-bit data). latches address lines internally; latched addresses brought Port ZPSD7XX(V) drives ADIO data only when internal resources accessed input active.
Figure Example Typical Multiplexed Interface, 16-Bit Data
(OPTIONAL)
PORT
PORT
(OPTIONAL)
ZPSD7XX(V)
(CNTRL1) (CNTRL2)
(CNTRL0)
PORT
(PD0)
15:8]
15:8]
7:0]
PORT RESET
ADIO PORT
MICRO CONTROLLER
ZPSD7XX(V) Family
Interface
(cont.)
ZPSD7XX(V) Interface Non-Multiplexed
Figure shows example system using microcontroller with non-multiplexed ZPSD7XX(V). address connected ADIO Port, data connected Port (D[7:0]) Ports (D[15:8], 16-bit data only). data Ports tri-state mode when ZPSD7XX(V) accessed microcontroller. Should system address exceed sixteen bits, Port used additional address inputs.
Figure Example Typical Non-Multiplexed Interface, 16-Bit Data
(16-BIT DATA ONLY)
PORT
PORT
15:8]
7:0]
ZPSD7XX(V)
(CNTRL1) (CNTRL2)
(CNTRL0)
PORT
(OPTIONAL) (PD0)
ADIO PORT
23:16]
15:0]
15:0]
PORT RESET
MICROCONTROLLER
ZPSD7XX(V) Family
Interface
(cont.)
Data Byte Enable Reference
Microcontrollers have different data byte orientations. following tables show ZPSD7XX(V) interprets byte/word operation different write configurations. Even-byte refers locations with address equal zero byte locations with equal one.
Table 8-Bit Data
Even Byte Byte
Table 16-Bit Data With
Byte Byte
Even Byte Even Byte
Table 16-Bit Data With
Byte Byte Even Byte Even Byte
Table 16-Bit Data With SIZ0, (Motorola MCU) SIZ0
Even Byte Even Byte Byte Byte
Table 16-Bit Data With UDS, (Motorola MCU)
Even Byte Even Byte Byte Byte
ZPSD7XX(V) Family
Interface
(cont.)
Microcontroller Interface Examples
Figures through show examples basic connections between ZPSD7XX(V) some popular microcontrollers. ZPSD7XX(V) control input pins labeled microcontroller function which they configured. interface specified using PSDsoft tools.
80C31
Figure shows interface 80C31 which 8-bit multiplexed address/data bus. lower address byte multiplexed with data bus. microcontroller signals used accessing internal SRAM Ports while PSEN signal used read EPROM. input (Port PD0) latches address. Refer Memory Section additional 80C31 operating modes.
68HC11
Figure shows interface 68HC11 where ZPSD7XX(V) configured 8-bit multiplexed mode with settings. ECSPLD generate READ signals external board devices. CNTL2 used used input.
80C196
Figure Intel 80C196 microcontroller, which multiplexed sixteen-bit bus, shown connected ZPSD7XX(V). signal used high data byte selection. Port pins configured PSDabel outputs control READY BUSWIDTH pins 80C196.
MC68331
Figure shows Motorola MC68331 with non-multiplexed sixteen-bit data 24-bit address bus. data from MC68331 connected Port Port -15). SIZ0 inputs determine high/low byte selection.
80C51XA
Philips 80C51XA microcontroller family multiplexed that supports burst cycles. Address bits A[3:0] multiplexed while A[19:4] multiplexed with data bits D[15:0] 16-bit mode. 8-bit mode, A[11:4] multiplexed with data bits D[7:0]. 80C51XA configured operate with ZPSD7XX(V) 8-bit (shown Figure 16-bit (shown Figure data mode. With 16-bit data bus, 80C51XA's connected ZPSD7XX(V). grounded used. 80C51XA improves throughput performance executing Burst cycles fetch codes from memory. Burst cycles, address latched internally ZPSD7XX(V), while 80C51XA changes lines sequentially fetch bytes code. access time then measured from address valid data valid. ZPSD7XX(V) timing requirement Burst cycle identical normal cycle except address hold time with respect required.
ZPSD7XX(V) Family
Interface
(cont.)
80C251
Intel 80C251 microcontroller features user-configurable interface with four possible configurations shown Table
Table 80C251 Configurations 80C251 Read/Write Pins
PSEN PSEN only PSEN only PSEN
Configuration
Connecting ZPSD7XX(V) Pins
CNTL0 CNTL1 CNTL2 CNTL0 CNTL1 CNTL0 CNTL1 CNTL0 CNTL1 CNTL2
Page Mode
Non-Page Mode, 80C31 compatible [7:0] multiplex with [7:0} Non-Page Mode [7:0] multiplex with [7:0} Page Mode [15:8] multiplex with [7:0} Page Mode [15:8] multiplex with [7:0}
Configuration 80C31 compatible. interface ZPSD7XX(V) identical that shown Figure Configurations have same connection shown Figure There only read input (PSEN) connected CNTL1 ZPSD7XX(V). connection allows larger address input ZPSD7XX(V). Configuration shown Figure signal connected CNTL PSEN signal connected CNTL2. 80C251 major operating modes: Page Mode Non-Page Mode. Non-Page Mode, data multiplexed with lower address byte. active every cycle. Page Mode, data D[7:0] multiplexed with address A[15:8]. cycle where there Page hit, signal active only addresses A[7:0] changing. ZPSD7XX(V) supports both modes. Page Mode, timing identical Non-Page Mode except address hold time setup time with respect required. ZPSD7XX(V) access time measured from address A[7:0] valid data valid. Upon power 80C251 accesses data addresses FFF8h FFF9h where configuration bytes reside. After configuration register set, 80C251 starts executing codes from location 0000h. EPROM block ZPSD7XX(V) chip selects, ES7A ES7B. second chip select, (ES7B) defined occupy configuration byte locations while ES7A assigned different memory space.
(cont.)
Interface
7:0]
80C31
EA/VP RESET INT0 INT1 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN PSEN ALE/P P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7
ZPSD7XX(V)
CNTL0 (WR) CNTL1(RD) CNTL2 (PSEN) (RST- OUT) (VSTBY) (CEOUT) (VSTBYON) (RST-OUT) (VTP)
Figure Interfacing ZPSD7XX(V) with 80C31
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
PD0-ALE RESET
RST-
ZPSD7XX(V) Family
used, RESET must pulled high.
AD[7:0] AD[7:0]
(cont.)
Interface
ZPSD7XX(V) Family
ZPSD7XX(V) 68HC11
RESET XIRQ MODB ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
CNTL0 CNTL1(E) CNTL RESET
Figure Interfacing ZPSD7XX(V) with 68HC11
MODA
(RST- OUT) (VSTBY) (CEOUT) (VSTBYON) (RST-OUT) (VTP)
RST-
used, RESET must pulled high.
(cont.)
Interface
[15:0]
[15:0]
80196 ZPSD7XX(V)
READY BUSWIDTH RESET ACH0/P0.0 ACH1/P0.1 ACH2/P0.2 ACH3/P0.3 ACH4/P0.4 ACH5/P0.5 PCS6/P0.6 PCS7/P0.7 CNTL0 (WR) CNTL1(RD) CNTL 2(BHE) P4.0/AD6 P4.1/AD9 P4.2/AD10 P4.3/AD11 P4.4/AD12 P4.5/AD13 P4.6/AD14 P4.7/AD15 AD10 AD11 AD12 AD13 AD14 AD15 ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15
P3.0/AD0 P3.1/AD1 P3.2/AD2 P3.3/AD3 P3.4/AD4 P3.5/AD5 P3.6/AD6 P3.7/AD7 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
Figure Interfacing ZPSD7XX(V) 80C196
INST CLKOUT P2.0/TXD P2.1/RXD P2.2/EXINT P2.3/T2CLK P2.4/T2RST P2.5/PWM P2.6/T2UP-DN P2.7/T2CAP
PD0-ALE RESET
(RST- OUT) (VSTBY) (CEOUT) (VSTBYON) (RST-OUT) (VTP)
HSI.0 HSI.1 HSI.2/HSO.4 HSI.3/HSO.5
VREF ANGND
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 HSO.0 HSO.1 HSO.2 HSO.3
RST-
ZPSD7XX(V) Family
used, RESET must pulled high.
(cont.)
Interface
[15:0] [15:0] A[18:0] A[18:0]
ZPSD7XX(V) Family
MC68331
ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
ZPSD7XX(V)
RESET DSACK0 DSACK1 A19_CS6 A20_CS7 A21_CS8 A22_CS9 A23_CS10 SIZ0
ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15
CNTL0 CNTL1( CNTL (SIZ0
Figure Interfacing ZPSD7XX(V) MC68331
IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
PD0-AS RESET
(RST- OUT) (VSTBY) (CEOUT) (VSTBYON) (RST-OUT) (VTP)
SIZ0 SIZ1 CLKOUT CSBOOT BR_CS0 BG_CS1 BGACK_CS2 FC0_CS3 FC1_CS4 FC2_CS5
used, RESET must pulled high.
RST-
(cont.)
Interface
80C51XA
XTAL1 XTAL2 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7
ZPSD7XX(V)
PSEN CNTL0 (WR) CNTL1(RD) CNTL (PSEN)
RXD0 TXD0 RXD1 TXD1
T2EX
INT0 INT1
A0/WRH A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15
A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7
PSEN EA/WAIT BUSW
PD0-ALE
(RST- OUT) (VSTBY) (CEOUT) (VSTBYON) (RST-OUT) (VTP)
Figure Interfacing ZPSD7XX(V) 80C51XA, 8-Bit Data
RESET
RST-
ZPSD7XX(V) Family
used, RESET must pulled high.
(cont.)
Interface
80C51XA ZPSD7XX(V)
A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7 XTAL1 XTAL2 RXD0 TXD0 RXD1 TXD1 T2EX INT0 INT1 A0/WRH A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12D9 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 CNTL0 (WR) CNTL1(RD) CNTL (PSEN) A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 PSEN EA/WAIT BUSW PSEN
ZPSD7XX(V) Family
(RST- OUT) (VSTBY) (CEOUT) (VSTBYON) (RST-OUT) (VTP)
Figure Interfacing ZPSD7XX(V) 80C51XA, 16-Bit Data
RESET
RST-
used, RESET must pulled high.
(cont.)
Interface
80C251SB
ZPSD7XX(V)
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
AD10 AD11 AD12 AD13 AD14 AD15
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
AD10 AD11 AD12 AD13 AD14 AD15
P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 RD/A16 PSEN
ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 CNTL0 CNTL1( CNTL 2(PSEN)
PD0-
(RST- OUT) (VSTBY) (CEOUT) (VSTBYON) (RST-OUT) (VTP)
RESET
Figure Interfacing ZPSD7XX(V) 80C251, with READ Input
RST-
ZPSD7XX(V) Family
**If used, RESET must pulled high. **A16 optional.
80C251SB
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
(cont.)
Interface
ZPSD7XX(V) Family
ZPSD7XX(V)
PSEN AD10 AD11 AD12 AD13 AD14 AD15
P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 PSEN RD/A16
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
AD10 AD11 AD12 AD13 AD14 AD15
ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15
CNTL0 CNTL1( CNTL (PSEN)
PD0- RESET
(RST- OUT) (VSTBY) (CEOUT) (VSTBYON) (RST-OUT) (VTP)
RST-
Figure Interfacing ZPSD7XX(V) 80C251, with READ PSEN Input
used, RESET must pulled high.
ZPSD7XX(V) Family
There four programmable ports: Ports bits, Port seven bits Port three bits. ports configured function different modes operation. Each port individually configurable allowing single port perform multiple functions. configuration defined either using PSDsoft tools microcontroller writing on-chip registers.
Ports
General Port Architecture
general architecture Port shown Figure Individual Port diagrams shown Figures will discussed section below. ZPSD7XX(V) configured non-multiplexed mode, Port and/or Port connected data available general purpose ports. shown Figure port pins contain output multiplexer whose selects driven configuration defined PSDabel Control Registers. Inputs multiplexer include following: Output data from Data Register output mode Latched address outputs GPLD MicroCell output ECSPLD external chip select output above inputs also connected Port Data Buffer (PDB) feedback Internal Data that read microcontroller. three-state buffer operating like multiplexer that allows only source read time. also inputs from Direction Register, Control Register direct port input (Data In). Port pin's tri-state output driver enable controlled input gate whose inputs come from GPLD array Enable product term (.oe) Direction Register. enable product term array output defined, then Direction Register sole control buffer. Refer Tables direction port configured.
Table Port Direction Control, Output Enable P.T. Defined Direction Register Port Mode
Input Output
Table Port Direction Control, Output Enable P.T. Defined Direction Register
*Port does have output enable P.T. register contents altered microcontroller. feedback path allows microcontroller check contents registers. Ports have embedded Input MicroCells which configured latch, register direct input GPLD. latch register clocked address strobe product term from GPLD array. output from Input MicroCell drives ZPLD input read microcontroller. Refer Input MicroCell description ZPLD section. Port additional logic (not shown Figure that enables operate Peripheral mode when Register set.
Output Enable P.T.*
Port Mode
Input Output Output Output
(cont.)
Ports
INTERNAL DATA
DATA REG. DATA ADDRESS OUTPUT ADDRESS MICRO CELL OUTPUTS EXT.CS READ DATA OUTPUT SELECT PORT
ZPSD7XX(V) Family
Figure General Port Architecture
CONTROL REG. REG. ENABLE PRODUCT TERM (.OE) INPUT MICRO CELL ENABLE
GPLD INPUT
ZPSD7XX(V) Family
Ports
(cont.)
Port Operating Modes
Ports have several modes operation shown Table mode selected using PSDabel tool programmed into device using Non-Volatile Memory (NVM) that active when power applied cannot altered unless device reprogrammed. mode defined PSDsoft, then other modes microcontroller writing Port configuration registers. ZPLD I/O, Data Port Address Input Supervisory Function modes configurations. other modes initiated microcontroller. modes selected, port altered dynamically between Address modes writing Control Register. Each eight-bit Control Register store "1", setting respective port I/O, "0", setting Address Out. Direction Register output enable product term determine input output. Table summarizes operating modes ports. functions available every port. Table shows where different modes configured.
Table Port Operating Modes Port Mode
ZPLD McellAB Outputs McellC Outputs ECSPLD Outputs ZPLD Inputs Address Address Data Port Open Drain Slew Rate Peripheral Supervisory Function
Port
PA7- (PA7 (PA3
Port
(A7- (D15 (PB7 (PB3
Port
PC7-
Port
ZPSD7XX(V) Family
Ports
(cont.)
Port Operating Modes (cont.) Table Port Operating Mode Settings Defined PSDabel
Declare pins only
Mode
Control Direction Defined Register Register Register PSDconfiguration Setting Setting Setting
output, input (Note (Note (Note
ZPLD Data Port (Port A,B) Address (Port A,B) Address (Port A,B,C)
Logic equations Declare pins only
Specify type
Logic equation Input MicroCells Specify clock source WatchDog configuration Reset output Reference voltage level Standby voltage configuration
Peripheral Logic equations (Port (PSEL0 Supervisory Function Logic equations (WDOG_EN WDOG_CLR)
Applicable
NOTE direction Port pins controlled Direction Register ORed with individual output enable product term (.oe) from GPLD array.
ZPSD7XX(V) Family
Ports
(cont.)
ZPLD Mode
mode uses port input GPLD Input MicroCell, and/or output from GPLD, ECSPLD. Port assignments shown Tables output tri-stated with control signal defined product term (.oe) from ZPLD, setting zero Direction Register. Direction Register must defined ZPLD input pin. ZPLD mode specified PSDabel declaring port pins, then writing equation assigning port.
Mode
Mode microcontroller uses ZPSD7XX(V) ports expand ports. ports ZPSD7XX(V) mapped into microcontroller address space. addresses ports listed Table port will into mode writing zero corresponding Control Register. direction changed writing Direction Register port where makes output input. output enable product term also change direction (see Table 21). When configured output, content Data Register drives pins. input mode, microcontroller reads port input through Data buffer Ports have Control Register mode default pins that configured ZPLD I/O.
Address Mode
microcontrollers with multiplexed address/data bus, ports Address mode drive latched addresses external devices. Address [7:0] always assigned Port Table address output assignments Ports Direction Register Control Register must port pins using Address mode. non-multiplexed mode, address[7:0] available Port Address Mode.
ZPSD7XX(V) Family
Ports
(cont.)
Port Operating Modes (cont.) Address Mode
microcontrollers that have more than address lines, higher addresses connected Port address input latched Input MicroCell ALE. input that included DPLD equations EPROM SRAM considered address input.
Data Port Mode
Port used data ports microcontroller with non-multiplexed address/data bus. Data Port connected data microcontroller. general functions disabled Port port configured Data Port.
Supervisory Function Mode
Port (pins PC1-PC6) configured implement Supervisory Function. Refer Supervisory section detailed description.
Peripheral Mode
Only Port supports Peripheral mode where Port serves tri-state capable bi-directional data buffer microcontroller's data bus. Peripheral mode enabled setting Register "1". Figure shows that when Peripheral mode enabled either PSEL0 PSEL1 from DPLD active, Port acts bi-directional buffer microcontroller D[7:0] data bus. buffer tri-stated when PSEL active. Peripheral mode used interface with external peripherals.
Open Drain/Slew Rate Mode
Ports (pins PA7-4) (pins PB7-4) configured open drain instead CMOS outputs. Open Drain configuration useful sinking large currents operate LEDs, example. Open Drain mode enabled writing corresponding Drive Register. Port (PA3-0), Port (PB3-0) Port configured ECSPLD outputs that have high slew rate. high slew rate enabled writing corresponding Drive Register.
Figure Port Peripheral Mode
PSEL0
PSEL1 DATA
REGISTER
ZPSD7XX(V) Family
Ports
(cont.)
Port Registers
Each port registers used configuration (PCR, Port Configuration Registers) data transfers (PDR, Port Data Registers). contents registers accessed microcontroller through normal read/write cycles addresses given Tables 28a. register addresses comprised CSIOP output from DPLD plus address offset listed tables. pins port individually configurable each register controls respective pin. example, register refers port. three Port Configuration Registers, shown Table used setting port configuration. Each register zero power
Table Port Configuration Registers Register Name
Control Direction Drive*
Port
A,B,C,D A,B,C,D
Access
Write/Read Write/Read Write/Read
*Note: Table Drive Register definition.
Control Register
zero Control Register sets Port Port sets Port Address mode. default mode I/O.
Direction Register
Controls direction data flow Ports. configures port output, input. configuration read from Direction Register. default mode input. shown Port Architecture diagram, direction data flow Port pins also controlled output enable (.oe) product term from GPLD array. product term active, Direction Register sole control direction. example configuration port with three least significant bits output remainder input shown Table Port register only three least significant bits active.
Table Port Direction Assignment Example
ZPSD7XX(V) Family
Ports
(cont.)
Port Registers (cont.) Drive Register
Drive Register configures driver Open Drain, case ECSPLD outputs, sets operate high slew rate. external pull-up resistor required when slew rate mode. Ports register sets different functions lower higher nibbles. four upper bits corresponding bits CMOS ("0") Open Drain ("1") driver. four lower bits used slew rate control. slew rate measurement rise fall times output. higher slew rate means faster output response while lower slew rate slower, lower slope, response. operates high slew rate when corresponding Drive Register "1". Table shows Drive Registers Port which Open Drain Slew Rate configuration.
Table Drive Register Assignment
Drive Register Port Port Port Port Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Open Drain Slew Rate Slew Rate Open Drain Slew Rate Slew Rate Slew Rate Open Drain Slew Rate Slew Rate Slew Rate Open Drain Slew Rate
NOTE: Applicable, should "0".
ZPSD7XX(V) Family
Ports
(cont.)
Port Data Registers
Port Data Registers, shown Table used microcontroller write read data from ports. Table shows register name, ports having each register type microcontroller access each register. registers described below.
Table Port Data Registers Register Name
Data Data Output MicroCell Input MicroCell Enable
Port
A,B,C,D A,B,C,D A,B,C A,B,C A,B,C Write/Read
Access
Read input
Read outputs MicroCells Write loading MicroCells Flip-Flop Read outputs Input MicroCells Read output enable control port driver
Data
Port pins connected directly Data buffer. input mode, input read through Data buffer.
Data Register
Stores output data written output mode. contents Register driven pins Direction Register product term "1". contents register also read back microcontroller.
Output MicroCell
GPLD Output MicroCells occupy location microcontroller's address space. microcontroller read output MicroCells. Writing MicroCell loads data MicroCell Flip-Flops. Refer ZPLD section more detail.
Input MicroCell
Input MicroCells used latch store external inputs. outputs Input MicroCells routed ZPLD input also read microcontroller. Refer ZPLD section detail description.
Enable
Enable buffer allows microcontroller read outputs "OR" gate that enable input port output driver. indicates driver output mode, indicates driver tri-state input mode.
ZPSD7XX(V) Family
Ports
(cont.)
Port Data Registers (cont.) Register Address Offset
base address Registers defined CSIOP equation that occupies bytes address space defined user PSDsoft. lower address byte A[7:0], address offset, selects register. Table shows address offset MCUs except those Motorola microcontrollers with 16-bit data bus. Table shows address offset Motorola MCUs 16-bit mode. example, when CSIOP defined occupy address range 1000h 10FFh PSDabel, address Port Control Register then 1002h.
Table Register Address Offset (relative CSIOP) Register Name
Data Control Data Direction Drive Input MicroCell Enable Output MicroCell
Port
Port
Port
Port
Table 28A. Register Address Offset 16-Bit Motorola Microcontrollers 16-Bit Mode (relative CSIOP) Register Name
Data Control Data Direction Drive Input MicroCell Enable Output MicroCell
Port
Port
Port
Port
ZPSD7XX(V) Family
Ports
(cont.)
Port Functionality Structure
Port have similar functionality structure shown Figure ports configured perform more following functions: Mode GPLD Output MicroCells McellAB[7:4] connected Port PA[7:4} Port PB[7:4]. ECSPLD Output External chip select output connected either Port PA[3:0] Port PB[3:0]. Latched Address output Provide latched address output Table Address Additional high address inputs using Input MicroCells. Open Drain/Slew Rate pins PA[3:0] PB[3:0] configured Open Drain Mode pins PA[7:4] PB[7:4] configured fast slew rate Data Port Port D[7:0} non-multiplexed Port D[15:8] 16-bit non-multiplexed Peripheral Mode Port only
Table Port Latched Address Output Assignments Microcontroller
8051XA (8-Bit) 80C251 (Page Mode) Other 8-Bit Multiplexed 8051XA (16-Bit) Other 16-Bit Multiplexed 8-Bit Non-Multiplexed
Applicable.
Port (3:0)
N/A* Address (3:0) Address (3:0)
Port (7:4)
Address (7:4) Address (7:4) Address (7:4) Address (7:4)
Port (3:0)
Address (11:8) Address (11:8) Address (3:0) Address (11:8) Address (11:8) Address (3:0)
Port (7:4)
Address (15:12) Address (7:4) Address (15:12) Address (15:12) Address (7:4)
INTERNAL DATA
DATA REG. DATA ADDRESS OUTPUT ADDRESS 7:0] A[15:8] PORT MCELL 7:4] ECS[3:0] READ DATA CONTROL REG. REG. ENABLE PRODUCT TERM (.OE) INPUT MICRO CELL ENABLE OUTPUT SELECT
(cont.)
Ports
Figure Port Structure
ZPSD7XX(V) Family
GPLD INPUT
ZPSD7XX(V) Family
Ports
(cont.)
Port Functionality Structure
Port does support Address mode Control Register required. Port configured perform more following functions: Mode GPLD Output McellC outputs connected Port pins GPLD Input eight Input MicroCells Address Additional high address inputs using Input MicroCells. Open Drain Port pins configured Open Drain Mode Supervisory Function Port (PC1 PC6) pins configured perform Supervisory Function. configured input certain microcontroller interface designs.
Port Functionality Structure
Port only three pins, does support Address mode, Control Register required. Port configured perform more following functions: Mode ECSPLD Output External chip select output ZPLD Input direct input ZPLD, Input MicroCells Slew rate pins fast slew rate Port pins configured PSDsoft input pins other dedicated functions: ALE, address strobe input CLKIN, clock input MicroCells Flip-Flops counter CSI, active chip select input. high input will disable EPROM/SRAM.
INTERNAL DATA
SUPERVISORY FUNCTION DATA REG. DATA PORT OUTPUT MCELL 7:0] READ
(cont.)
Ports
Figure Port Structure
ZPSD7XX(V) Family
DATA
OUTPUT SELECT
ENABLE
REG. ENABLE PRODUCT TERM (.OE) INPUT MICRO CELL GPLD-INPUT
(cont.)
Ports
DATA REG. DATA PORT OUTPUT ECS[ 6:4] READ
Figure Port Structure
DATA
INTERNAL DATA
OUTPUT SELECT
REG. GPLD-INPUT
ZPSD7XX(V) Family
ZPSD7XX(V) Family
ZPSD7XX(V) internal EPROM SRAM memory blocks. memory select signals come from DPLD user-defined PSDsoft Software.
Memory Blocks
EPROM
ZPSD7XX(V) provides three EPROM densities: 256K bit, 512K bit. EPROM divided into eight blocks. EPROM configured 128K eight-bit data busses 16-bit data buses. Each block EPROM select. Blocks zero have select (ES0-ES6) block selects, ES7A ES7B, either which enables Block dual selects allow Block reside separate memory spaces. typical application would store reset vector residing memory space accessed ES7B. rest Block memory space would accessed ES7A. same technique also used store Configuration bytes Intel 80251 microcontroller which reside high memory space.
SRAM
SRAM bits memory that configured SRAM enabled from output DPLD. SRAM battery back-up mode which automatically invoked when supply voltage drops under standby voltage. SRAM write protection provided back-up mode.
Memory Select
EPROM SRAM select outputs from DPLD whose equations defined using PSDabel. following rules apply memory space definitions: EPROM block select space should larger than physical block size EPROM block select space must overlap SRAM, Peripheral spaces cannot overlap SRAM, Peripheral spaces overlap EPROM with priority given SRAM I/O. This allows SRAM utilize EPROM space that used.
ZPSD7XX(V) Family
Memory Blocks
(cont.)
Page Register
four-bit Page Register increases addressing capability microcontroller factor contents Register also read microcontroller. outputs Page Register (PGR0-PGR3) inputs ZPLD included EPROM SRAM chip select equations. Figure shows Page Register. four Flip-Flops Register connected internal data microcontroller write read from Page Register. Register operate independent register microcontroller page mode implemented.
Figure Page Register Memory Bank Switching
RESET
PGR0 PGR1 PGR2 PGR3 GPLD ECSPLD ZPLD DPLD
PAGE REG.
Security Protection
ZPSD7XX(V) programmable security which acts duplication barrier. When set, contents EPROM, non-volatile configuration bits, ZPLD cannot read device programmers. security through PSDsoft Design Tools embedded compiled output file. security erasable secured ZPSD7XX(V) windowed package erased re-programmed.
ZPSD7XX(V) Family
Memory Blocks
(cont.)
Memory Select 8031 Microcontrollers
8031 family microcontrollers, including 80C251 80C51XA, separate address space code memory (enabled PSEN) data memory (enabled RD). ZPSD7XX(V) allows EPROM SRAM reside program space, data space both. Three different configurations possible:
Separate Space Mode
Code memory space separated from data memory space. PSEN signal used access program code from EPROM, signal used access data from SRAM Ports. This default configuration.
Combined Space Mode
program data memory spaces combined into 64KB block space that allows EPROM SRAM accessed either PSEN EPROM SRAM blocks address space must overlap. This mode enabled microcontroller setting bits Register shown Table "1", either PSEN access SRAM. "1", either PSEN access EPROM. Figure shows memory select logic Combined Space Mode.
Mixed Mode
Allows individual EPROM blocks configured either Data Space Program Space. EPROM block chip selects must qualified with 8031 input -ES7 equations. active will select EPROM blocks data space disable blocks that program space. EPROM blocks that reside data space, access time calculated from valid data valid. This mode automatically PSDsoft whenever signal included EPROM chip select equations.
Table Register
PIO_EN disable mode enable mode *Bit used, "0".
Bits after reset.
RD_EN access SRAM, access EPROM, SRAM,
PSEN_EN PSEN access EPROM only PSEN access EPROM, SRAM,
ZPSD7XX(V) Family
Memory Blocks
(cont.)
Figure 8031 Memory Modes Separate Space Mode
EPROM ES0-ES7 DPLD
SRAM
PSEN
Figure 80C31 Memory Mode Combined Space Mode
DPLD
ES0-ES7
EPROM
SRAM
PSEN
ZPSD7XX(V) Family
ZPSD7XX(V) offers number configurable power saving options which include Automatic Power Down (APD) Logic Power Management Mode Registers (PMMR0 PMMR1). Logic allows ZPSD7XX(V) enter into either Power Down Sleep Mode automatically, while PMMRs configured time microcontroller selectively reduce power consumption functional blocks.
Power Management Unit
Logic Power Down Mode
Automatic Power Down (APD) logic puts ZPSD7XX(V) into power savings mode monitoring activity address strobe (ALE/AS). unit enabled, four-bit counter starts counting whenever address strobe inactive. strobe remains inactive fifteen CLKIN clock periods, power down (PDN) signal will become active ZPSD7XX(V) enter into either Power Down Sleep Mode. Immediately after starts pulsing ZPSD7XX(V) will return normal operation. counter clock source comes from CLKIN which Port Superv_Clk from Supervisory Function. order guarantee that counter will overflow when enabled, there should less than clocks between successive pulses. Usually, microcontrollers entering power down mode will freeze their logic high level. programming PMMR0, knows when power down mode. detects level power down state CLKIN periods, then ZPSD7XX(V) will enter power down mode. enable operation, PMMR0 should "1". When address strobe starts pulsing again, input switches from high low, ZPSD7XX(V) will return normal activity. When signal (active state) Power Down Sleep Mode), ZPSD7XX(V) interface disabled inputs (address, data control signals) blocked from entering device. clock input ZPLD needed Power Down mode, should blocked save power setting PMMR0 "1".
Sleep Mode
Sleep Mode activated Sleep mode bit, Polarity PMMRs set, Counter overflowed after CLKIN clocks (see Figure 29). Sleep Mode ZPSD7XX(V) consumes less power than Power Down Mode, with typical reduced 10µA. this mode, ZPLD still monitors inputs responds them. soon starts pulsing input switches from high low, ZPSD7XX(V) exits Sleep Mode. ZPSD7XX(V) access time from Sleep Mode specified tLVDV1. response time input transition specified tLVDV2.
Table Power Down Effect Ports Port Function
ZPLD Address Data Port Peripheral
Level
Change Change Undefined Three-State Three-State
ZPSD7XX(V) Family
Power Management Unit
(cont.)
Table Summary ZPSD7XX(V) Timing Standby Current During Power Down Sleep Mode
ZPLD Propagation Delay
Normal (Note tLVDV2 (Note
Mode
Power Down Sleep
ZPLD Recovery Time Normal Operation
tLVDV3 (Note
Access Time
Access Access
Access Recovery Time Normal Access
tLVDV tLVDV1
Typical Standby Current
25µA (Note 10µA (Note
NOTES: Power Down does affect operation ZPLD. ZPLD operation this mode based only ZPLD Turbo bit. Sleep Mode input will have propagation delay tLVDV2. recovery time normal operation after existing Sleep Mode. input during transition will have propagation delay tLVDV3. Typical current consumption assuming CLKIN disabled ZPLD Turbo OFF. Typical current consumption assuming CLKIN disabled.
Figure Logic Block
PMMR0 POLARITY PMMR0 CLEAR LOGIC
SLEEP-EN PMMR1
SLEEP MODE EPROM SELECT
COUNTER EDGE DETECT POWER DOWN (PD) ZPLD SRAM SELECT
CLKIN
SELECT DISABLE EPROM/SRAM DISABLE INTERFACE
ZPSD7XX(V) Family
Power Management Unit
(cont.)
Figure Enable Power Down Flow Chart
RESET
DISABLED
POLARITY PMMR0
NEED SLEEP MODE
ENABLE SLEEP MODE PMMR1
ENABLE PMMR0
ENABLE PMMR0
DISABLE CLKIN PMMR0
DISABLE CLKIN PMMR0
IDLE CLKIN CLOCK ZPSD7XX(V) POWER DOWN MODE
IDLE CLKIN CLOCK ZPSD7XX(V) SLEEP MODE
ZPSD7XX(V) Family
Power Management Unit
(cont.)
Table Power Management Mode Registers (PMMR0, PMMR1)**
PMMR0
Superv ZPLD Mcell ZPLD Array ZPLD Turbo CMiser Enable Polarity high
**Bit used, should **Both PMMR0 PMMR1 register bits clear zero following power
Subsequent reset pulses will clear registers.
power down polarity power down polarity high Automatic Power Down (APD) disabled Automatic Power Down (APD) enabled EPROM/SRAM CMiser EPROM/SRAM CMiser ZPLD Turbo ZPLD Turbo CLKIN input ZPLD array connected Every CLKIN change will power ZPLD when Turbo CLKIN input ZPLD array disconnected CLKIN input ZPLD MicroCells connected CLKIN input ZPLD MicroCells disconnected Supervisory Clock input GPLD connected Supervisory Clock input GPLD disconnected
PMMR1
Sleep Mode Enable *Unused bits should Supervisory Clock serves clock CLKIN serves clock Sleep Mode Disabled Sleep Mode Enabled Source CLKIN
Table Counter Operation Enable
Polarity
Level
Pulsing Counting Counting
Counter
Counting (Generates after Clocks) Counting (Generates after Clocks)
ZPSD7XX(V) Family
Power Management Unit
(cont.)
Other Power Saving Options
ZPSD7XX(V) offers other reduced power saving options that independent Power Down Sleep Mode. Except SRAM Standby input features, they enabled setting bits PMMR register.
CMiser
CMiser resides PMMR0. This controls power consumption access time EPROM SRAM. When data mode CMiser set, ZPSD7XX(V) will consume lowest level power. However, access time will slower (see CMiser adder timing parameters). When CMiser off, power higher ZPSD7XX(V) will return standard access time.
SRAM Standby Mode
SRAM Vstby (PC2) that connected battery. When becomes lower than Vstby then ZPSD7XX(V) will automatically connect Vstby power source SRAM. SRAM Standby Current (Istby) typically 0.5µA. SRAM data retention voltage minimum.
Input
Port configured PSDsoft input When low, signal selects enables internal EPROM SRAM read write operations. high will disable EPROM SRAM reduce power consumption. However, ZPLD remains operational when high.
Zero Power ZPLD
power speed ZPLD controlled Turbo (bit PMMR0. After reset ZPLD Turbo mode runs full power speed. setting one, Turbo mode disabled ZPLD consumes Zero Power current inputs switching time propagation delay time will increased 10ns after Turbo (turned off) inputs change frequency less than 15MHz. Turbo CMiser independent each other. Turbo controls only ZPLD power propagation delay. CMiser affects EPROM SRAM power access time only.
Input Clock
ZPSD7XX(V) provides option turn CLKIN Supervisory Clock input ZPLD save power consumption. CLKIN input ZPLD array Output MicroCells. During power down CLKIN input being used part ZPLD logic equation, clock should disabled save power. CLKIN will disconnected from ZPLD array MicroCells setting PMMR0.
ZPSD7XX(V) Family
Supervisory Function ZPSD7XX(V) significantly improves microcontroller system reliability with programmable features such power supply monitoring, reset control WatchDog Timer. These features are: power supply monitoring Reset generation based various conditions: Power-On reset; voltage comparator with programmable internal external trip point Push Button System reset input WatchDog Timer output User programmable WatchDog Timer (controlled PPLD product terms). Battery-backup internal SRAM. Write protect internal SRAM external memory. Reset input debouncer filter. Programmable reset pulse width generator Figure block diagram Supervisory Function. input output supervisory pins listed Table Pins that used configured other ZPSD7XX(V) functions. Table shows inputs outputs PPLD that involved controlling Supervisory Function.
Supervisory Function
Table Supervisory Pins Input Name
VSTBY (PC2)
Output Name
VSTBYON (PC4)
Description
SRAM Battery Backup input
Description
driven high when ZPSD7XX(V) switched over Standby Voltage Chip select output that used external non-volatile writable memory. This chip select becomes inactive automatically when ZPSD7XX(V) switched standby voltage. conserve power external battery backup SRAM prevent unwanted writes external EEPROM, SRAM, FLASH. Active high reset output Active reset output
VTRIP (PC6)
External Trip voltage input voltage comparator
CEOUT (PC3)
RESET CLKIN (PD1)
System push button reset input External clock input
RST_OUT (PC5) RST_OUT (PC1)
ZPSD7XX(V) Family
Supervisory Function
(cont.)
Table PPLD Supervisory Signals Input Signals
GRESET ERESET
Description
Reset generated WatchDog Timer, Voltage Comparator Reset input. ERESET output Pulse Generator that triggered GRESET. GRESET ERESET active signal.
Output Signals
WDOG_EN
Description
product term that enables WatchDog Timer. active high pulse minimum 20ns duration.
WDOG_ON
Active high WatchDog output. Will remain active until WatchDog cleared WDOG_CLR. Other GPLD inputs, refer GPLD chapter. clock generated Supervisory Function. WatchDog Timer runs internal oscillator, SUPERV_CLK connected 2KHz oscillator. Otherwise SUPERV_CLK connected external CLKIN/8192.
WDOG_CLR
product term that clears re-loads WatchDog Timer. active high pulse minimum 20ns duration.
GPLD Inputs
SUPERV_CLK
ZPSD7XX(V) Family (cont.)
Supervisory Function
Figure Supervisory Function Block Diagram
ON-CHIP SRAM (ONLY)
VSTBY SELECT
VSTBYON
VSTBYON
(GPLD) MCELLC3 CEOUT CONTROL
CEOUT
EXT.VTP 1.29V BANDGAP DIGITAL SAMPLER
RESET 32KHz
PROGRAMMABLE PULSE GENERATOR
RST-OUT
VTP- DEBOUNCER STATUS REGISTER
RST-OUT
EMBEDDED 2KHz
GRESET CLKIN CLOCK DIVISOR WDOG
ERESET
EXT-
WDOG
SUPERV- ZPLD INPUTS PPLD WDOG WDOG PROGRAMABLE WATCHDOG TIMER
WDOG -CLR
WDOG GRESET ERESET
ZPSD7XX(V) Family
Supervisory Function
(cont.)
Reset Generation
ZPSD7XX(V) generate output reset signals that external peripherals microcontroller. Three sources capable issuing reset:
Power-On reset; voltage comparator with programmable internal external trip point. Push button system reset input from pin. WatchDog Timer timeout output when enabled
microcontroller read ZPSD7XX(V) Status Register determine source reset. internal global reset (GRESET) brought pins Port active high output. width extended reset output (ERESET) pulse user configurable controlled Programmable Pulse Generator. Either GRESET ERESET (active high) declared internal node PSDabel participate logic equation definition.
Push Button Reset Input
ZPSD7XX(V) dedicated active-low reset input that connected system reset push button reset. system reset direct input reset generator, while Push Button input routed through selectable debouncer filter that filters transitions shorter than three clock cycles. clock source this debouncer either 125Hz internal oscillator CLKIN/128K. Figure shows reset input timing requirement. active range minimum tNLNH duration. After rising edge reset, ZPSD7XX(V) remains reset state during tOPR range. Table shows status ZPSD7XX(V) during reset power down mode.
Table Status During Reset Power Down Mode Port Configuration
ZPLD Output Address Data Port Peripheral Input Active Tri-stated Tri-stated Tri-stated
Reset
Power Down Mode
Unchanged Depends inputs ZPLD defined Tri-stated Tri-stated
Register
PMMR0
Reset
Cleared (power reset) Unchanged (warm reset)
Power Down Mode
Unchanged
MicroCell Flip-Flop other registers
Unchanged* Cleared
Unchanged* Unchanged
*The MicroCell flip-flop cleared reset input (Power Down) signal, depending
equations that defined PSDabel file.
ZPSD7XX(V) Family
Supervisory Function
(cont.)
Power Monitor
Power Monitor circuitry monitors supply generates reset pulse whenever drops below selected reference voltage. Voltage Comparator compares either with internally generated reference voltage with external reference voltage applied (PC6) pin. voltage comparator output applied directly reset generator through 100-microsecond digital sampler. digital sampler acts filter eliminate false trips that created noises. digital sampler runs internal 32KHz oscillator, masking Voltage Comparator output that less than oscillator clock cycles duration. external voltage reference selected, external resistor voltage divider used provide desired voltage input level that compared with internal bandgap reference voltage 1.29V. voltage divider shown Figure where Vmon connected monitored supply. typical application would Vmon 4.75V. value calculated follows: Vmon R2)) (4.75V 10K)/1.29V 26.8K internal reset generated when Vmon drops below 4.75V.
Figure Voltage Divider Circuit
RST- VSTBY CEOUT VSTBYON RST-
ZPSD7XX(V)
ZPSD7XX(V) Family
Supervisory Function
(cont.)
Power Monitor (cont.)
configuration options Voltage Comparator provided PSDsoft Design Tool are:
Reference voltage source Internal reference voltage level Digital Sampler Voltage Comparator disable
internal level selections shown Table power supply tolerances available: 10%. Depending selected power supply option, fixed value provided.
Table Internal Selection Range Intended Selectable Operating Supply Voltage Tolerance
3.3V 2.7V 3.3V 3.3V
Device
ZPSD7XXS5 ZPSD7XXS3V ZPSD7XXS2V
Min.
4.47 4.08 2.94 2.69 2.68 2.45
Typ.
4.61 4.29 3.03 2.83 2.76 2.57
Max.
4.75 4.50 3.12 2.97 2.84 2.70
Accuracy
Programmable Watchdog Timer
WatchDog Timer consists retriggerable counter. Once enabled, starts counting down from initial value that specified user PSDSoft Design Tool. WatchDog timeout generated when count reaches zero. timeout output connected PPLD internal reset pulse generator. WatchDog Timer enabled controlled internal reset PPLD outputs:
Internal Reset
WatchDog Timer starts count immediately after trailing edge extended reset (ERESET) pulse enabled PSDsoft design tool.
PPLD Outputs
WDOG_EN WDOG_EN signal defined PSDabel, Watchdog Timer starts counting only after WDOG_EN generates high pulse. This signal defined terms microcontroller address write signal. Writing this address microcontroller will enable Watchdog Timer. WDOG_EN signals activated only after extended reset (ERESET) expires. WDOG_CLR This PPLD output signal re-loads re-triggers Watchdog Timer. This signal used clear WatchDog before timeout reached, defined terms microcontroller address write signal. Writing this address microcontroller will clear WatchDog.
ZPSD7XX(V) Family
Supervisory Function
(cont.)
Watchdog Timeout Output
Once enabled, Watchdog Timer counts down using selected clock rate. re-loaded PPLD output WDOG_CLR internal reset. WatchDog re-loaded time period specified PSDsoft Design Tool, WatchDog times generates WDOG_RST signal Reset Generator WDOG_ON PPLD. WDOG_ON signal used GPLD output generate interrupt microcontroller. WDOG_RST signal create internal reset pulse activate RST_OUT pins. pulse width RST_OUT WDOG_ON output controlled Pulse Generator.
Watchdog Timer Power-Down Mode
When ZPSD7XX(V) enters into power down mode, WatchDog Timer continues count operation affected. RST_OUT PPLD still fully functional. ZPSD7XX(V) consumes considerably less power power-down mode internal oscillator selected WatchDog clock source instead CLKIN.
Battery Backup
(VSTBY) input external battery backup voltage onboard SRAM. falls below value VSTBY, automatic internal power switchover occurs which connects external battery power onboard SRAM. minimum SRAM data retention voltage 2.0V standby current typically 0.5µA. switchover, (CEOUT) chip select automatically forced inactive (VSTBYON) driven active. CEOUT defined PSDsoft chip select external battery backup SRAM, FLASH, EEPROM. During normal operation, CEOUT driven directly output MicroCell (Mcell3) select deselect memory device. battery backup mode, CEOUT driven high automatically deselect memory device. This ensures minimal power consumption (external battery backup SRAM) protects against inadvertent writes during standby mode. VSTBYON external indication that switched standby power mode. used designer's discretion.
ZPSD7XX(V) Family
Supervisory Function
(cont.)
Figure Supervisory Functions
ZPSD7XX(V)
RESET RST-OUT VSTBY CEOUT BATTERY SRAM BACKUP
RESET
N.O. MOMENTARY
VSTBY RST-OUT 1.29V WHEN 4.75V
26.8K
TYPICAL MICROCONTROLLER
NON-VOLATILE WRITABLE MEMORY (BATTERY BACKED SRAM, FLASH, EEPROM, etc.)
*Reset signal active WatchDog
timeout, drop, pushbutton activation.
figure above shows optional usage supervisory functions. These features included this diagram: reset input debounce, external trip voltage configuration, external nonvolatile writable memory, external standby power source.
Clock Source Frequency Selection
With exception Digital Sampler which dedicated 32KHz internal oscillator, other Supervisory circuitry either 2KHz internal oscillator external CLKIN input. Table shows available clock sources clock inputs different circuitry. Based selected clock source, PSDsoft Design Tool provides user with programmable WatchDog timeout periods reset pulse widths.
Table Clock Sources Reset Debouncer Clock Frequency
Internal Oscillator 2KHz External Clock CLKIN 2KHz/16
Clock Source
WatchDog Timer Clock Timeout Frequency Periods
2KHz 2KHz/256 From 0.5ms 63.875s (0.5ms increment) Depends CLKIN Frequency
Pulse Generator Clock Pulse Width Frequency (ms)
2KHz/2 8,16,32,64, 128,256,512
CLKIN/128K
CLKIN/8K CLKIN/2M
CLKIN/16K
Depends CLKIN Frequency
ZPSD7XX(V) Family
Supervisory Function
(cont.)
Status Register
ZPSD7XX(V) able generate reset microcontroller from three different sources: WatchDog Timer, Voltage Comparator Push Button reset input. order determine which source causes reset, microcontroller needs read Status Register. After source reset identified, microcontroller writes Reset_Clr Register clear reset bits Status Register.
Table
Status Register Address :CSIOP :CSIOP (Motorola bit) Vext_en Vtp2 Vtp1 Vtp0 Wdog RST_IN
definitions:
above Reset pulse generated when level dropped below Vtp. RST_IN RSTIN driven high. Reset pulse generated when RSTIN been driven low. Wdog WatchDog reset occurred. Reset pulse generated when WatchDog Timer expired Vtp<2:0> Indicates selected internal threshold voltage reference level. reset issued whenver stays below selected reference level. 0,0,0 Vtpref 4.61v 0,0,1 Vtpref 2.57v 0,1,0 Vtpref 2.76v 0,1,1 Vtpref 2.83v 1,0,0 Vtpref 3.03v 1,0,1 Vtpref used 1,1,0 Vtpref 4.29v 1,1,1 Vtpref trip point. Vext_en: Select internal reference level from above table. Enable serve external input pin. reset issued whenever stays below reference voltage level. Reset_Clr Register Address :CSIOP :CSIOP (Motorola bit) Writing this register clears reset bits Status Register.
ZPSD7XX(V) Family
Supervisory Function
(cont.)
Supervisory Diagnostic Registers
Supervisory Function four read-only registers that provide additional Supervisory WatchDog Timer status debugging purposes. contents registers described following tables.
Sup-Pins (read only)
Cen_resf
CEout
Stby
RST_En
Deb_En
Vstby_on Cresb Cresb
Deb_En RSTIN RSTIN RST_En serves active-high reset output. doesn't serve active-high reset output. Cresb<1:0> serves active-low, CMOS reset output. serves active-low, open-drain reset output. doesn't serve active-low reset output. Reserved input filter. using debounce filter.
Vstby_on serves battery backup mode indicator (high when Vstby Vcc). used battery backup indicator. VStby serves battery backup input. used battery backup input. Ceout serves external memory select, backed-up battery input. used battery-backed, external memory select. Cen_resf Bypass reset digital sampler. reset using digital sampler.
ZPSD7XX(V) Family
Supervisory Function
(cont.)
WDRST_Stat (read only)
RST_On
Crst2pld
Wdog_ enable
Wdck
Wdog
Wd2_
Wpt_
Wpt_pwr WatchDog enabled En_Wdog only. Watchdog starts counting following reset. Wd2_res WatchDog can't issue reset pulse. WatchDog issues reset pulse upon completion count. Wdog_on WatchDog count hasn't expired. WatchDog count expired. En_WdCk WatchDog counter disabled. WatchDog counter enabled. Wdog_enable En_Wdog hasn't been activated yet. En_Wdog already been activated, WatchDog enabled. Crst2pld GRESET serves reset input GPLD. ERESET serves reset input GPLD. RST_On Reset active. extended Reset pulse
ZPSD7XX(V) Family
Supervisory Function
(cont.)
WD-timeout1 (read only)
WdTmo<7>
WdTmo<6>
WdTmo<5>
WdTmo<4>
WdTmo<3>
WdTmo<2>
WdTmo<1>
WdTmo<0>
WDRST-Var (read only)
Wclk_ src<1>
Wclk_ src<0>
WdTmo<8>
WD_Rst<2> Wd_Rst<1> Wd_Rst<0>
WdTmo<8:0> Current WatchDog count. Must read twice. Only when fetch identical count-values, count correct. WdTmo<8> most significant bit, WdTmo<0> least significant bit. Wclk_src<1:0> Determines WatchDog clock source. Embedded 2KHz oscillator. Embedded oscillator. CLKin frequency 8192 CLKin 8K). CLKin frequency 2,097,152 (CLKin 2M).
successive reads
Wd_Rst<2:0> Defines WatchDog 0,0,0 0,0,1 0,1,0 0,1,1 1,0,0 1,0,1 1,1,0 1,1,1 0,0,0 0,0,1 0,1,0 0,1,1 1,0,0 1,0,1 1,1,0 1,1,1 pulse length reset pulse extension.
With Wclk_src<1> 1024 1sec)
With Wclk_src<1>
{1024
[16384 [16384 [16384 [16384 [16384 [16384 [16384 [16384
/CLKin(hz)]} /CLKin(hz)]} /CLKin(hz)]} /CLKin(hz)]} /CLKin(hz)]} /CLKin(hz)]} /CLKin(hz)]} /CLKin(hz)]}
NOTE: Supervisory functions have control/configuration registers that accessible during run-time. Supervisory function control/configuration done using PSDsoft.
ZPSD7XX(V) Family
Absolute Maximum Ratings
Symbol
TSTG
Parameter
Storage Temperature Operating Temperature Voltage
Condition
CLDCC PLDCC Commercial Industrial With Respect With Respect With Respect
Unit
Programming Supply Voltage Supply Voltage Protection
>2000
NOTE: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods time affect device reliability.
Operating Range
Range
Commercial Industrial Commercial Industrial
Temperature
+70°C -40° +85°C +70°C -40° +85°C
Tolerance
Recommended Operating Conditions
Symbol
Parameter
Supply Voltage Supply Voltage
Condition
Speeds V-Versions Speeds
Unit
ZPSD7XX(V) Family
following tables describe AD/DC parameters ZPSD7XX(V) family:
AC/DC Parameters
Electrical Specification Timing Specification
ZPLD Timing
Combinatorial Timing Synchronous Clock Mode Asynchronous Clock Mode Input MicroCell Timing Microcontroller Timing Read Timing Write Timing Peripheral Mode Timing Power Down Reset Timing
Following some issues concerning parameters presented:
specification Supply Current given different modes operation.
Before calculating total power consumption, determine percentage time that ZPSD7XX(V) each mode. Also supply power considerably different ZPLD_TURBO "OFF" EPROM_CMISER "ON".
power component gives ZPLD, EPROM, SRAM mA/MHz specification.
Figures show ZPLD mA/MHz function number Product Terms (PT) used.
ZPLD timing parameters required delay when ZPLD_TURBO "OFF". timing specification required time delay when EPROM_CMISER
"ON".
Figure ZPLD /Frequency Consumption
(VCC 10%)
(mA)
PT100% PT25%
HIGHEST FREQUENCY INPUTS (MHz)
ZPSD7XX(V) Family
Figure 34A. ZPLD /Frequency Consumption
(ZPSD7XX(V) Versions, 10%)
(mA)
PT100% PT25%
HIGHEST FREQUENCY INPUTS (MHz)
Typical Power Calculation
Example ZPSD7XX Typical Power Calculation Conditions
Highest input frequency (Freq PLD) frequency (Freq ALE) EPROM Access SRAM access access Operational Modes Normal Sleep Number product terms used (from fitter report) total product terms Turbo CMiser 8-bit mode additional power above base) 32/129 24.8%
Calculation (typical numbers used)
total Isleep %sleep %normal (ICC (ac) (dc)) Isleep %sleep normal (%EPROM mA/MHz Freq %SRAM mA/MHz Freq %PLD (from graph using Freq PLD)) 0.90 (0.8 mA/MHz 0.15 mA/MHz 0.95 22.5 (2.56 0.84 20.9) 22.5 24.3 22.5 2.43 2.45 Standby current consumption handled similarly sleep mode shown above.
ZPSD7XX(V) Family
Versions)
Characteristics
Symbol
VIH1 VIH2 VIL1 VHYS
Parameter
Supply Voltage High Level Input Voltage Level Input Voltage Reset High Level Input Voltage Reset Level Input Voltage Reset Hysteresis (Note
Conditions
Speeds (Note
-0.5 4.47 4.08 2.94 2.69 2.68 2.45
Unit
Vtp(2:0) Vtp(2:0) 3.3V, Vtp(2:0) Power Supply Trip Point 3.3V, Vtp(2:0) 2.7V, Vtp(2:0) 2.7V, Vtp(2:0) Vtp(2:0) Power Reset VETP VOH1 VSBY ISBY IIDLE (DC) (Note External Trip Point (PC6) Output Voltage Output High Voltage Except VSTBYON, CEOUT
4.61 4.29 3.03 2.83 2.76 2.57
4.75 4.50 3.12 2.97 2.84 2.70
1.23
1.29 0.01 0.15
1.35 0.45
4.49 VSBY -0.5
Output High Voltage VSTBYON, CEOUT IOH1 SRAM Standby Voltage SRAM Standby Current Idle Current (VSTBY Pin) SRAM Data Retention Voltage Standby Supply Current Power Down Mode Sleep Mode VSBY Only VSTBY >VCC (Note >VCC (Note ZPLD_TURBO OFF, (Note ZPLD_TURBO CMiser 8-Bit Mode Other Cases CMiser 8-Bit Mode SRAM Adder CMiser 16-Bit Mode CMiser -0.1
Figure
Input Leakage Current Output Leakage Current Operating Supply Current ZPLD Base
ZPLD Only
µA/PT Figure
mA/MHz mA/MHz mA/MHz mA/MHz mA/MHz
EPROM Adder (AC) (Note
NOTES:
Reset input hysteresis. VIL1 valid below .2VCC -.1. VIH1 valid above .8VCC. deselected internal active. Sleep mode internal active. ZPLD ICC/Frequency Power Consumption graph details. IOUT
ZPSD7XX(V) AC/DC Parameters GPLD ECSPLD Timing
Versions)
GPLD ECSPLD Combinatorial Timing 10%)
Parameter
ECSPLD Input ECSPLD Combinatorial Output (Notes (Note (Note GPLD Input Pin/Feedback GPLD Combinatorial Output Port GPLD Input Pin/Feedback GPLD Combinatorial Output Port GPLD Input ECSPLD Output Enable (Notes (Notes (Notes (Notes (Notes (Notes Microcell GPLD Input GPLD Output Enable GPLD Input ECSPLD Output Disable GPLD Input GPLD Output Disable GPLD Register Clear Preset Delay GPLD Register Clear Preset Pulse Width GPLD Array Delay
-90**
Symbol
Conditions
Aloc
Slew Rate
Unit
ARPW
NOTES:
ECSPLD Input pins A(0:15), PGR(0:3), CNTL(0:2), PDN. ECSPLD Outputs PA(0:3), PB(0:3), PD(0:2). GPLD Inputs A(0:15), PGR(0:3), CNTL(0:2), PA(0:7), PB(0:7), PC(0:7), PD(0:2), ALE, PDN, RESET, WDOG_ON WCLK. GPLD Outputs PA(4:7), PB(4:7), PC(0:7).
ZPSD7XX(V) Family
**-90 speed available only Industrial Operating Temperature Range product.
ZPSD7XX(V) AC/DC Parameters GPLD ECSPLD Timing
Versions)
ZPSD7XX(V) Family
GPLD MicroCell Synchronous Clock Mode Timing 10%)
Parameter
Maximum Frequency External Feedback 1/(t 1/(t -10) 43.48 50.00 1/(t (Notes (Notes Clock Input Clock Input Clock Input Microcell 37.04 41.67 Add2 30.30 27.03 Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data Input Setup Time Input Hold Time Clock High Time Clock Time Clock Output Delay GPLD Array Delay Minimum Clock Period
-90**
25.00 31.25 35.71
Aloc Slew Rate Unit
Symbol
Conditions
fMAX
NOTE: GPLD Inputs A(0:15), PGR(0:3), CNTL(0:2), PA(0:7), PB(0:7), PC(0:7), PD(0:2), ALE, PDN, Reset, WDOG_ON, WCLK. CLKIN tCLCL tCL.
**-90 speed available only Industrial Operating Temperature Range product.
ZPSD7XX(V) AC/DC Parameters GPLD ECSPLD Timing
Versions)
GPLD MicroCell Asynchronous Clock Mode Timing 10%)
Parameter
Maximum Frequency External Feedback 1/(t COA) 1/(t -10) 1/(t (Note (Note (Note (Note (Note Microcell CNTA 41.67 35.71 26.32 25.00 33.33 41.67 Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data Input Setup Time Input Hold Time Clock Input High Time Clock Input Time Clock Output Delay GPLD Array Delay Minimum Clock Period
-90**
21.74 27.78 35.71
Symbol
Conditions
Aloc
Slew Rate
Unit
fMAXA
ARDA
MINA
NOTE: GPLD Inputs A(0:15), PGR(0:3), CNTL(0:2), PA(0:7), PB(0:7), PC(0:7), PD(0:2), ALE, PDN, Reset, WDOG_ON, WCLK. CLKIN tCLCL tCL.
**-90 speed available only Industrial Operating Temperature Range product.
ZPSD7XX(V) Family
ZPSD7XX(V) AC/DC Parameters GPLD ECSPLD Timing
Versions)
ZPSD7XX(V) Family
Input MicroCell Timing 10%)
Symbol
Input Combinatorial Delay (Note Input Time (Note Input High Time (Note Input Hold Time (Note Input Setup Time (Note
-90**
Aloc Unit
Parameter
Conditions
NOTE: Inputs from Port relative register/latch clock from PLD. latch timings refer tAVLX tLXAX.
**-90 speed available only Industrial Operating Temperature Range product.
ZPSD7XX(V) Family
Microcontroller Interface AC/DC Parameters
Versions)
Explanation Symbols Timing. Example:
AVLX Time from Address Valid Invalid.
Signal Letters
Address Input CEout Output Input Data Input Internal WDOG_ON signal Interrupt Input Input Reset Input Output Port Signal Output Output Data UDS, LDS, IORD, PSEN Inputs Chip Select Input Input Internal Signal Vstby Output Output MicroCell
Signal Behavior
Time Logic Level Logic Level High Valid Longer Valid Logic Level Float Pulse Width
Microcontroller Interface AC/DC Parameters
Versions)
ZPSD7XX(V) Family
Read Timing 10%)
Parameter
Pulse Width Address Setup Time Address Hold Time Address Valid Data Valid Valid Data Valid Data Valid 8/16-Bit Data Valid 8-Bit Bus, 8031, 80251 Separate Mode (Note (Note (Note (Note 16-Bit Mode (Note 8-Bit Mode (Note Data Hold Time Pulse Width Data High-Z Pulse Width Setup Time Enable Hold Time After Enable Address Input Valid Address Output Delay (Note (Note (Note (Note
-90**
Symbol
Conditions
CMiser
Unit
LVLX
AVLX
LXAX
AVQV
SLQV
RLQV
RHQX
RLRH
RHQZ
EHEL
THEH
ELTL
AVPV
NOTES:
timing same timing LDS, UDS, PSEN 8031 combined mode) signals. PSEN have same timing 8031 separate mode. input used select internal ZPSD7XX(V) function. multiplexed mode latched address generated from ADIO delay address output Port.
**-90 speed available only Industrial Operating Temperature Range product.
Microcontroller Interface AC/DC Parameters
Versions)
Write Timing 10%)
Parameter
Pulse Width Address Setup Time Address Hold Time Address Valid Leading Edge (Notes (Note (Note (Note (Note (Note (Note (Notes (Notes 16-Bit Mode (Note 8-Bit Mode (Note Valid Leading Edge Data Setup Time Data Hold Time Pulse Width Trailing Edge Address Invalid Trailing Edge Port Output Valid Using Port Data Register Valid Port Output Valid Using MicroCell Register Preset /Clear Data Valid Port Output Valid Using MicroCell Register Preset /Clear Address Input Valid Address Output Delay (Note (Note
-90**
Unit
Symbol
LVLX AVLX LXAX AVWL SLWL DVWH WHDX WLWH WHAX WHPV WHMV DVMV
Conditions
AVPV
ZPSD7XX(V) Family
NOTE: timing same timing LDS, UDS, WRL, signals. Assuming data stable before active write signal. Assuming write active before data becomes valid.
**-90 speed available only Industrial Operating Temperature Range product.
Microcontroller Interface AC/DC Parameters
Versions)
ZPSD7XX(V) Family
Port Peripheral Data Mode Read Timing 10%)
Symbol
AVQV (PA) SLQV (PA) Data Valid RLQV (PA) Data Valid 8031 Mode Data Data Valid Data Hold Time Pulse Width Data High-Z (Note (Note (Note DVQV (PA) QXRH (PA) RLRH (PA) RHQZ (PA) (Notes Valid Data Valid Address Valid Data Valid (Note
-90**
Parameter
Conditions
Unit
Port Peripheral Data Mode Write Timing 10%)
Symbol
WLQV (PA)
-90**
Conditions
(Note (Note (Note
Parameter
Data Propagation Delay Data Port Data Propagation Delay Invalid Port Tri-State
Unit
DVQV (PA) WHQZ (PA)
NOTES: input used select Port Data Peripheral Mode. Data already stable Port Data stable ADIO pins data Port
**-90 speed available only Industrial Operating Temperature Range product.
Microcontroller Interface AC/DC Parameters
Versions)
Power Down Timing 10%)
Symbol
LVDV LVDV1 GPLD FPLD Recovery Time After Sleep Mode Using CLKIN Input Using WatchDog Clock Maximum Delay from Enable Internal Valid Signal GPLD FPLD Propagation Delay Sleep Mode Access Time from Sleep Access Time from Power Down
-90**
Parameter
Conditions
Unit
CLCL (µs) (Note WDCLK (µs)
CLWH
NOTES: tCLCL CLKIN clock period. Figure
**-90 speed available only Industrial Operating Temperature Range product.
ZPSD7XX(V) Family
Microcontroller Interface AC/DC Parameters
Versions)
ZPSD7XX(V) Family
WatchDog Internal Oscillator Timing 10%) Parameter
(Note (Note RLQV CLCL CLCL
Symbol
Conditions
Unit
PDGL
Propagation Delay from GPLD Input Clear Internal WDOG_ON
WDPW
WatchDog Clear (CLR_WDOG) Enable (EN_WDOG) Pulse Width
fOSC
Internal Oscillator Frequency
WatchDog Clock WCLK Signal Period CLKIN Short Divisor (CLKIN/8K)
WatchDog Clock WCLK Signal Period CLKIN Long Divisor (CLKIN/2M)
tWDCLK
WatchDog Clock WCLK Signal Period Internal with Divisor (2KHz)
WatchDog Clock WCLK Signal Period Internal with Divisor (2KHz/256) WD_TMO 0,1,2.29 (Note
tWDTMO
WatchDog Timeout Period
WD_TMO WDCLK (µs) Pulse Generator Clock 0,1,2,3,4,5,6,7 (Note Pulse Generator Clock 0,1,2,3,4,5,6,7 (Note (kHz) 16384 CLCL 1000
tCHGH
WatchDog Clock Internal WDOG_ON High Delay
tGHGL
Internal WDON_ON Active Time Using Internal Oscillator
Internal WDON_ON Active Time Using External Clock (CLKIN)
NOTES: Refer PSDsoft Report Timing Parameters tWDTMO, tGHGL tNVNX.
Microcontroller Interface AC/DC Parameters
Versions)
Reset Timing 10%) Parameter
Using Internal Oscillator Using External Clock Input (CLKin) Pulse Generator Clock 0,1,2,3,4,5,6,7 (Note Pulse Generaror Clock= 0,1,2,3,4,5,6,7 (Note (kHz) 16384 CLCL
Symbol
Conditions
48/f (kHz) 393.2 CLCL (µs)
Unit
NLNH
Reset Input Minimum Active Time with Debouncer Enabled
Reset Input Minimum Active Time with Debouncer Disabled
tOPR
Operational after RESET Input Inactive
NVNX
RST_OUT, RST_OUT Output Active Time Using Internal Oscillator
RST_OUT, RST_OUT Output Active Time Using External Clock (CLKIN)
tNLNV
Reset RST_OUT, RST_OUT Output Valid with Debouncer Enabled
Reset RST_OUT, RST_OUT Output Valid with Debouncer Disabled
tVXNV
Fall Detect RST_OUT, RST_OUT Active with Digital Samplerr
Fall Detect RST_OUT, RST_OUT Active without Digital Sampler
tVVNX
Valid Internal Reset Active with Digital Sampler
Valid Internal Reset Active without Digital Sampler
ZPSD7XX(V) Family
NOTES: Refer PSDsoft Report Timing Parameters tWDTMO, tGHGL tNVNX.
Microcontroller Interface AC/DC Parameters
Versions)
ZPSD7XX(V) Family
CEout Timing 10%) Parameter
Load Load Load Load
Symbol
Conditions
Unit
NVCH
From Fall Detection (VCC CEOUT High with Digital Sampler
From Fall Detection (VCCtp) CEOUT High without Digital Sampler
NXCV
CEout Recovery Time after Power Detection (VCC VCCtp) with Digital Sampler
CEout Recovery Time after Power Detection (VCC VCCtp) without Digital Sampler
Vstbyon Timing 10%) Parameter Conditions
Symbol
Unit
BVBH
Vstby Detection Vstbyon Output High
BXBL
Vstby Detection Vstbyon Output
ZPSD7XX(V) Family
(3.3 Versions)
Characteristics
Symbol
VIH1 VIH2 VIL1 VHYS
Parameter
Supply Voltage High Level Input Voltage Level Input Voltage Reset High Level Input Voltage Reset Level Input Voltage Reset Hysteresis (Note
Conditions
Speeds (Note
-0.5 2.94 2.69
Unit
3.3V, Vtp(2:0) Power Supply Trip Point 3.3V, Vtp(2:0) Vtp(2:0) Power Reset VETP VOH1 VSBY ISBY IIDLE (DC) (Note External Trip Point (PC6) Output Voltage Output High Voltage Except VSTBYON, CEOUT
3.03 2.83
3.12 2.97
1.23
1.29 0.01 0.15
1.35 0.45
2.99 VSBY -0.5
Output High Voltage VSTBYON, CEOUT IOH1 SRAM Standby Voltage SRAM Standby Current Idle Current (VSTBY Pin) SRAM Data Retention Voltage Standby Supply Current Power Down Mode Sleep Mode VSBY Only VSTBY >VCC (Note >VCC (Note ZPLD_TURBO OFF, (Note ZPLD_TURBO CMiser 8-Bit Mode Other Cases CMiser 8-Bit Mode SRAM Adder CMiser 16-Bit Mode CMiser -0.1
Figure
Input Leakage Current Output Leakage Current Operating Supply Current ZPLD Base
ZPLD Only
µA/PT Figure
mA/MHz mA/MHz mA/MHz mA/MHz mA/MHz
EPROM Adder (AC) (Note
NOTES:
Reset input hysteresis. VIL1 valid below .2VCC -.1. VIH1 valid above .8VCC. deselected internal active. Sleep mode internal active. ZPLD ICC/Frequency Power Consumption graph details. IOUT
ZPSD7XX(V) AC/DC Parameters GPLD ECSPLD Timing Parameters
Versions)
ZPSD7XX(V) Family
GPLD ECSPLD Combinatorial Timing Versions)
Parameter
(Notes (Note (Note (Notes (Notes (Notes (Notes MicroCell (Notes MicroCell (Notes MicroCell
Aloc TURBO
Symbol
Conditions
Slew Rate
Unit
ECSPLD Input ECSPLD Combinatorial Output
GPLD Input Pin/Feedback GPLD Combinatorial Output Port
GPLD Input Pin/Feedback GPLD Combinatorial Output Port
GPLD Input ECSPLD Output Enable
GPLD Input GPLD Output Enable
GPLD Input ECSPLD Output Disable
GPLD Input GPLD Output Disable
GPLD Register Clear Preset Delay
ARPW
GPLD Register Clear Preset Pulse Width
GPLD Array Delay
NOTES:
ECSPLD Input pins A(0:15), PGR(0:3), CNTL(0:2), PDN. ECSPLD Outputs PA(0:3), PB(0:3), PD(0:2). GPLD Inputs A(0:15), PGR(0:3), CNTL(0:2), PA(0:7), PB(0:7), PC(0:7), PD(0:2), ALE, PDN, Reset, WDOG_ON, WCLK. GPLD Outputs PA(4:7), PB(4:7), PC(0:7).
ZPSD7XX(V) AC/DC Parameters GPLD ECSPLD Timing Parameters
Versions)
GPLD MicroCell Synchronous Clock Mode Timing Versions)
Parameter
1/(tS 1/(tS -10) 1/(tC (Note (Note Clock Input Clock Input Clock Input MicroCell 31.25 17.24 14.71
12.82 14.71 27.78
Symbol
Conditions
Aloc
TURBO
Slew Rate
Unit
Maximum Frequency External Feedback
Maximum Frequency Internal Feedback fCNT
Maximum Frequency Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Time
Clock Output Delay
GPLD Array Delay
Minimum Clock Period
NOTES: GPLD Inputs A(0:15), PGR(0:3), CNTL(0:2), PA(0:7), PB(0:7), PC(0:7), PD(0:2), ALE, PDN, Reset, WDOG_ON, WCLK. CLKIN tCLCL tCL.
ZPSD7XX(V) Family
ZPSD7XX(V) AC/DC Parameters GPLD ECSPLD Timing Parameters
Versions)
ZPSD7XX(V) Family
GPLD MicroCell Asynchronous Clock Mode Timing Versions)
Parameter
1/(tS 1/(tS -10) 17.24 24.40 1/(tC (Note (Note (Note (Note (Note MicroCell 14.71 21.70 14.71 12.82
Aloc TURBO Slew Rate Unit
Symbol
Conditions
Maximum Frequency External Feedback
MAXA
Maximum Frequency Internal Feedback fCNTA)
Maximum Frequency Pipelined Data
Input Setup Time
Input Hold Time
Clock Input High Time
Clock Input Time
Clock Output Delay
GPLD Array Delay
MINA
Minimum Clock Period
NOTES: GPLD Inputs A(0:15), PGR(0:3), CNTL(0:2), PA(0:7), PB(0:7), PC(0:7), PD(0:2), ALE, PDN, Reset, WDOG_ON, WCLK.
ZPSD7XX(V) AC/DC Parameters GPLD ECSPLD Timing Parameters
Versions)
Input MicroCell Timing Versions)
Symbol
Input Combinatorial Output Delay (Note Input Time (Note Input High Time (Note Input Hold Time (Note Input Setup Time (Note
Parameter
Conditions
Aloc
TURBO
Unit
NOTES: Inputs from Port relative register/latch clock from PLD. latch timings refer tAVLX tLXAX.
ZPSD7XX(V) Family
ZPSD7XX(V) Family
Microcontroller Interface ZPSD7XX(V) AC/DC Parameters
Versions)
Explanation Symbols ZPLD Timing. Example:
AVLX Time from Address Valid Invalid.
Signal Letters
Address Input CEout Output Input Data Input Internal WDOG_ON signal Interrupt Input Input Reset Input Output Port Signal Output Output Data UDS, LDS, IORD, PSEN Inputs Chip Select Input Input Internal Signal Vstby Output Output MicroCell
Signal Behavior
Time Logic Level Logic Level High Valid Longer Valid Logic Level Float Pulse Width
Microcontroller Interface ZPSD7XX(V) AC/DC Parameters
Versions)
Read Timing Versions)
Symbol
LVLX AVLX LXAX AVQV SLQV Data Valid 8/16-Bit RLQV Data Valid 8-Bit Bus, 8031, 80251 Separate Mode Data Hold Time Pulse Width Data High-Z Pulse Width Setup Time Enable Hold Time After Enable Address Input Valid Address Output Delay 16-Bit Mode (Note 8-Bit Mode (Note RHQX RLRH RHQZ EHEL THEH ELTL AVPV (Note (Note (Note (Note (Note Valid Data Valid Address Valid Data Valid (Note Address Hold Time (Note Address Setup Time (Note Pulse Width
Parameter
Conditions
CMiser
Unit
ZPSD7XX(V) Family
NOTES:
timing same timing LDS, UDS, PSEN 8031 combined mode) signals. PSEN have same timing 8031 separate mode. input used select internal ZPSD7XX(V) function. multiplexed mode latched address generated from ADIO delay address output Port.
Microcontroller Interface ZPSD7XX(V) AC/DC Parameters
Versions)
ZPSD7XX(V) Family
Write Timing Versions)
Symbol
LVLX AVLX LXAX AVWL SLWL DVWH WHDX WLWH WHAX WHPV WLMV DVMV Data Valid Port Output Valid Using MicroCell Register Data Address Input Valid Address Output Delay Valid Port Output Valid Using MicroCell Register Load Trailing Edge Port Output Valid Using Port Data Register Trailing Edge Address Invalid Pulse Width Data Hold Time Data Setup Time (Note (Note (Note (Note (Note (Notes (Notes 16-Bit Mode (Note 8-Bit Mode (Note Valid Leading Edge (Note Address Valid Leading Edge (Notes Address Hold Time (Note Address Setup Time (Note Pulse Width
Parameter
Conditions
Unit
AVPV
NOTE: timing same timing LDS, UDS, WRL, signals. Assuming data stable before active write signal. Assuming write active before data becomes valid.
Microcontroller Interface ZPSD7XX(V) AC/DC Parameters
Versions)
Port Peripheral Data Mode Read Timing 10%)
Symbol
AVQV (PA) SLQV (PA) RLQV (PA) Data Valid 8031 Mode Data Data Valid Data Hold Time Pulse Width Data High-Z (Note (Note (Note DVQV (PA) QXRH (PA) RLRH (PA) RHQZ (PA) Data Valid (Notes Valid Data Valid Address Valid Data Valid (Note
Parameter
Conditions
TURBO
Unit
Port Peripheral Data Mode Write Timing 10%)
Symbol
WLQV (PA) DVQV (PA) WHQZ (PA)
Conditions
(Note (Note (Note
Parameter
Data Propagation Delay Data Port Data Propagation Delay Invalid Port Tri-state
TURBO
Unit
ZPSD7XX(V) Family
NOTES: input used select Port Data Peripheral Mode. Data already stable Port Data stable ADIO pins data Port
Microcontroller Interface AC/DC Parameters
Versions)
ZPSD7XX(V) Family
Power Down Timing 10%)
Symbol
LVDV LVDV1 Access Ti
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