Single-chip 16/32-bit microcontrollers; 32/64/512 ISP/IAP Flash with 1
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LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers; 32/64/512 ISP/IAP Flash with 10-bit
Rev. November 2004 Preliminary data sheet
LPC2131/2132/2138 microcontrollers based 32/16 ARM7TDMI-SCPU with real-time emulation embedded trace support, that combines microcontroller with embedded high speed Flash memory. 128-bit wide memory interface unique accelerator architecture enable 32-bit code execution maximum clock rate. critical code size applications, alternative 16-bit Thumb® Mode reduces code more than with minimal performance penalty. their tiny size power consumption, these microcontrollers ideal applications where miniaturization requirement, such access control point-of-sale. With wide range serial communications interfaces on-chip SRAM options 8/16/32 they very well suited communication gateways protocol converters, soft modems, voice recognition imaging, providing both large buffer size high processing power. Various 32-bit timers, single dual 10-bit channel ADC(s), 10-bit DAC, channels GPIO lines with nine edge level sensitive external interrupt pins make these microcontrollers particularly suitable industrial control medical systems.
Features
features
16/32-bit ARM7TDMI-S microcontroller tiny LQFP64 package. 8/16/32 on-chip static 64/512 on-chip Flash program memory. wide interface/accelerator enables high speed operation. In-System/In-Application Programming (ISP/IAP) on-chip boot-loader software. Single Flash sector full chip erase programming bytes EmbeddedICE® Embedded Trace interfaces offer real-time debugging with on-chip RealMonitorsoftware high speed tracing instruction execution. (LPC2131/2132) (LPC2138) channel 10-bit converters provides total analog inputs, with conversion times 2.44 channel. Single 10-bit converter provides variable analog output. (LPC2132/2138 only) 32-bit timers/counters (with four capture four compare channels each), unit (six outputs) watchdog. Real-time clock equipped with independent power clock supply permitting extremely power consumption power-save modes. Multiple serial interfaces including UARTs (16C550), Fast I2C-bus (400 kbit/s), SPIand with buffering variable data length capabilities. Vectored interrupt controller with configurable priorities vector addresses.
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
tolerant general purpose pins tiny LQFP64 package. nine edge level sensitive external interrupt pins available. maximum clock available from programmable on-chip with settling time On-chip crystal oscillator with operating range MHz. Power saving modes include Idle Power-down. Individual enable/disable peripheral functions well peripheral clock scaling down additional power optimization. Processor wake-up from Power-down mode external interrupt. Single power supply chip with circuits: operating voltage range (3.3 with tolerant pads.
Ordering information
Table Ordering information Package Name LPC2131FBD64 LPC2132FBD64 LPC2138FBD64 LQFP64 LQFP64 LQFP64 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body Version SOT314-2 SOT314-2 SOT314-2 Type number
Ordering options
Table Ordering options Flash memory Temperature range (°C) Type number LPC2131FBD64 LPC2132FBD64 LPC2138FBD64
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
Rev. November 2004
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Block diagram
TMS(1) TDI(1) TRST(1) TCK(1) TDO(1) XTAL2 XTAL1
LPC2132/2138
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
system clock
SYSTEM FUNCTIONS VECTORED INTERRUPT CONTROLLER
ARM7TDMI-S
BRIDGE ARM7 local
AMBA (Advanced High-performance Bus)
INTERNAL SRAM CONTROLLER
INTERNAL FLASH CONTROLLER
DECODER BRIDGE DIVIDER
8/16/32 SRAM
32/64/512 FLASH
(VLSI peripheral bus) EINT3:0 EXTERNAL INTERRUPTS SERIAL INTERFACES SCL0,1 SDA0,1 SCK0,1 CAPTURE/ COMPARE TIMER 0/TIMER SERIAL INTERFACES MOSI0,1 MISO0,1 SSEL0,1 TXD0,1 UART0/UART1 RXD0,1
CAP0
AD0.7:0 AD1.7:0(1)
CONVERTERS 1(1)
AOUT(2)
CONVERTER(2)
REAL TIME CLOCK
DSR1(1),CTS1(1), RTS1(1), DTR1(1) DCD1(1),RI1(1) RTXC1 RTXC2
VBAT
P0.31:0 P1.31:16,
GENERAL PURPOSE
WATCHDOG TIMER
PWM6:1
PWM0
SYSTEM CONTROL
002aab067
LPC2138 only. LPC2132/2138 only.
Block diagram.
9397 14008 Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
Rev. November 2004
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Pinning information
Pinning
P0.19/MAT1.2/MOSI1/CAP1.2 P0.18/CAP1.3/MISO1/MAT1.3 P0.20/MAT1.3/SSEL1/EINT3
P1.30/TMS
P1.27/TDO
P1.29/TCK
P1.28/TDI
RESET
XTAL1
XTAL2
P0.23
VSSA
VREF
P0.21/PWM5/AD1.6(1)/CAP1.3 P0.22/AD1.7(1)/CAP0.0/MAT0.0 RTXC1 P1.19/TRACEPKT3 RTXC2 VDDA P1.18/TRACEPKT2 P0.25/AD0.4/AOUT(2)
VBAT P1.20/TRACESYNC P0.17/CAP1.2/SCK1/MAT1.2 P0.16/EINT0/MAT0.2/CAP0.2 P0.15/RI1(1)/EINT2/AD1.5(1) P1.21/PIPESTAT0 P0.14/DCD1(1)/EINT1/SDA1 P1.22/PIPESTAT1 P0.13/DTR1(1)/MAT1.1/AD1.4(1) P0.12/DSR1(1)/MAT1.0/AD1.3(1) P0.11/CTS1(1)/CAP1.1/SCL1 P1.23/PIPESTAT2 P0.10/RTS1(1)/CAP1.0/AD1.2(1) P0.9/RXD1/PWM6/EINT3 P0.8/TXD1/PWM4/AD1.1(1) P1.24/TRACECLK
002aab068
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P0.6/MOSI0/CAP0.2/AD1.0(1)
LPC2131/2132/2138
P0.26/AD0.5 P0.27/AD0.0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 P0.28/AD0.1/CAP0.2/MAT0.2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 P1.16/TRACEPKT0
P0.31
P0.0/TXD0/PWM1
P1.31/TRST
P0.1/RXD0/PWM3/EINT0
P0.2/SCL0/CAP0.0
P1.26/RTCK
P0.3/SDA0/MAT0.0/EINT1
P0.4/SCK0/CAP0.1/AD0.6
P1.25/EXTIN0
P0.5/MISO0/MAT0.1/AD0.7
LPC2138 only. LPC2132/2138 only.
Pinning.
9397 14008
Preliminary data sheet
Rev. November 2004
P0.7/SSEL0/PWM2/EINT2
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
description
Table Symbol P0.0 P0.31 description Type Description Port Port 32-bit port with individual direction controls each bit. Total pins Port used general purpose bi-directional digital I/Os while P0.31 output only pin. operation port pins depends upon function selected connect block. P0.24 available. P0.0/TXD0/ PWM1 P0.1/RXD0/ PWM3/EINT0 P0.2/SCL0/ CAP0.0 P0.3/SDA0/ MAT0.0/EINT1 P0.4/SCK0/ CAP0.1/AD0.6 P0.5/MISO0/ MAT0.1/AD0.7 P0.6/MOSI0/ CAP0.2/AD1.0 P0.7/SSEL0/ PWM2/EINT2 P0.8/TXD1/ PWM4/AD1.1 P0.9/RXD1/ PWM6/EINT3 TXD0 Transmitter output UART0. PWM1 Pulse Width Modulator output RXD0 Receiver input UART0. PWM3 Pulse Width Modulator output EINT0 External interrupt input SCL0 I2C0 clock input/output. Open drain output (for I2C-bus compliance). CAP0.0 Capture input Timer channel SDA0 I2C0 data input/output. Open drain output (for I2C-bus compliance). MAT0.0 Match output Timer channel EINT1 External interrupt input. SCK0 Serial clock SPI0. clock output from master input slave. CAP0.1 Capture input Timer channel AD0.6 converter input This analog input always connected pin. MISO0 Master Slave SPI0. Data input master data output from slave. MAT0.1 Match output Timer channel AD0.7 converter input This analog input always connected pin. MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0.2 Capture input Timer channel AD1.0 converter input This analog input always connected pin. Available LPC2138 only. SSEL0 Slave Select SPI0. Selects interface slave. PWM2 Pulse Width Modulator output EINT2 External interrupt input. TXD1 Transmitter output UART1. PWM4 Pulse Width Modulator output AD1.1 converter input This analog input always connected pin. Available LPC2138 only. RXD1 Receiver input UART1. PWM6 Pulse Width Modulator output EINT3 External interrupt input.
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
Rev. November 2004
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Table Symbol
description .continued Type Description RTS1 Request Send output UART1. Available LPC2138 only. CAP1.0 Capture input Timer channel AD1.2 converter input This analog input always connected pin. Available LPC2138 only. CTS1 Clear Send input UART1. Available LPC2138 only. CAP1.1 Capture input Timer channel SCL1 I2C1 clock input/output. Open drain output (for I2C-bus compliance) DSR1 Data Ready input UART1. Available LPC2138 only. MAT1.0 Match output Timer channel AD1.3 converter input This analog input always connected pin. Available LPC2138 only. DTR1 Data Terminal Ready output UART1. Available LPC2138 only. MAT1.1 Match output Timer channel AD1.4 converter input This analog input always connected pin. Available LPC2138 only. DCD1 Data Carrier Detect input UART1. Available LPC2138 only. EINT1 External interrupt input. SDA1 I2C1 data input/output. Open drain output (for I2C-bus compliance) Ring Indicator input UART1. Available LPC2138 only. EINT2 External interrupt input. AD1.5 converter input This analog input always connected pin. Available LPC2138 only. EINT0 External interrupt input. MAT0.2 Match output Timer channel CAP0.2 Capture input Timer channel CAP1.2 Capture input Timer channel SCK1 Serial Clock SSP. Clock output from master input slave. MAT1.2 Match output Timer channel CAP1.3 Capture input Timer channel MISO1 Master Slave SSP. Data input master data output from slave. MAT1.3 Match output Timer channel MAT1.2 Match output Timer channel MOSI1 Master Slave SSP. Data output from master data input slave. CAP1.2 Capture input Timer channel MAT1.3 Match output Timer channel SSEL1 Slave Select SSP. Selects interface slave. EINT3 External interrupt input. PWM5 Pulse Width Modulator output AD1.6 converter input This analog input always connected pin. Available LPC2138 only. CAP1.3 Capture input Timer channel
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P0.10/RTS1/ CAP1.0/AD1.2
P0.11/CTS1/ CAP1.1/SCL1
P0.12/DSR1/ MAT1.0/AD1.3
P0.13/DTR1/ MAT1.1/AD1.4
P0.14/DCD1/ EINT1/SDA1
P0.15/RI1/ EINT2/AD1.5
P0.16/EINT0/ MAT0.2/CAP0.2
P0.17/CAP1.2/ SCK1/MAT1.2
P0.18/CAP1.3/ MISO1/MAT1.3
P0.19/MAT1.2/ MOSI1/CAP1.2
P0.20/MAT1.3/ SSEL1/EINT3
P0.21/PWM5/ AD1.6/CAP1.3
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Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Table Symbol
description .continued Type Description AD1.7 converter input This analog input always connected pin. Available LPC2138 only. CAP0.0 Capture input Timer channel MAT0.0 Match output Timer channel General purpose digital input/output pin. AD0.4 converter input This analog input always connected pin. AOUT converter output. Available LPC2132 LPC2138 only. AD0.5 converter input This analog input always connected pin. AD0.0 converter input This analog input always connected pin. CAP0.1 Capture input Timer channel MAT0.1 Match output Timer channel AD0.1 converter input This analog input always connected pin. CAP0.2 Capture input Timer channel MAT0.2 Match output Timer channel AD0.2 converter input This analog input always connected pin. CAP0.3 Capture input Timer Channel MAT0.3 Match output Timer channel AD0.3 converter input This analog input always connected pin. EINT3 External interrupt input. CAP0.0 Capture input Timer channel General purpose digital output only pin. Port Port 32-bit bi-directional port with individual direction controls each bit. operation port pins depends upon function selected connect block. Pins through port available. TRACEPKT0 Trace Packet, Standard port with internal pull-up. TRACEPKT1 Trace Packet, Standard port with internal pull-up. TRACEPKT2 Trace Packet, Standard port with internal pull-up. TRACEPKT3 Trace Packet, Standard port with internal pull-up. TRACESYNC Trace Synchronization. Standard port with internal pull-up. TRACESYNC while RESET enables pins P1.25:16 operate Trace port after reset. PIPESTAT0 Pipeline Status, Standard port with internal pull-up. PIPESTAT1 Pipeline Status, Standard port with internal pull-up.
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P0.22/AD1.7/ CAP0.0/MAT0.0
P0.23 P0.25/AD0.4/ AOUT P0.26/AD0.5
P0.27/AD0.0/ CAP0.1/MAT0.1
P0.28/AD0.1/ CAP0.2/MAT0.2
P0.29/AD0.2/ CAP0.3/MAT0.3
P0.30/AD0.3/ EINT3/CAP0.0
P0.31 P1.0 P1.31
P1.16/ TRACEPKT0 P1.17/ TRACEPKT1 P1.18/ TRACEPKT2 P1.19/ TRACEPKT3 P1.20/ TRACESYNC P1.21/ PIPESTAT0 P1.22/ PIPESTAT1
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Preliminary data sheet
Rev. November 2004
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Table Symbol
description .continued Type Description PIPESTAT2 Pipeline Status, Standard port with internal pull-up. TRACECLK Trace Clock. Standard port with internal pull-up. EXTIN0 External Trigger Input. Standard with internal pull-up. RTCK Returned Test Clock output. Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bi-directional with internal pull-up. RTCK while RESET enables pins P1.31:26 operate Debug port after reset. Test Data JTAG interface. Test Data JTAG interface. Test Clock JTAG interface. Test Mode Select JTAG interface. TRST Test Reset JTAG interface. External reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Input oscillator circuit. Output from oscillator circuit. Ground: reference. Analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. power supply: This power supply voltage core ports. Analog power supply: This should nominally same voltage should isolated minimize noise error. This voltage used power on-chip PLL. converter reference: This should nominally same voltage should isolated minimize noise error. Level this used reference convertor. power supply: this supplies power RTC.
P1.23/ PIPESTAT2 P1.24/ TRACECLK P1.25/EXTIN0 P1.26/RTCK
P1.27/TDO P1.28/TDI P1.29/TCK P1.30/TMS P1.31/TRST RESET
XTAL1 XTAL2 RTXC1 RTXC2 VSSA VDDA
VREF
VBAT
9397 14008
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
Rev. November 2004
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Functional description
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. ARM® architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit Thumb set.
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-Chip Flash program memory
LPC2131/2132/2138 incorporate Flash memory system respectively. This memory used both code data storage. Programming Flash memory accomplished several ways. programmed System serial port. application program also erase and/or program Flash while application running, allowing great degree flexibility data storage field firmware upgrades, etc. When LPC2131/2132/2138 on-chip bootloader used, 32/64/500 Flash memory available user code. LPC2131/2132/2138 Flash memory provides minimum 10,000 erase/write cycles years data-retention.
On-Chip static
On-Chip static used code and/or data storage. SRAM accessed 8-bits, 16-bits, 32-bits. LPC2131/2132/2138 provide 8/16/32 static RAM.
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Preliminary data sheet
Rev. November 2004
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Memory
LPC2131/2132/2138 memory maps incorporate several distinct regions, shown following figures. addition, interrupt vectors re-mapped allow them reside either Flash memory (the default) on-chip static RAM. This described Section 6.21 "System control".
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xE000 0000
RESERVED ADDRESS SPACE
0xC000 0000
0x8000 0000 BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY RESERVED ADDRESS SPACE 0x4001 0000 0x4000 FFFF TOTAL ON-CHIP STATIC (LPC2138) TOTAL ON-CHIP STATIC (LPC2132) TOTAL ON-CHIP STATIC (LPC2131) 0x4000 4000 0x4000 3FFF 0x4000 2000 0x4000 1FFF 0x4000 0000 0x0008 0000 0x0007 FFFF 0x0001 0000 0x0000 FFFF 0x0000 8000 0x0000 7FFF 0x0000 0000
TOTAL ON-CHIP NON-VOLATILE MEMORY (LPC2138) TOTAL ON-CHIP NON-VOLATILE MEMORY (LPC2132) TOTAL ON-CHIP NON-VOLATILE MEMORY (LPC2131)
002aab069
LPC2131/2132/2138 memory map.
Interrupt controller
accepts interrupt request inputs categorizes them FIQ, vectored IRQ, non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted.
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Preliminary data sheet
Rev. November 2004
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Fast Interrupt reQuest (FIQ) highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt. Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest. Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs requesting, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active.
6.5.1 Interrupt sources
Table lists interrupt sources each peripheral function. Each peripheral device interrupt line connected Vectored Interrupt Controller, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
Table Block Core Core TIMER0 TIMER1 UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved software interrupts only Embedded ICE, DbgCommRX Embedded ICE, DbgCommTX Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) UART1 Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) (Available LPC2138 only) PWM0 I2C0 Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) Capture (CR0, CR1, CR2, CR3) (state change) channel
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Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Interrupt sources .continued Flag(s) SPIF, MODF FIFO least half empty (TXRIS) FIFO least half full (RXRIS) Receive Timeout (RTRIS) Receive Overrun (RORRIS) channel
Table Block SPI0
System Control
Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt (EINT0) External Interrupt (EINT1) External Interrupt (EINT2) External Interrupt (EINT3)
I2C1
Converter (state change) Brown Detect Converter (Available LPC2138 only)
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined. Control Module contains three registers shown Table
Table Address 0xE002C000 0xE002C004 0xE002C014 control module registers Name PINSEL0 PINSEL1 PINSEL2 Description function select register function select register function select register Access Read/Write Read/Write Read/Write
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Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
function select register (PINSEL0 0xE002C000)
PINSEL0 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions, direction controlled automatically. Settings other than those shown Table reserved, should used.
Table PINSEL0 function select register (PINSEL0 0xE002C000) name P0.0 Value P0.1 P0.2 P0.3 P0.4 11:10 P0.5 13:12 P0.6 15:14 P0.7 Function GPIO Port (UART0) PWM1 Reserved GPIO Port (UART0) PWM3 EINT0 GPIO Port SCL0 (I2C0) Capture (Timer Reserved GPIO Port SDA0 EINT1 GPIO Port SCK0 (SPI0) Capture (Timer AD0.6 GPIO Port MISO0 (SPI0) Match (Timer AD0.7 GPIO Port MOSI0 (SPI0) Capture (Timer Reserved (LPC2131/32) AD1.0 (LPC2138) GPIO Port SSEL0 (SPI0) PWM2 EINT2 (I2C0) Match (Timer Value after reset
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Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
function select register (PINSEL0 0xE002C000) .continued name P0.8 Value Function GPIO Port UART1 PWM4 Reserved (LPC2131/32) AD1.1 (LPC2138) GPIO Port (UART1) PWM6 EINT3 GPIO Port 0.10 Reserved (LPC2131/32) (UART1) (LPC2138) Capture (Timer Reserved (LPC2131/32) AD1.2 (LPC2138) GPIO Port 0.11 Reserved (LPC2131/32) (UART1) (LPC2138) Capture (Timer SCL1 (I2C1) GPIO Port 0.12 Reserved (LPC2131/32) (UART1) (LPC2138) Match (Timer Reserved (LPC2131/32) AD1.3 (LPC2138) GPIO Port 0.13 Reserved (LPC2131/32) (UART1) (LPC2138) Match (Timer Reserved (LPC2131/32) AD1.4 (LPC2138) GPIO Port 0.14 Reserved (LPC2131/32) (UART1) (LPC2138) EINT1 SDA1 (I2C1) GPIO Port 0.15 Reserved (LPC2131/32) (UART1) (LPC2138) EINT2 Reserved (LPC2131/32) AD1.5 (LPC2138) Value after reset
Table PINSEL0 17:16
19:18
P0.9
21:20
P0.10
23:22
P0.11
25:24
P0.12
27:26
P0.13
29:28
P0.14
31:30
P0.15
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Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
function select register (PINSEL1 0xE002C004)
PINSEL1 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Settings other than those shown table reserved, should used.
Table PINSEL1 function select register (PINSEL1 0xE002C004) Name P0.16 Value P0.17 P0.18 P0.19 P0.20 11:10 P0.21 13:12 P0.22 15:14 P0.23 Function GPIO Port 0.16 EINT0 Match (Timer Capture (Timer GPIO Port 0.17 Capture (Timer (SSP) Match (Timer GPIO Port 0.18 Capture (Timer MISO (SSP) Match (Timer GPIO Port 0.19 Match (Timer MOSI (SSP) Capture (Timer GPIO Port 0.20 Match (Timer SSEL (SSP) EINT3 GPIO Port 0.21 PWM5 Reserved (LPC2131/32) AD1.6 (LPC2138) Capture (Timer GPIO Port 0.22 Reserved (LPC2131/32) AD1.7 (LPC2138) Capture (Timer Match (Timer GPIO Port 0.23 Reserved Reserved Reserved Value after reset
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Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
function select register (PINSEL1 0xE002C004) .continued Name P0.24 Value Function Reserved Reserved Reserved Reserved GPIO Port 0.25 AD0.4 Reserved (LPC2131) AOUT (DAC) (LPC2132/38) Reserved GPIO Port 0.26 AD0.5 Reserved Reserved GPIO Port 0.27 AD0.0 Capture (Timer Match (Timer GPIO Port 0.28 AD0.1 Capture (Timer Match (Timer GPIO Port 0.29 AD0.2 Capture (Timer Match (Timer GPIO Port 0.30 AD0.3 EINT3 Capture (Timer GPIO Port Reserved Reserved Reserved Value after reset
Table PINSEL1 17:16
19:18
P0.25
21:20
P0.26
23:22
P0.27
25:24
P0.28
27:26
P0.29
29:28
P0.30
31:30
P0.31
function select register (PINSEL2 0xE002C014)
PINSEL2 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Settings other than those shown table reserved, should used.
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Preliminary data sheet
Rev. November 2004
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
function select register (PINSEL2 0xE002C014) Description Reserved When pins P1.31:26 GPIO pins. When P1.31:26 used Debug port. Reset value
Table 31:30
PINSEL2 bits
When pins P1.25:16 used GPIO pins. When P1.25:16 used Trace port. Reserved
6.10 General purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins.
6.10.1 Features
Direction control individual bits. Separate control output clear. default inputs after reset. 6.11 10-bit converter
LPC2131/32 contain LPC2138 contains analog digital converters. These converters single 10-bit successive approximation analog digital converters with eight multiplexed channels.
6.11.1 Features
Measurement range Each converter capable performing more than 400,000 10-bit samples second. Burst conversion mode single multiple inputs. Optional conversion transition input Timer Match signal. Global Start command both converters (LPC2138 only).
6.12 10-bit converter
This peripheral available LPC2138 only. converter enables LPC2138 generate variable analog output.
6.12.1 Features
digital analog converter. Buffered output. Power-down mode available. Selectable speed versus power.
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Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
6.13 UARTs
LPC2131/2132/2138 each contain UARTs. addition standard transmit receive data lines, LPC2138 UART1 provides full modem control handshake interface, too.
6.13.1 Features
byte Receive Transmit FIFOs. Register locations conform `550 industry standard. Receiver FIFO trigger points bytes Built-in baud rate generator. Standard modem interface signals included UART1. (LPC2138 only) LPC2131/2132/2138 transmission FIFO control enables implementation software (XON/XOFF) flow control both UARTs hardware (CTS/RTS) flow control LPC2138 UART1 only.
6.14 I2C-bus serial controller
LPC2131/2132/2138 each contain I2C-bus controllers. I2C-bus bi-directional, inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver transmitter with capability both receive send information (such memory)). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. I2C-bus multi-master bus, controlled more than master connected I2C-bus implemented LPC2131/2132/2138 supports rates kbit/s (Fast I2C).
6.14.1 Features
Standard compliant interface. Easy configure Master, Slave, Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes.
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Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
6.15 serial controller
LPC2131/2132/2138 each contain controller. full duplex serial interface, designed able handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master.
6.15.1 Features
Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, Serial, Full Duplex, Communication. Combined master slave. Maximum data rate eighth input clock rate.
6.16 serial controller
LPC2131/2132/2138 each contain Serial Synchronous Port controller (SSP). controller capable operation SPI, 4-wire SSITM, Microwirebus. interact with multiple masters slaves bus. However, only single master single slave communicate during given data transfer. supports full duplex transfers, with frames bits bits data flowing from master slave from slave master. Often only these data flows carries meaningful data.
6.16.1 Features
Compatible with Motorola SPI, 4-wire National Semiconductor Microwire
buses.
Synchronous Serial Communication. Master slave operation. 8-frame FIFOs both transmit receive. Four bits bits frame.
6.17 General purpose timers/counters
Timer/Counter designed count cycles peripheral clock (PCLK) externally supplied clock, optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them.
6.17.1 Features
32-bit Timer/Counter with programmable 32-bit Prescaler. Counter timer operation. Four 32-bit capture channels timer that take snapshot timer value
when input signal transitions. capture event also optionally generate interrupt.
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LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Four external outputs timer corresponding match registers, with following
capabilities: match. HIGH match. Toggle match. nothing match.
6.18 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
6.18.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (TPCLK (TPCLK multiples TPCLK
6.19 Real-time clock
Real-Time Clock (RTC) designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode).
6.19.1 Features
Measures passage time maintain calendar clock. Ultra-low power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
either dedicated oscillator input clock derived from
external crystal/oscillator input XTAL1. Programmable Reference Clock Divider allows fine adjustment RTC.
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Dedicated power supply connected battery main 6.20 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2131/2132/2138. Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. function also based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs. Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
6.20.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit Prescaler. 6.21 System control
6.21.1 Crystal oscillator
oscillator supports crystals range MHz. oscillator output frequency called fosc processor clock frequency referred CCLK purposes rate equations, etc. fosc CCLK same value unless running connected. Refer Section 6.21.2 "PLL" additional information.
6.21.2
accepts input clock frequency range MHz. input frequency multiplied into range with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle.The turned bypassed following chip reset enabled software. program must configure activate PLL, wait Lock, then connect clock source. settling time
6.21.3 Reset wake-up timer
Reset sources LPC2131/2132/2138: RESET watchdog reset. RESET Schmitt trigger input with additional glitch filter. Assertion chip reset source starts wake-up timer (see wake-up timer description below), causing internal chip reset remain asserted until external reset de-asserted, oscillator running, fixed number clocks have passed, on-chip Flash controller completed initialization. When internal reset removed, processor begins executing address which reset vector. that point, processor peripheral registers have been initialized predetermined values. wake-up timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power types reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes wake-up timer. wake-up timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce
9397 14008 Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
6.21.4 Brown-out detector
LPC2131/2132/2138 include 2-stage monitoring voltage pins. this voltage falls below asserts interrupt signal Vectored Interrupt Controller. This signal enabled interrupt; not, software monitor signal reading dedicated register. second stage low-voltage detection asserts reset inactivate LPC2131/2132/2138 when voltage pins falls below This reset prevents alteration Flash operation various elements chip would otherwise become unreliable voltage. circuit maintains this reset down below which point circuitry maintains overall reset. Both thresholds include some hysteresis. normal operation, this hysteresis allows detection reliably interrupt, regularly-executed event loop sense condition.
6.21.5 Code security
This feature LPC2131/2132/2138 allow application control whether debugged protected from observation. after reset on-chip boot-loader detects valid checksum Flash reads 0x87654321 from address 0x1FC Flash, debugging will disabled thus code Flash will protected from observation. Once debugging disabled, enabled only performing full chip erase.
6.21.6 External interrupt inputs
LPC2131/2132/2138 include nine edge level sensitive External Interrupt Inputs selectable functions. When pins combined, external events processed four independent interrupt signals. External Interrupt Inputs optionally used wake processor from Power-down mode.
6.21.7 Memory Mapping Control
Memory Mapping Control alters mapping interrupt vectors that appear beginning address 0x00000000. Vectors mapped bottom on-chip Flash memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
6.21.8 Power Control
LPC2131/2132/2138 support reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses.
9397 14008
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Power-down mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. Power Control Peripherals feature allows individual peripherals turned they needed application, resulting additional power savings.
6.21.9
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside bus), default condition reset processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
6.22 Emulation debugging
LPC2131/2132/2138 support emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs Port This means that communication, timer interface peripherals residing Port available during development debugging phase they when application embedded system itself.
6.22.1 EmbeddedICE
Standard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts Remote Debug Protocol commands JTAG data needed access core. core Debug Communication Channel function built-in. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed co-processor program running ARM7TDMI-S core. debug communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICE logic.
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
6.22.2 Embedded trace
Since LPC2131/2132/2138 have significant amounts on-chip memory, possible determine processor core operating simply observing external pins. Embedded Trace Macrocellprovides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external trace port analyzer must capture trace information under software debugger control. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code traced because this restriction.
6.22.3 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using DCC, which present EmbeddedICE logic. LPC2131/2132/2138 contain specific configuration RealMonitor software programmed into on-chip Flash memory.
9397 14008
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
Rev. November 2004
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Symbol VDDA VBAT VREF Tstg Ptot Parameter supply voltage, core external rail analog supply voltage power supply voltage converter reference voltage analog input voltage related pins input voltage, tolerant pins input voltage, other pins supply current supply ground current ground storage temperature total power dissipation (based package heat transfer, device power consumption)
Conditions
-0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5
+3.6
Unit
following applies Limiting values: Stresses above those listed under Limiting values cause permanent damage device. This stress rating only functional operation device these conditions other than those described Section "Static characteristics"and Section "Dynamic characteristics" this specification implied. This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Including voltage outputs 3-state mode. Only valid when supply voltage present. exceed peak current limited times corresponding maximum current. Dependent package type.
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Static characteristics
Table characteristics commercial, unless otherwise specified. Symbol Parameter VDDA VBAT VREF supply voltage, core external rail analog supply voltage supply voltage converter reference voltage LOW-level input current HIGH-level input current 3-state output leakage current latch-up current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output LOW-level output voltage VDDA CCLK MHz, code voltage output active pull-up VDD; no-pull-down VDD; pull-up/down -(0.5 VDD) (1.5 VDD) Vhys IOHS IOLS
Conditions
Unit
Standard port pins, RESET, RTCK Ilatch <tbd>
HIGH-level output current LOW-level output current HIGH-level short circuit current LOW-level short circuit current pull-down current pull-up current (applies P1.16 P1.25) active mode supply current
while(1){}
executed from FLASH, active peripherals Power-down mode I2C-bus
9397 14008
0.7Vtol
<tbd> <tbd>
<tbd> 0.3Vtol
pins HIGH-level input voltage LOW-level input voltage Vtol from Vtol from
Rev. November 2004
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Table characteristics .continued commercial, unless otherwise specified. Symbol Parameter Vhys hysteresis voltage LOW-level output voltage Conditions Vtol from IOLS Oscillator pins VXTAL1 VXTAL2 VRTXC1 VRTXC2
0.5Vtol
Unit
input leakage current
XTAL1 input voltages XTAL2 output voltages RTXC1 input voltages RTXC2 output voltages
Typical ratings guaranteed. values listed room temperature (+25 °C), nominal supply voltages. Including voltage outputs 3-state mode. supply voltages must present. 3-state outputs into 3-state mode when grounded. Accounts voltage drop supply lines. Only allowed short time period. Minimum condition maximum condition
Table converter electrical characteristics VDDA unless otherwise specified; unless otherwise specified; converter frequency MHz. Symbol Ciss EL(adj)
Parameter analog input voltage analog input capacitance differential non-linearity integral non-linearity offset error gain error absolute error
Conditions
VDDA ±0.5
Unit
Conditions: VSSA VDDA monotonic, there missing codes. differential non-linearity (ED) difference between actual step width ideal step width. Figure integral no-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute voltage error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure
9397 14008
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
(LSBideal) offset error
VDDA VSSA 1024
002aab136
Example actual transfer curve. ideal transfer curve. Differential non-linearity (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
conversion characteristics.
9397 14008
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Dynamic characteristics
Table characteristics commercial, industrial, over specified ranges Symbol External clock fosc Tclk tCHCX tCLCX tCLCH tCHCL tr(O) tf(O) oscillator frequency oscillator clock period clock HIGH time clock time clock rise time clock fall time output rise time output fall time output fall time Tclk Tclk Parameter Conditions Unit
Port pins (except P0.2 P0.3)
I2C-bus pins (P0.2 P0.3)
Parameters valid over operating temperature range unless otherwise specified. capacitance from
9397 14008
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Timing
0.45
0.2VDD 0.2VDD tCHCX tCHCL tCLCX Tclk tCLCH
002aab137
External clock timing.
9397 14008
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Package outline
LQFP64: plastic profile quad flat package; leads; body SOT314-2
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 10.1 0.75 0.45 0.12 1.45 1.05 1.45 1.05
12.15 12.15 11.85 11.85
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT314-2 REFERENCES 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Package outline SOT314-2 (LQFP64).
9397 14008 Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Abbreviations
Table Acronym FIFO GPIO SRAM UART Acronym list Description Analog-to-Digital Converter Brown-Out Detection Central Processing Unit Digital-to-Analog Converter Debug Communications Channel First First General Purpose Input/Output Phase-Locked Loop Power-On Reset Pulse Width Modulator Random Access Memory Static Random Access Memory Universal Asynchronous Receiver/Transmitter Vector Interrupt Controller VLSI Peripheral
9397 14008
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
Rev. November 2004
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Revision history
Table Revision history Release date Data sheet status Change notice Doc. number Supersedes Preliminary data sheet 9397 14008 Document
LPC2131_2132_2138 20041118
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
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Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Data sheet status
Level Data sheet status Objective data Preliminary data Product status Development Qualification Definition This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Relevant changes will communicated Customer Product/Process Change Notification (CPCN).
Product data
Production
Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet data sheets describing multiple type numbers, highest-level product status determines data sheet status.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
Change Notification (CPCN). Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
Licenses
Purchase Philips I2C-bus components Purchase Philips I2C-bus components conveys license under Philips' I2C-bus patent components I2C-bus system provided system conforms I2C-bus specification defined Koninklijke Philips Electronics N.V. This specification ordered using code 9398 40011.
Disclaimers
Life support These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes products including circuits, standard cells, and/or software described contained herein order improve design and/or performance. When product full production (status `Production'), relevant changes will communicated Customer Product/Process
Trademarks
registered trademark ARM, Inc. ARM7TDMI-S trademark ARM, Inc. EmbeddedICE registered trademark ARM, Inc. Embedded Trace Macrocell trademark ARM, Inc. Microwire trademark National Semiconductors, Inc. RealMonitor trademark ARM, Inc. trademark Motorola, Inc. trademark Texas Instruments, Inc. Thumb registered trademark ARM, Inc.
Contact information
additional information, please visit: sales office addresses, send email
9397 14008
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Preliminary data sheet
Rev. November 2004
Philips Semiconductors
LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
Contents
6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 General description Features features Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-Chip Flash program memory On-Chip static Memory map. Interrupt controller connect block function select register (PINSEL0 0xE002C000) function select register (PINSEL1 0xE002C004) function select register (PINSEL2 0xE002C014) General purpose parallel I/O. 10-bit converter 10-bit converter UARTs I2C-bus serial controller serial controller. serial controller General purpose timers/counters Watchdog timer. Real-time clock Pulse width modulator System control Emulation debugging Limiting values. Static characteristics. Dynamic characteristics Timing Package outline Abbreviations Revision history Data sheet status Definitions Disclaimers Licenses Trademarks Contact information
Koninklijke Philips Electronics N.V. 2004
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights. Date release: November 2004 Document number: 9397 14008
Published U.S.A.
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