RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388 real-time

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RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388 real-time

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4/05
RTC/Supervisor with Trickle Charger Bytes EEPROM
DS1388 real-time clock (RTC), supervisor, EEPROM multifunction device that provides clock/calendar, programmable watchdog timer, powersupply monitor with reset, bytes EEPROM. clock provides hundredths seconds, seconds, minutes, hours, operates 24-hour 12-hour format with AM/PM indicator. calendar provides day, date, month, year information. date month automatically adjusted months with fewer than days, including corrections leap year. watchdog timer provides reset unresponsive microprocessor. programmable 10ms intervals from 0.01 99.99 seconds. temperaturecompensated voltage reference comparator circuit monitors status VCC. primary power failure detected, device automatically switches backup supply drives reset output active state. backup supply maintains time date operation absence VCC. When returns nominal levels, reset held period allow power supply processor stabilize. device also pushbutton reset controller, which debounces reset input signal. device accessed through serial interface. Fast (400kHz) Interface
Features
Counts Hundredths Seconds, Seconds, Minutes, Hours, Day, Date, Month, Year with Leap Year Compensation Valid 2100 Programmable Watchdog Timer Automatic Power-Fail Detect Switch Circuitry Reset Output with Pushbutton Reset Input Capability Bits EEPROM Integrated Trickle-Charge Capability Backup Supply Three Operating Voltages: 5.0V, 3.3V, 3.0V Timekeeping Voltage Down 1.3V -40°C +85°C Temperature Range Recognized
DS1388
Ordering Information
PART DS1388Z-3 DS1388Z-33 DS1388Z-5 DS1388Z-5+ DS1388Z-3+ TEMP RANGE PINPACKAGE MARK DS1388-3 DS138833 DS1388-5 DS1388-5 DS138833 DS1388-3
Applications
Portable Instruments Point-of-Sale Equipment Network Interface Cards Wireless Equipment
-40°C +85°C (150 mils) -40°C +85°C (150 mils) -40°C +85°C (150 mils) -40°C +85°C (150 mils) -40°C +85°C (150 mils)
DS1388Z-33+ -40°C +85°C (150 mils)
Configuration
VIEW
symbol near indicator indicates lead-free. Lead free.
Typical Operating Circuit
CRYSTAL
VBACKUP
DS1388
DS1388
VBACKUP
Purchase components from Maxim Integrated Products, Inc., sublicensed Associated Companies, conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
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Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
ABSOLUTE MAXIMUM RATINGS
Voltage Range Relative Ground .-0.3V +6.0V Voltage Range Inputs Relative Ground .-0.3V (VCC 0.3V) Operating Temperature Range (noncondensing) .-40°C +85°C Storage Temperature Range .-55°C +125°C Soldering Temperature .See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
-40°C +85°C, unless otherwise noted.) (Note
PARAMETER Supply Voltage SYMBOL (Note CONDITIONS DS1388Z-5 DS1388Z-33 DS1388Z-3 Logic Logic Pullup Voltage (SCL, SDA), VBACKUP Voltage Power-Fail Voltage VBACKUP (Note DS1388Z-5 (Note DS1388Z-33 DS1388Z-3 4.15 2.70 2.45 4.33 2.88 2.60 (Note (Note 2.97 -0.3 3.63 +0.3 4.50 2.97 2.70 UNITS
ELECTRICAL CHARACTERISTICS
(VCC VCC(MIN) VCC(MAX), -40°C +85°C, unless otherwise noted.) (Note
PARAMETER Trickle-Charger Current-Limiting Resistors Input Leakage (SCL) Leakage (SDA) Leakage (RST) Logic Output (VOL 0.15 VCC) SYMBOL ILORST IOLDOUT (Note (Notes (Note (Note -200 CONDITIONS 2000 4000 UNITS
RTC/Supervisor with Trickle Charger Bytes EEPROM
ELECTRICAL CHARACTERISTICS (continued)
(VCC VCC(MIN) VCC(MAX), -40°C +85°C, unless otherwise noted.) (Note
PARAMETER Logic Output SYMBOL IOLSIR CONDITIONS 0.4V 1.8V 1.3V 1.8V; DS1388Z-5 Active Current, EEPROM Read, Read/Write Access ICCER (Note DS1388Z-33 DS1388Z-3 DS1388Z-5 Active Current, EEPROM Write Cycle ICCEW (Note DS1388Z-33 DS1388Z-3 DS1388Z-5 Standby Current ICCS (Note DS1388Z-33 DS1388Z-3 VBACKUP Leakage Current (VBACKUP 3.7V, VCC(MAX)) EEPROM Write/Erase Cycles IBACKUPLKG +25°C (guaranteed design) -40°C +85°C (guaranteed design) 200k Cycles 0.70 0.65 UNITS
DS1388
ELECTRICAL CHARACTERISTICS
(VCC VBACKUP 3.7V, +25°C, unless otherwise noted.) (Note
PARAMETER VBACKUP Current, (EOSC VBACKUP Current, (EOSC (Data Retention) SYMBOL IBACKUP (Note CONDITIONS UNITS
IBACKUPDR
(Note
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
ELECTRICAL CHARACTERISTICS
(VCC VCC(MIN) VCC(MAX), -40°C +85°C, unless otherwise noted.) (Note
PARAMETER Clock Frequency Free Time Between STOP START Condition Hold Time (Repeated) START Condition (Note Period Clock HIGH Period Clock Setup Time Repeated START Condition Data Hold Time (Notes Data Setup Time (Note Rise Time Both Signals (Note Fall Time Both Signals (Note Setup Time STOP Condition Capacitive Load Each Line (Note Capacitance (SDA, SCL, RST) Pushbutton Debounce Reset Active Time EEPROM Write Cycle Time Oscillator Stop Flag (OSF) Delay (Note SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tSU:STO CI/O PBDB tRST tWEE tOSF +25°C Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode CONDITION 0.1CB 0.1CB 1000 UNITS
RTC/Supervisor with Trickle Charger Bytes EEPROM
POWER-UP/POWER-DOWN CHARACTERISTICS
-40°C +85°C) (Note (Figures
PARAMETER Detect Recognize Inputs (VCC Rising) Fall Time; VPF(MAX) VPF(MIN) Rise Time; VPF(MIN) VPF(MAX) SYMBOL tRST (Note CONDITIONS UNITS
DS1388
VPF(MAX) VPF(MIN)
tRPU tRST
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH IMPEDANCE OUTPUTS VALID VALID
Figure Power-Up/Down Timing
PBDB
tRST
Figure Pushbutton Reset Timing
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
WARNING: Under circumstances negative undershoots, amplitude, allowed when device write protection.
Note Note Note Note Note Note Note Note Note Note Note Note Note Note Limits -40°C guaranteed design production tested. voltages referenced ground. Measured typ, VBACKUP register 0Ah, block A5h. trickle-charge resistor allowed 3.63V should enabled. Measured typ, VBACKUP register 0Ah, block A6h. Measured typ, VBACKUP register 0Ah, block A7h. internal pullup resistor VCC. ICCA-SCL clocking frequency 400kHz. Specified with inactive. Measured with 32.768kHz crystal attached After this period, first clock pulse generated. device must internally provide hold time least 300ns signal (referred VIHMIN signal) bridge undefined region falling edge SCL. maximum tHD:DAT need only device does stretch period (tLOW) signal. fast-mode device used standard-mode system, requirement tSU:DAT 250ns must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line tR(MAX) tSU:DAT 1000 1250ns before line released. CB-total capacitance line parameter tOSF period time that oscillator must stopped flag over voltage range VCC(MAX) 1.3V VBACKUP 3.7V. oscillator disabled stopped, goes inactive after tRST plus startup time oscillator.
Note Note Note
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
Typical Operating Characteristics
(VCC +3.3V, +25°C, unless otherwise noted.)
IBACKUP SUPPLY CURRENT VOLTAGE VBACKUP
DS1388 toc01
IBACKUP SUPPLY CURRENT VOLTAGE TEMPERATURE
VBACKUP SUPPLY CURRENT (nA)
DS1388 toc02
SUPPLY CURRENT (nA)
VBACKUP
TEMPERATURE (°C)
OSCILLATOR FREQUENCY SUPPLY VOLTAGE
DS1388 toc03
FALLING DELAY
0.1V
DS1388 toc04
32768.45 32768.40 32768.35 FREQUENCY (Hz) 32768.30 32768.25 32768.20 32768.15 32768.10 32768.05 32768.00 SUPPLY
10,000
RESET DELAY (µs)
1000
0.01 FALLING (V/ms)
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
Description
NAME FUNCTION Connections Standard 32.768kHz Quartz Crystal. internal oscillator circuitry designed operation with crystal having specified load capacitance (CL) 6.0pF. input oscillator optionally connected external 32.768kHz oscillator. output internal oscillator, floated external oscillator connected Connection Secondary Power Supply. Supply voltage must held between 1.3V 5.5V proper operation. This connected primary cell, such lithium button cell. Additionally, this connected rechargeable cell super when used with trickle-charge feature. used, this must connected ground. recognized ensure against reverse charging current when used with lithium battery. (www.maxim-ic.com/qa/info/ul/) Ground Serial Data Output. input/output serial interface. This open drain requires external pullup resistor. Serial Clock Input. clock input interface used synchronize data movement serial interface. Active-Low, Open-Drain Reset Output. This indicates status relative specification. falls below VPF, driven low. When exceeds VPF, tRST, driven high impedance. active-low, open-drain output combined with debounced pushbutton input function. This activated pushbutton reset request. internal nominal value pullup resistor VCC. external pullup resistors should connected. crystal oscillator disabled, startup time oscillator added tRST delay. Power Primary Power Supply
VBACKUP
Block Diagram
BLOCK OSCILLATOR/ CLOCK DIVIDER BLOCK BLOCK
VBACKUP POWER CONTROL TRICKLE CHARGER
WATCHDOG TIMER
EEPROM
EEPROM
STAT/CTRL/TRICKLE
INTERFACE
EEPROM INTERFACE
DS1388
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
Detailed Description
DS1388 RTC, supervisor, EEPROM multifunction device that provides clock/calendar, programmable watchdog timer, power-supply monitor with reset, bytes EEPROM. clock provides hundredths seconds, seconds, minutes, hours, operates 24-hour 12-hour format with AM/PM indicator. calendar provides day, date, month, year information. date month automatically adjusted months with fewer than days, including corrections leap year. watchdog timer provides reset unresponsive microprocessor. programmable 10ms intervals from 0.01 99.99 seconds. temperature-compensated voltage reference comparator circuit monitors status VCC. primary power failure detected, device automatically switches backup supply drives reset output active state. When returns nominal levels, reset held period allow power supply processor stabilize. device also pushbutton reset controller, which debounces reset input signal. device accessed through serial interface. device power switched from VBACKUP when drops below greater than VBACKUP, device power switched from VBACKUP when drops below VBACKUP. registers maintained from VBACKUP source until returned nominal levels (Table After returns above VPF, read write access allowed after goes high (Figure
Table Power Control
SUPPLY CONDITION VPF, VBACKPUP VPF, VBACKUP VPF, VBACKUP VPF, VBACKUP READ/WRITE ACCESS POWERED VBACKUP
Oscillator Circuit
DS1388 uses external 32.768kHz crystal. oscillator circuit does require external resistors capacitors operate. Table specifies several crystal parameters external crystal, Figure shows functional schematic oscillator circuit. Using crystal with specified characteristics, startup time usually less than second.
Operation
DS1388 operates slave device bus. Access obtained implementing START condition providing device identification code followed data. Subsequent registers accessed sequentially until STOP condition executed. Block Diagram, which shows main elements serial real-time clock.
Table Crystal Specifications*
PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL 32.768 UNITS
Power Control
power-control function provided precise, temperature-compensated voltage reference comparator circuit that monitors level. device fully accessible data written read when greater than VPF. However, when falls below VPF, internal clock registers blocked from access. less than VBACKUP,
*The crystal, traces, crystal input pins should isolated from generating signals. Refer Application Note Crystal Considerations Dallas Real-Time Clocks additional specifications.
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
LOCAL GROUND PLANE (LAYER
COUNTDOWN CHAIN
CRYSTAL
REGISTERS
NOTE: AVOID ROUTING SIGNAL LINES CROSSHATCHED AREA (UPPER LEFT QUADRANT) PACKAGE UNLESS THERE GROUND PLANE BETWEEN SIGNAL LINE DEVICE PACKAGE.
DS1388
CRYSTAL
Figure Oscillator Circuit Showing Internal Bias Network
Figure Layout Example
Clock Accuracy
accuracy clock dependent upon accuracy crystal accuracy match between capacitive load oscillator circuit capacitive load which crystal trimmed. Additional error added crystal frequency drift caused temperature shifts. External circuit noise coupled into oscillator circuit result clock running fast. Figure shows typical board layout isolation crystal oscillator from noise. Refer Application Note Crystal Considerations with Dallas Real-Time Clocks detailed information.
Address
Figure shows address DS1388. memory divided into three blocks. memory block accessed determined value block address bits slave address byte. timekeeping registers reside block During multibyte access timekeeping registers, when internal address pointer reaches 0Ch, wraps around location 00h. START address pointer incrementing location 00h, current time transferred second registers. time information read from these secondary registers, while clock continue run. This eliminates need reread registers case main registers update during
read. EEPROM divided into 256-byte blocks located blocks During multibyte read EEPROM registers, when internal address pointer reaches FFh, wraps around location block EEPROM specified block address. During multibyte write EEPROM registers, when internal address pointer reaches current 8-byte EEPROM page, wraps around beginning EEPROM page. Write Operation section details. avoid rollover issues when writing time date registers, registers should written before hundredths-of-seconds register reaches (BCD).
Hundredths-of-Seconds Generator
hundredths-of-seconds generator circuit shown Block Diagram state machine that divides incoming frequency (4096Hz) cycles cycle. This produces 100Hz output that slightly during short term, exactly correct every 250ms. divide ratio given Ratio 40.96 Thus, long-term average frequency output exactly 100Hz.
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
ADDRESS WORD 12/24 Year Watchdog Tenths Seconds FUNCTION Hundredths Seconds Seconds Minutes Hours Date Month Year Watchdog Hundredth Seconds Watchdog Seconds ROUT0 WD/RST Trickle Charger Flag Control EEPROM EEPROM RANGE 00-99 00-59 00-59 1-12+ AM/PM 00-23 01-07 00-31 01-12 00-99 00-99
Tenth Seconds Seconds Minutes Hour
Hundredths Seconds Seconds Minutes Hours Date Month Year Watchdog Hundredths Seconds
Hour Date Month
00-FFH 00-FFH
Watchdog Tenths Seconds TCS3 EOSC TCS2 TCS1 TCS0
Watchdog Seconds ROUT1
00-99 00-FFh 00-FFh
EEPROM EEPROM
Figure Address Note: Unless otherwise specified, state registers defined when power (VCC VBACKUP) first applied. General-purpose read/write bit. Always reads zero.
Clock Calendar
time calendar information obtained reading appropriate register bytes. Figure illustrates registers. time calendar initialized writing appropriate register bytes. contents time calendar registers binary-coded decimal (BCD) format. month date automatically adjusted months with fewer than days, including corrections leap years through 2099. day-of-week register increments midnight. Values that correspond day-of-week
user-defined must sequential (i.e., equals Sunday, then equals Monday, on). Illogical time date entries result undefined operation. DS1388 either 12-hour 24hour mode. hours register defined 24-hour mode-select bit. When high, 12-hour mode selected. 12-hour mode, AM/PM with logic-high being 24-hour mode, second 10-hour (20-23 hours). Changing 12/24 requires that hours data re-entered proper format.
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
Watchdog Alarm Counter
contents watchdog alarm counter, which separate two-byte down counter, accessed address range 08h-09h block programmable 10ms intervals from 0.01 99.99 seconds. When this counter written, both counter seed register loaded with desired value. When counter reloaded, uses value seed register. When counter read, current counter value latched into register, which output serial data line while counter continues decrement. counter needed, disabled used 16-bit cache battery-backed setting control register logic bits watchdog alarm counter written zero when counter disabled set. When control register logic non-zero value written into watchdog registers, watchdog alarm counter decrements every 1/100 second, until reaches zero. this point, flag register set. WD/RST pulsed tRST access DS1388 inhibited. tRST, becomes high impedance, read/write access DS1388 enabled. flag remains until cleared writing logic watchdog alarm counter reloaded restarted before counter reaches zero reading writing watchdog alarm counter registers. must zero before writing watchdog registers. After writing watchdog registers, must enable watchdog. DS1388 provides pushbutton switch connected output pin. When DS1388 reset cycle, continuously monitors signal low-going edge. edge detected, part debounces switch pulling inhibits read/write access. After internal timer expired, part continues monitor line. line still low, continues monitor line looking rising edge. Upon detecting release, part forces holds tRST.
Special-Purpose Registers
DS1388 three additional registers (control, flag, trickle charger) that control real-time clock, watchdog, trickle charger.
Flag Register (00Bh)
Oscillator Stop Flag (OSF). logic this indicates that oscillator stopped stopped some period time used judge validity clock calendar data. This edge triggered logic when internal circuitry senses oscillator transitioned from normal state STOP condition. following examples conditions that cause set: first time power applied. voltage present both VBACKUP insufficient support oscillation. EOSC turned off. External influences crystal (i.e., noise, leakage, etc.). This remains logic until written logic This only written logic Attempting write logic leaves value unchanged. Watchdog Alarm Flag (WF). logic this indicates that watchdog counter reached zero. WD/RST pulses tRST when watchdog counter reaches zero sets completion pulse, remains logic Writing this logic clears flag. This only written logic Attempting write logic leaves value unchanged. Bits These bits read zero cannot modified.
Power-Up/Down, Reset, Pushbutton Reset Functions
precision temperature-compensated reference comparator circuit monitors status VCC. When out-of-tolerance condition occurs, internal power-fail signal generated that blocks read/write access device forces low. When returns in-tolerance condition, internal power-fail signal held active tRST allow power supply stabilize, held low. EOSC logic disable oscillator battery-backup mode), internal power-fail signal kept active tRST plus oscillator startup time.
Flag Register (00Bh)
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
Control Register (00Ch)
EOSC WD/RST
Control Register (00Ch)
Enable Oscillator (EOSC). When logic oscillator started. When logic oscillator stopped when DS1388 switches battery power. This setting used conserve battery power when timekeeping operation required. This cleared (logic when power first applied. When DS1388 powered VCC, oscillator always regardless status EOSC bit. Bits These bits read zero cannot modified. Watchdog Enable (WDE). When logic one, watchdog counter enabled. When logic watchdog counter disabled, registers used RAM. This cleared (logic when power first applied. Watchdog Reset (WD/RST). This enables watchdog alarm output drive pin. When WD/RST logic pulses tRST watchdog counter reaches zero. When WD/RST logic driven watchdog alarm; only watchdog flag (WF) flag register logic This logic when power first applied.
Trickle-Charge Register (00Ah)
simplified schematic Figure shows basic components trickle charger. trickle-charge select (TCS) bits (bits 4-7) control selection
trickle charger. prevent accidental enabling, only pattern 1010 enables trickle charger. other patterns disable trickle charger disabled when power first applied. diode-select (DS) bits (bits select whether diode connected between VBACKUP. diode selected, diode selected. ROUT bits (bits select value resistor connected between VBACKUP. Table shows resistor selected resistor select (ROUT) bits diode selected diode-select (DS) bits. Warning: ROUT value must selected whenever greater than 3.63V. user determines diode resistor selection according maximum current desired battery super charging. maximum charging current calculated illustrated following example. Assume that system power supply 3.3V applied super connected VBACKUP. Also, assume that trickle charger been enabled with diode resistor between VBACKUP. maximum current IMAX would calculated follows: IMAX (3.3V diode drop) (3.3V 0.7V) 1.3mA super charges, voltage drop between VBACKUP decreases therefore charge current decreases.
Table Trickle-Charge Register
TCS3 TCS2 TCS1 TCS0 ROUT1 ROUT0 Disabled Disabled Disabled diode, resistor diode, resistor diode, resistor diode, resistor diode, resistor diode, resistor Initial default value-disabled FUNCTION
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
TRICKLE-CHARGE REGISTER (00Ah) TCS3 TCS2 TCS1 TCS0 ROUT1 ROUT0 TCS0-3 TRICKLE-CHARGE SELECT DS0-1 DIODE SELECT ROUT0-1 RESISTOR SELECT
SELECT NOTE: ONLY 1010b ENABLES CHARGER
SELECT
SELECT
VBACKUP
Figure Programmable Trickle Charger
EEPROM
DS1388 provides bytes EEPROM organized into blocks bytes. Each 256-byte block divided into pages consisting bytes page. EEPROM written page time. Page write operations limited writing bytes within single physical page, regardless number bytes actually being written. Physical page boundaries start addresses that integer multiples page size bytes) addresses that integer multiples [page size -1]. example, page contains word addresses 07h. Similarly, page contains word addresses 0Fh. page write command attempts write across physical page boundary, result that data wraps around beginning current page (overwriting data previously stored there), instead being written next page might expected. Therefore, necessary application software prevent page write operations that would attempt cross page boundary.
operates slave bus. Connections made through open-drain lines SCL. Within specifications, standard mode (100kHz maximum clock rate) fast mode (400kHz maximum clock rate) defined. DS1388 works both modes. following protocol been defined (Figure Data transfer initiated only when busy. During data transfer, data line must remain stable whenever clock line high. Changes data line while clock line high will interpreted control signals. Accordingly, following conditions have been defined: busy: Both data clock lines remain high. Start data transfer: change state data line from high low, while clock line high, defines START condition. Stop data transfer: change state data line from high, while clock line high, defines STOP condition. Data valid: state data line represents valid data when, after START condition, data line stable duration high period clock signal. data line must changed during period clock signal. There clock pulse data.
Serial Data
DS1388 supports bidirectional data transmission protocol. device that sends data onto defined transmitter device receiving data defined receiver. device that controls message called master. devices that controlled master slaves. must controlled master device that generates serial clock (SCL), controls access, generates START STOP conditions. DS1388
RTC/Supervisor with Trickle Charger Bytes EEPROM
Each data transfer initiated with START condition terminated with STOP condition. number data bytes transferred between START STOP conditions limited, determined master device. information transferred byte-wise each receiver acknowledges with ninth bit. Acknowledge: Each receiving device, when addressed, obliged generate acknowledge (ACK) after reception each byte. master device must generate extra clock pulse, which associated with this acknowledge bit. DS1388 does generate acknowledge bits access EEPROM attempted during internal programming cycle. device that acknowledges must pull down line during acknowledge clock pulse such that line stable during high period acknowledge-related clock pulse. course, setup hold times must taken into account. master must signal data slave generating not-acknowledge (NACK) last byte that been clocked slave. this case, slave must leave data line high enable master generate STOP condition. Figures detail data transfer accomplished bus. Depending upon state bit, types data transfer possible: Data transfer from master transmitter slave receiver. first byte transmitted master slave address. Next follows number data bytes. slave returns acknowledge after each received byte. Data transferred with most significant (MSB) first. Data transfer from slave transmitter master receiver. first byte (the slave address) transmitted master. slave then returns acknowledge bit. Next follows number data bytes transmitted slave master. master returns acknowledge after received bytes other than last byte. last received byte, NACK returned. master device generates serial clock pulses START STOP conditions. transfer ended with STOP condition with repeated START condition. Since repeated START condition also beginning next serial transfer, released. Data transferred with most significant (MSB) first.
DS1388
SLAVE ADDRESS DIRECTION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER START CONDITION REPEATED MORE BYTES TRANSFERED STOP CONDITION REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure Data Transfer Overview
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
Device Addressing
slave address byte first byte received following START condition from master device. slave address byte consists 4-bit control code. DS1388, this 1101 binary read write operations. next three bits slave address byte block select bits (B2, B0). always logic DS1388. These bits used master device select which three blocks memory accessed. These bits three most significant bits word address. last slave address byte defines operation performed. When read operation selected; when write operation selected. Receiver Mode section. master transmits data byte, with DS1388 acknowledging transfer ninth clock cycle. master then generates STOP condition terminate data write. This initiates internal write cycle, and, write EEPROM, DS1388 does generate acknowledge signals during internal EEPROM write cycle.
EEPROM Page Write
write-slave address byte, word address, first data byte transmitted DS1388 same byte write. instead generating STOP condition, master transmits data bytes DS1388, which temporarily stored on-chip page buffer written into memory after master transmitted STOP condition. Data bytes within page that written remain unchanged. internal address pointer automatically increments after each byte written. master should transmit more than data bytes prior generating STOP condition, address pointer rolls over previously received data overwritten. with byte write operation, once STOP condition received internal write cycle begins.
Write Operation
Slave Receiver Mode (Write Mode)
Following START condition from master, device code bits); block address bits); bit, which logic-low, placed onto master transmitter. This indicates DS1388 that byte with word address follows after DS1388 generated acknowledge during ninth clock cycle. next byte transmitted master word address will internal address pointer DS1388, with DS1388 acknowledging transfer ninth clock cycle. master device then transmit zero more bytes data, with DS1388 acknowledging transfer ninth clock cycle. master generates STOP condition terminate data write.
Multibyte Write
Writing multiple bytes works much same EEPROM page write, except that entire contents block written once. 8-byte page size limitation does apply block master should transmit more bytes than exists block prior generating STOP condition, internal address pointer rolls over previously received data overwritten. with byte write operation, once STOP condition received internal write cycle begins.
Byte Write
write-slave address byte word address transmitted DS1388 described Slave
Slave Address Byte
OPERATION Read Clock Write Clock Read Lower Block EEPROM Write Lower Block EEPROM Read Upper Block EEPROM Write Upper Block EEPROM CONTROL CODE 1101 1101 1101 1101 1101 1101 BLOCK SELECT
RTC/Supervisor with Trickle Charger Bytes EEPROM
Acknowledge Polling
Since DS1388 does acknowledge during EEPROM write cycle, acknowledge polling used determine when cycle complete (this feature used maximize throughput). Once master issues STOP condition write command, DS1388 initiates internally timed write cycle. polling initiated immediately. This involves master sending START condition, followed slave address byte write command (R/W EEPROM. device still busy with write cycle, then NACK returned. cycle complete, then device returns master then proceed with next read write command. registers block accessible during EEPROM write cycle.
Sequential Read
Sequential reads initiated same random read except that after DS1388 transmits first data byte, master issues acknowledge opposed STOP condition random read. This directs DS1388 transmit next sequentially addressed 8-bit byte. provide sequential reads, DS1388 contains internal address pointer, which incremented completion each operation. This allows entire memory contents block specified slave address serially read during operation. master terminates read generating NACK followed STOP condition. page boundaries exist read operations. When address pointer reaches EEPROM block (FFh), address pointer wraps beginning (00h) same block. DS1388 operate modes illustrated Figure
DS1388
Read Operation
Read operations initiated same write operations with exception that slave address There three basic types read operations: current address read, random read, sequential read.
Current Address Read
DS1388 contains address pointer that maintains last address accessed, internally incremented Therefore, previous access (either read write operation) address next current address read operation would access data from address Upon receipt slave address with DS1388 issues acknowledge transmits 8-bit data byte. master issues NACK followed STOP condition, DS1388 discontinues transmission.
<WORD <SLAVE ADDRESS (n)> <DATA (n)> <DATA <DATA ADDRESS> 1101BBB XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BLOCK SELECT DATA TRANSFERRED START BYTES ACKNOWLEDGE) ACKNOWLEDGE STOP READ/WRITE DIRECTION ADDRESS
Figure Slave Receiver Mode (Write Mode)
Random Read
Random read operations allow master access memory location random manner. perform this type read operation, first word address must set. This done sending word address DS1388 part write operation. After word address sent, master generates START condition following acknowledge. This terminates write operation, before internal address pointer set. Then master issues slave address byte again with DS1388 then issues acknowledge transmits 8-bit data byte. master issues NACK followed STOP condition, DS1388 discontinues transmission.
<SLAVE <DATA (n)> <DATA <DATA <DATA ADDRESS> 1101BBB XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DATA TRANSFERRED BLOCK SELECT BYTES ACKNOWLEDGE) START NOTE: LAST DATA BYTE FOLLOWED ACKNOWLEDGE ACKNOWLEDGE SIGNAL STOP ACKNOWLEDGE READ/WRITE DIRECTION ADDRESS
Figure Slave Transmitter Mode (Read Mode)
<R/W>
<R/W>
RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388
Thermal Information
Theta-JA: +170°C/W Theta-JC: +40°C/W
Chip Information
TRANSISTOR COUNT: 25,527 SUBSTRATE CONNECTED GROUND PROCESS: CMOS
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information,
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2005 Maxim Integrated Products Printed registered trademark Maxim Integrated Products, Inc.
registered trademark Dallas Semiconductor Corporation.

RTC/Supervisor with Trickle Charger Bytes EEPROM DS1388 real-time

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