Non-Volatile SRAM MODULE 2Mbit (128K 16-Bit), 40pin-Dip, Part HMN12816

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Non-Volatile SRAM MODULE 2Mbit (128K 16-Bit), 40pin-Dip, Part HMN12816

Datasheet Thumbnail

Top Searches for this datasheet

HMN12816D
Non-Volatile SRAM MODULE 2Mbit (128K 16-Bit), 40pin-Dip, Part HMN12816D
HMN12816D 128K nonvolatile SRAM's 2,097,152-bit fully static, nonvolatile SRAM's, organized 131,072 words bits. Each NVSRAM self contained lithium energy source control circuitry which constantly monitors out-of-tolerance condition. When such condition occurs, lithium energy source automatically switched write protection unconditionally enabled prevent data corruption. DIP-package HMN12816D devices used place solutions which build nonvolatile 128Kx16 memory utilizing variety discrete components. There limit number write cycles that executed additional support circuitry required microprocessor interfacing. HMN12816D uses extremely standby current CMOS SRAM's, coupled with small lithium coin cells provide nonvolatility without long write-cycle times write-cycle limitations associated with EEPROM.
FEATURES
Access time 120, 150ns High-density design 256KByte Design Battery internally isolated until power applied Industry-standard 40-pin 128K pinout Unlimited write cycles Data retention absence 10-years minimum data retention absence power Automatic write-protection during power-up/power-down cycles Data automatically protected during power loss Conventional SRAM operation; unlimited write cycles
ASSIGNMENT
/CEU /CEL DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
OPTIONS
Timing
MARKING
-120 -150
40-pin Encapsulated Package
www.hbe.co.kr Rev. (April, 2002)
HANBit Electronics Co.,Ltd
HMN12816D
FUNCTIONAL DESCRIPTION
HMN12816D devices execute read cycle whenever (Write Enable) inactive (high) either/both /CEU /CEL (Chip Enables) active (low) (Output Enable) active (low). unique address specified address inputs (A0-A16) defines which 131,072 words data accessed. status /CEU /CEL determines whether part addressed word accessed. /CEU active with /CEL inactive, then only upper byte addressed word accessed. /CEU inactive with /CEL active, then only lower byte addressed word accessed. both /CEU /CEL inputs active (low), then entire 16-bit word accessed. Valid data will available data output drivers within tACC (Access Time) after last address input signal stable, providing that /CEU, /CEL access times also satisfied. /CEU, /CEL, access times satisfied, then data access must measured from later occurring signal, limiting parameter either /CEU, /CEL, rather than address access. HMN12816D devices execute write cycle whenever either/both /CEU /CEL active (low) after address inputs stable. unique address specified address inputs (A0-A16) defines which 131,072 words data accessed. status /CEU /CEL determines whether part addressed word accessed. /CEU active with /CEL inactive, then only upper byte addressed word accessed. /CEU inactive with /CEL active, then only lower byte addressed word accessed. both /CEU /CEL inputs active (low), then entire 16-bit word accessed. write cycle terminated earlier rising edge /CEU and/or /CEL, address inputs must kept valid throughout write cycle. must return high state minimum recovery time (tWR before another cycle initiated. control signal should kept inactive (high) during write cycles avoid contention. However, output drivers enabled (/CEU and/or /CEL, active) then will disable outputs tODW from falling edge.
DESCRIPTION
A0-A16 Address Inputs /CEU Chip enable upper byte /CEL Chip enable lower byte DQ0-DQ15 Data input Data output Write enable Output enable power supply Ground
/CEL /CEU
BLOCK DIAGRAM
128K SRAM Block Power /CEL
A0-A16 DQ0-DQ15
/CEU
Power Fail Control Lithium Cell
www.hbe.co.kr Rev. (April, 2002)
HANBit Electronics Co.,Ltd
HMN12816D
READ/WRITE FUNCTION
CYCLE PERFORMED Output Disabled
/CEL
/CEU
CURRENT ICCO ICCO
DQ0-DQ7 High-Z Output Output High-Z Input
DQ8-DQ15 High-Z Output High-Z Output Input High-Z Input High-Z
Read Cycle
ICCO ICCS
Input High-Z High-Z
Write Cycle
Output Disabled
DATA RETENTION MODE
HMN12816D provides full functional capability greater than volts write protects 4.25volts. Data maintained absence without additional support circuitry. nonvolatile static RAMs constantly monitor VCC. Should supply volt-age decay, SRAM's automatically write protect themselves, inputs become "don't care," out-puts become high impedance. falls below approximately volts, power switching circuit connects lithium energy source retain data. During power-up, when rises above approximately volts, power switching circuit connects external disconnects lithium energy source.
ABSOLUTE MAXIMUM RATINGS
PARAMETER voltage applied relative Voltage applied excluding relative Operating temperature Storage temperature Temperature under bias Soldering temperature SYMBOL TOPR TSTG TBIAS TSOLDER RATING -0.3V 7.0V -0.3V 7.0V 70°C -40°C 70°C -10°C 70°C 260°C second VCC+0.3 CONDITIONS
NOTE: Permanent device damage occur Absolute Maximum Ratings exceeded. Functional operation should restricted Recommended Operating Conditions detailed this data sheet. Exposure higher than recommended voltage extended periods time could affect device reliability.
www.hbe.co.kr Rev. (April, 2002)
HANBit Electronics Co.,Ltd
RECOMMENDED OPERATING CONDITIONS TOPR
PARAMETER Supply Voltage Ground Input high voltage Input voltage SYMBOL 4.5V -0.3 TYPICAL 5.0V
HMN12816D
5.5V Vcc+0.3V 0.8V
NOTE: Typical values indicate operation
ELECTRICAL CHARACTERISTICS (TA=
PARAMETER Input Leakage Current Leakage Current Output Current 2.4V Output Current @0.4V Standby Current /CEU,/CEL=2.2V Standby Current /CEU,/CEL=Vcc-0.5V Operating Current ICCS2 ICCO1 SYMBOL ICCS1 -2.0 -1.0 -1.0 TYP. +2.0 +1.0 UNIT
CAPACITANCE (TA=25 f=1MHz, VCC=5.0V)
DESCRIPTION Input Capacitance Input/Output Capacitance SYMBOL CI/O UNITS
www.hbe.co.kr Rev. (April, 2002)
HANBit Electronics Co.,Ltd
READ CYCLE (TA= TOPR, VCCmin VCCmax
PARAMETER Read Cycle Time Address Access Time Chip enable access time Output enable Output valid Chip enable output Output enable output Chip disable output high Output disable output high Output hold from address change SYMBOL tACC tACE tCLZ tOLZ tCHZ tOHZ Output load Output load Output load Output load Output load Output load Output load Output load CONDITIONS -120
HMN12816D
-150
UNIT
WRITE CYCLE (TA= TOPR, Vccmin Vccmax
PARAMETER Write Cycle Time Chip enable write Address setup time Address valid write Write pulse width Write recovery time (write cycle Write recovery time (write cycle Data valid write Data hold time (write cycle Data hold time (write cycle Write enabled output high Output active from write SYMBOL tWR1 tWR2 tDH1 tDH2 Note Note Note Note Note Note Note Note Note Note CONDITIONS -120 -150
NOTE: write ends earlier transition going high going high. write occurs during overlap allow /WE. write begins later transition going going low. Either tWR1 tWR2 must met. Either tDH1 tDH2 must met. goes simultaneously with going after going low, outputs remain highimpedance state.
www.hbe.co.kr Rev. (April, 2002)
HANBit Electronics Co.,Ltd
HMN12816D
TIMING WAVEFORM READ CYCLE
Address tACC /CEU, /CEL DOUT tCOE Data Valid
WRITE CYCLE NO.1
Address tWR1 /CEU,/CEL tODW DOUT Data Undefined Data-in Valid tOEW High-Z tDH1
www.hbe.co.kr Rev. (April, 2002)
HANBit Electronics Co.,Ltd
HMN12816D
WRITE CYCLE NO.2
Address tWR2 /CEU,/CEL tCOE DOUT tODW High-Z Data-in Valid tDH2
POWER-DOWN/POWER-UP CONDITION
3.2V /CEU,/CEL tREC
Data Retention Time
www.hbe.co.kr Rev. (April, 2002)
HANBit Electronics Co.,Ltd
POWER-DOWN/POWER-UP TIMING(tA= 70OC)
PARAMETER /CEU,/CEL before Power-Down Slew from Slew from /CEU,/CEL after Power-Up SYMBOL tREC TYP.
HMN12816D
UNITS
NOTES
(tA= PARAMETER Expected Data Retention Time WARNING: Under circumstance negative undershoots, amplitude, allowed when device battery backup mode. SYMBOL UNITS years NOTES
NOTES: high read cycle. during write cycle, output buffers remain high impedance state. specified logical /CEU /CEL /WE. measured from latter /CEU, /CEL going earlier /CEU, /CEL going high. measured from earlier /CEU /CEL going high. These parameters sampled with load 100% tested. /CEU /CEL transition occurs simultaneously with later than transition output buffers remain high impedance state during this period. /CEU /CEL high transition occurs prior simultaneously with high transition, output buffers remain high impedance state during this period. transition occurs prior simultaneously with /CEU /CEL transition, output buffers remain high impedance state during this period. Each HMN12816D built-in switch that disconnects lithium source until first applied user. expected defined accumulative time absence starting from time power first applied user. electrical characteristics valid over full operating temperature range 70_C. power down condition voltage exceed voltage tWR1, tDH1 measured from going high. tWR2, tDH2 measured from /CEU /CEL going high.
www.hbe.co.kr Rev. (April, 2002)
HANBit Electronics Co.,Ltd
HMN12816D
PACKAGE DIMENSION
Dimension 2.070 0.710 0.365 0.015 0.008 0.590 0.017 0.090 0.080 0.120 2.100 0.740 0.375 0.013 0.630 0.023 0.110 0.110 0.150
dimensions inches.
ODERING INFORMATION
Operating Temp. Blank Commercial Industrial (-40 85°C) Speed options
type package Device 128K Nonvolatile SRAM HANBit Memory Module
www.hbe.co.kr Rev. (April, 2002)
HANBit Electronics Co.,Ltd

Non-Volatile SRAM MODULE 2Mbit (128K 16-Bit), 40pin-Dip, Part HMN12816

Top Searches for this datasheet

Other recent searches