High-Performance Fixed-Point Digital Signal Processor (DSP) SMJ32
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
High-Performance Fixed-Point Digital
Signal Processor (DSP) SMJ320C62x 5-ns Instruction Cycle Time 200-MHz Clock Rate Eight 32-Bit Instructions/Cycle 1600 Million Instructions Second (MIPS) 429-Pin Ball Grid Array (BGA) Package (GLP Suffix) VelociTI Advanced Very-Long-InstructionWord (VLIW) C62x Core Eight Highly Independent Functional Units: Arithmetic Logic Units (ALUs) (32-/40-Bit) 16-Bit Multipliers (32-Bit Result) Load-Store Architecture With 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size Instructions Conditional Instruction Features Byte-Addressable (8-, 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation Bit-Field Extract, Set, Clear Bit-Counting Normalization 7M-Bit On-Chip SRAM 3M-Bit Internal Program/Cache (96K 32-Bit Instructions) 4M-Bit Dual-Access Internal Data (512K Bytes) Organized 256K-Byte Blocks Improved Concurrency Flexible Phase-Locked-Loop (PLL) Clock Generator
32-Bit External Memory Interface (EMIF)
Glueless Interface Synchronous Memories: SDRAM SBSRAM Glueless Interface Asynchronous Memories: SRAM EPROM 52M-Byte Addressable External Memory Space Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With Auxiliary Channel 32-Bit Expansion Glueless/Low-Glue Interface Popular Bridge Chips Glueless/Low-Glue Interface Popular Synchronous Asynchronous Microprocessor Buses Master/Slave Functionality Glueless Interface Synchronous FIFOs Asynchronous Peripherals Three Multichannel Buffered Serial Ports (McBSPs) Direct Interface T1/E1, MVIP, SCSA Framers ST-Bus-Switching Compatible Channels Each AC97-Compatible Serial-Peripheral Interface (SPI) Compatible (Motorola) 32-Bit General-Purpose Timers IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 0.15-µm/5-Level Metal Process CMOS Technology 3.3-V I/Os, 1.5-V Internal
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
SMJ320C62x, VelociTI, C62x trademarks Texas Instruments. Motorola trademark Motorola, Inc. trademarks property their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port Boundary Scan Architecture.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2002, Texas Instruments Incorporated
products compliant 38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
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Table Contents package (bottom view) description device characteristics functional (DSP core) block diagram (DSP core) description memory summary peripheral register descriptions synchronization events interrupt sources interrupt selector signal groups description signal descriptions development support documentation support clock power-supply sequencing absolute maximum ratings over operating case temperature ranges recommended operating conditions electrical characteristics over recommended ranges supply voltage operating case temperature signal transition levels timing parameters board routing analysis input output clocks asynchronous memory timing synchronous-burst memory timing synchronous DRAM timing HOLD/HOLDA timing reset timing external interrupt timing expansion synchronous FIFO timing expansion asynchronous peripheral timing expansion synchronous host-port timing expansion asynchronous host-port timing XHOLD/XHOLDA timing multichannel buffered serial port timing DMAC, timer, power-down timing JTAG test-port timing mechanical data
parameter measurement information
package (bottom view)
429-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW)
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
description
SMJ320C6203 device part SMJ320C62x fixed-point generation SMJ320C6000 platform. C62x devices based high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed Texas Instruments (TI), making these DSPs excellent choice multichannel multifunction applications. SMJ320C62x offers cost-effective solutions high-performance DSP-programming challenges. SMJ320C6203 performance capability 1600 MIPS clock rate MHz. C6203 possesses operational flexibility high-speed controllers numerical capability array processors. This processor general-purpose registers 32-bit word length eight highly independent functional units. eight functional units provide arithmetic logic units (ALUs) high degree parallelism 16-bit multipliers 32-bit result. C6203 produce multiply-accumulates (MACs) cycle total million MACs second (MMACS). C6203 also application-specific hardware logic, on-chip memory, additional on-chip peripherals. C6203 device program memory consists blocks, with 256K-byte block configured memory-mapped program space, other 128K-byte block user-configurable cache memory-mapped program space. Data memory C6203 consists 256K-byte blocks RAM. C6203 device powerful diverse peripherals. peripheral includes three multichannel buffered serial ports (McBSPs), general-purpose timers, 32-bit expansion that offers ease interface synchronous asynchronous industry-standard host protocols, glueless 32-bit external memory interface (EMIF) capable interfacing SDRAM SBSRAM asynchronous peripherals. C62x devices have complete development tools that includes: compiler, assembly optimizer simplify programming scheduling, Windows debugger interface visibility into source code execution.
device characteristics
Table provides overview SMJ320C6203 DSP. table shows significant features device, including capacity on-chip RAM, peripherals, execution time, package type with count. This data sheet focuses functionality SMJ320C6203 device. more details C6000 part numbering, Figure
SMJ320C6000 C6000 trademarks Texas Instruments. Windows registered trademark Microsoft Corporation.
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device characteristics (continued)
Table Characteristics C6203
HARDWARE FEATURES EMIF Peripherals Expansion McBSPs 32-Bit Timers Size (Bytes) Internal Program Memory C6203 4-Channel With Throughput Enhancements 384K Block 256K-Byte Mapped Program Block 128K-Byte Cache/Mapped Program 512K Blocks: Four 16-Bit Banks Block 50/50 Split 0x0003 (6203-200) Bypass (x1), x10, 0.15
Organization
Size (Bytes) Internal Data Memory Organization
Frequency Cycle Time Voltage Options Package Process Technology Product Status
Control Status Register (CSR.[31:16]) Core CLKIN frequency multiplier [Bypass (x1), x10, x11] Product Preview (PP) Advance Information (AI) Production Data (PD)
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functional (DSP core) block diagram
SDRAM SBSRAM
C6203 Digital Signal Processors
Program Access/Cache Controller Internal Program Memory Blocks Program/Cache (384K Bytes)
SRAM ROM/FLASH Devices
External Memory Interface (EMIF)
C62x (DSP Core) Timer Timer Multichannel Buffered Serial Port Multichannel Buffered Serial Port Multichannel Buffered Serial Port Interrupt Selector Synchronous FIFOs Devices HOST CONNECTION Master /Slave PCI2040 Power 683xx
Peripheral Control
Instruction Fetch Instruction Dispatch Instruction Decode Data Path Register File Data Path Register File
Control Registers Control Logic Test In-Circuit Emulation Interrupt Control
Framing Chips: H.100, MVIP, SCSA, AC97 Devices, Devices, Codecs
Data Access Controller
Internal Data Memory (512K Bytes)
Expansion 32-Bit
Direct Memory Access Controller (DMA) (See Table (x1, x10, x11, x12)
PowerDown Logic Boot Configuration
additional details clock module specific options C6203 device, Table Clock section this data sheet.
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(DSP core) description
fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) supply eight 32-bit instructions eight functional units during every clock cycle. VelociTI VLIW architecture features controls which eight units have supplied with instructions they ready execute. first every 32-bit instruction determines next instruction belongs same execute packet previous instruction, whether should executed following clock part next execute packet. Fetch packets always bits wide; however, execute packets vary size. variable-length execute packets memory-saving feature, distinguishing C62x from other VLIW architectures. features sets functional units. Each contains four units register file. contains functional units .L1, .S1, .M1, .D1; other contains units .D2, .M2, .S2, .L2. register files each contain 32-bit registers total general-purpose registers. sets functional units, along with register files, compose sides [see functional (DSP core) block diagram Figure four functional units each side freely share registers belonging that side. Additionally, each side features single data connected registers other side, which sets functional units access data from register files opposite side. While register access functional units same side register file service units single clock cycle, register access using register file across supports read write cycle. Another feature C62x load/store architecture, where instructions operate registers opposed data memory). sets data-addressing units (.D1 .D2) responsible data transfers between register files memory. data address driven units allows data addresses generated from register file used load store data from other register file. C62x supports variety indirect addressing modes using either linear- circular-addressing modes with 15-bit offsets. instructions conditional, most access registers. Some registers, however, singled support specific addressing hold condition conditional instructions condition automatically "true"). functional units dedicated multiplies. functional units perform general arithmetic, logical, branch functions with results available every clock cycle. processing flow begins when 256-bit-wide instruction fetch packet fetched from program memory. 32-bit instructions destined individual functional units "linked" together bits least significant (LSB) position instructions. instructions that "chained" together simultaneous execution eight total) compose execute packet. instruction breaks chain, effectively placing instructions that follow next execute packet. execute packet crosses 256-bit-wide fetch-packet boundary, assembler places next fetch packet, while remainder current fetch packet padded with instructions. number execute packets within fetch packet vary from eight. Execute packets dispatched their respective functional units rate clock cycle next 256-bit fetch packet fetched until execute packets from current fetch packet have been dispatched. After decoding, instructions simultaneously drive active functional units maximum execution rate eight instructions every clock cycle. While most results stored 32-bit registers, they subsequently moved memory bytes half-words well. load store instructions byte-, half-word, word-addressable.
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(DSP core) description (continued)
src1
src2
long long
Data Path
src2
src1
src2
src1 src2
src2 src1 src2
src1
src2
Data Path
src1 long long
src1
Figure SMJ320C62x (DSP Core) Data Paths
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long long src2
long long src1
Register File (A0-A15) Register File (B0-B15) Control Register File
SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
memory summary
Table shows memory address ranges C6203 device. C6203 device capability memory block configuration. These memory block configurations reset boot configuration pins (generically called BOOTMODE[4:0]). C6203 device, BOOTMODE configuration handled, reset, expansion module (specifically XD[4:0] pins). more detailed information C6203 device settings, which include device boot mode configuration reset other device-specific configurations, Boot Configuration section Boot Configuration Summary table TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 320C6203 Memory Summary
MEMORY BLOCK DESCRIPTION External Memory Interface (EMIF) EMIF EMIF EMIF Internal Program Reserved EMIF Registers Controller Registers Expansion Registers McBSP Registers McBSP Registers Timer Registers Timer Registers Interrupt Selector Registers Power-Down Registers Reserved McBSP Registers Reserved EMIF EMIF Reserved Expansion XCE0 Expansion XCE1 Expansion XCE2 Expansion XCE3 Internal Data Reserved Internal Program Reserved EMIF EMIF EMIF EMIF BLOCK SIZE (BYTES) 384K 384K 384K 384K 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 5.5M 256M 256M 256M 256M 512K 512K ADDRESS RANGE 0000_0000 0005_FFFF 0006_0000 003F_FFFF 0040_0000 00FF_FFFF 0100_0000 013F_FFFF 0140_0000 0145_FFFF 0146_0000 017F_FFFF 0180_0000 0183_FFFF 0184_0000 0187_FFFF 0188_0000 018B_FFFF 018C_0000 018F_FFFF 0190_0000 0193_FFFF 0194_0000 0197_FFFF 0198_0000 019B_FFFF 019C_0000 019C_01FF 019C_0200 019F_FFFF 01A0_0000 01A3_FFFF 01A4_0000 01A7_FFFF 01A8_0000 01FF_FFFF 0200_0000 02FF_FFFF 0300_0000 03FF_FFFF 0400_0000 3FFF_FFFF 4000_0000 4FFF_FFFF 5000_0000 5FFF_FFFF 6000_0000 6FFF_FFFF 7000_0000 7FFF_FFFF 8000_0000 8007_FFFF 8008_0000 FFFF_FFFF
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peripheral register descriptions
Table through Table identify peripheral registers C6203 device their register names, acronyms, address address range. more detailed information register contents, names, their descriptions, TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table EMIF Registers
ADDRESS RANGE 0180 0000 0180 0004 ACRONYM GBLCTL CECTL1 REGISTER NAME EMIF global control EMIF space control External internal; dependent MAP0 MAP1 configuration (selected EMIF GBLCTL register External internal; dependent MAP0 MAP1 configuration (selected EMIF GBLCTL register Corresponds EMIF memory space: [0200 0000 02FF FFFF] Corresponds EMIF memory space: [0300 0000 03FF FFFF] COMMENTS
0180 0008 0180 000C 0180 0010
CECTL0 CECTL2
EMIF space control Reserved EMIF space control
0180 0014 0180 0018 0180 001C 0180 0020 0180 0054 0180 0058 0183 FFFF
CECTL3 SDCTL SDTIM
EMIF space control EMIF SDRAM control EMIF SDRAM refresh control Reserved Reserved
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peripheral register descriptions (continued)
Table Registers
ADDRESS RANGE 0184 0000 0184 0004 0184 0008 0184 000C 0184 0010 0184 0014 0184 0018 0184 001C 0184 0020 0184 0024 0184 0028 0184 002C 0184 0030 0184 0034 0184 0038 0184 003C 0184 0040 0184 0044 0184 0048 0184 004C 0184 0050 0184 0054 0184 0058 0184 005C 0184 0060 0184 0064 0184 0068 0184 006C 0184 0070 0184 0074 0187 FFFF ACRONYM PRICTL0 PRICTL2 SECCTL0 SECCTL2 SRC0 SRC2 DST0 DST2 XFRCNT0 XFRCNT2 GBLCNTA GBLCNTB GBLIDXA GBLIDXB GBLADDRA GBLADDRB PRICTL1 PRICTL3 SECCTL1 SECCTL3 SRC1 SRC3 DST1 DST3 XFRCNT1 XFRCNT3 GBLADDRC GBLADDRD AUXCTL channel primary control channel primary control channel secondary control channel secondary control channel source address channel source address channel destination address channel destination address channel transfer counter channel transfer counter global count reload register global count reload register global index register global index register global address register global address register channel primary control channel primary control channel secondary control channel secondary control channel source address channel source address channel destination address channel destination address channel transfer counter channel transfer counter global address register global address register auxiliary control register Reserved REGISTER NAME
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peripheral register descriptions (continued)
Table Expansion Registers
ADDRESS RANGE 0188 0000 0188 0004 ACRONYM XBGC XCECTL1 REGISTER NAME Expansion global control register XCE1 space control register Corresponds expansion XCE0 memory space: [4000 0000 4FFF FFFF] Corresponds expansion XCE1 memory space: [5000 0000 5FFF FFFF] read/write access only Corresponds expansion XCE2 memory space: [6000 0000 6FFF FFFF] Corresponds expansion XCE3 memory space: [7000 0000 7FFF FFFF] COMMENTS
0188 0008 0188 000C 0188 0010
XCECTL0 XBHC XCECTL2
XCE0 space control register Expansion host port interface control register XCE2 space control register
0188 0014 0188 0018 0188 001C 0188 0020 0188 0024 0188 0028 018B FFFF
XCECTL3 XBIMA XBEA XBISA
XCE3 space control register Reserved Reserved Expansion internal master address register Expansion external address register Reserved Expansion internal slave address Expansion data
read/write access only read/write access only
Table Interrupt Selector Registers
ADDRESS RANGE 019C 0000 019C 0004 019C 0008 019C 000C 019C 01FF 019C 0200 019C 0204 019F FFFF ACRONYM MUXH MUXL EXTPOL PDCTL REGISTER NAME Interrupt multiplexer high Interrupt multiplexer External interrupt polarity Reserved Peripheral power-down control register Reserved COMMENTS Selects which interrupts drive interrupts 10-15 (INT10-INT15) Selects which interrupts drive interrupts (INT04-INT09) Sets polarity external interrupts (EXT_INT4-EXT_INT7)
Table Peripheral Power-Down Control Register
ADDRESS RANGE 019C 0200 ACRONYM PDCTL REGISTER NAME Peripheral power-down control register
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peripheral register descriptions (continued)
Table McBSP Registers
ADDRESS RANGE 018C 0000 018C 0004 018C 0008 018C 000C 018C 0010 018C 0014 018C 0018 018C 001C 018C 0020 018C 0024 018C 0028 018F FFFF ACRONYM DRR0 DXR0 SPCR0 RCR0 XCR0 SRGR0 MCR0 RCER0 XCER0 PCR0 REGISTER NAME McBSP0 data receive register McBSP0 data transmit register McBSP0 serial port control register McBSP0 receive control register McBSP0 transmit control register McBSP0 sample rate generator register McBSP0 multichannel control register McBSP0 receive channel enable register McBSP0 transmit channel enable register McBSP0 control register Reserved COMMENTS DMA/EDMA controller only read this register; they cannot write
Table McBSP Registers
ADDRESS RANGE 0190 0000 0190 0004 0190 0008 0190 000C 0190 0010 0190 0014 0190 0018 0190 001C 0190 0020 0190 0024 0190 0028 0193 FFFF ACRONYM DRR1 DXR1 SPCR1 RCR1 XCR1 SRGR1 MCR1 RCER1 XCER1 PCR1 REGISTER NAME Data receive register McBSP1 data transmit register McBSP1 serial port control register McBSP1 receive control register McBSP1 transmit control register McBSP1 sample rate generator register McBSP1 multichannel control register McBSP1 receive channel enable register McBSP1 transmit channel enable register McBSP1 control register Reserved COMMENTS DMA/EDMA controller only read this register; they cannot write
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peripheral register descriptions (continued)
Table McBSP Registers
ADDRESS RANGE 01A4 0000 01A4 0004 01A4 0008 01A4 000C 01A4 0010 01A4 0014 01A4 0018 01A4 001C 01A4 0020 01A4 0024 01A4 0028 01A7 FFFF ACRONYM DRR2 DXR2 SPCR2 RCR2 XCR2 SRGR2 MCR2 RCER2 XCER2 PCR2 REGISTER NAME McBSP2 data receive register McBSP2 data transmit register McBSP2 serial port control register McBSP2 receive control register McBSP2 transmit control register McBSP2 sample rate generator register McBSP2 multichannel control register McBSP2 receive channel enable register McBSP2 transmit channel enable register McBSP2 control register Reserved COMMENTS DMA/EDMA controller only read this register; they cannot write
Table Timer Registers
ADDRESS RANGE 0194 0000 ACRONYM CTL0 REGISTER NAME Timer control register COMMENTS Determines operating mode timer, monitors timer status, controls function TOUT pin. Contains number timer input clock cycles count. This number controls TSTAT signal frequency. Contains current value incrementing counter.
0194 0004
PRD0
Timer period register
0194 0008 0194 000C 0197 FFFF
CNT0
Timer counter register Reserved
Table Timer Registers
ADDRESS RANGE 0198 0000 ACRONYM CTL1 REGISTER NAME Timer control register COMMENTS Determines operating mode timer, monitors timer status, controls function TOUT pin. Contains number timer input clock cycles count. This number controls TSTAT signal frequency. Contains current value incrementing counter.
0198 0004
PRD1
Timer period register
0198 0008 0198 000C 019B FFFF
CNT1
Timer counter register Reserved
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synchronization events
C6203 supports four independent programmable channels, plus auxiliary channel used servicing module. four main channels read/write synchronized based events shown Table Selection these events done RSYNC WSYNC fields Primary Control registers specific channel. more detailed information module, associated channels, event-synchronization, Direct Memory Access (DMA) Controller chapter TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 320C6203 Synchronization Events
EVENT NUMBER (BINARY) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 11111 EVENT NAME Reserved TINT0 TINT1 SD_INT EXT_INT4 EXT_INT5 EXT_INT6 EXT_INT7 DMA_INT0 DMA_INT1 DMA_INT2 DMA_INT3 XEVT0 REVT0 XEVT1 REVT1 DSP_INT XEVT2 REVT2 Reserved Reserved Timer interrupt Timer interrupt EMIF SDRAM timer interrupt External interrupt External interrupt External interrupt External interrupt channel interrupt channel interrupt channel interrupt channel interrupt McBSP0 transmit event McBSP0 receive event McBSP1 transmit event McBSP1 receive event Host processor-to-DSP interrupt McBSP2 transmit event McBSP2 receive event Reserved. used. EVENT DESCRIPTION
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interrupt sources interrupt selector
C62x core supports prioritized interrupts, which listed Table highest-priority interrupt INT_00 (dedicated RESET) while lowest-priority interrupt INT_15. first four interrupts (INT_00-INT_03) non-maskable fixed. remaining interrupts (INT_04-INT_15) maskable default interrupt source specified Table interrupt source interrupts 4-15 programmed modifying selector value (binary value) corresponding fields Interrupt Selector Control registers: MUXH (address 0x019C0000) MUXL (address 0x019C0004). Table C6203 Interrupts
INTERRUPT NUMBER INT_00 INT_01 INT_02 INT_03 INT_04 INT_05 INT_06 INT_07 INT_08 INT_09 INT_10 INT_11 INT_12 INT_13 INT_14 INT_15 INTERRUPT SELECTOR CONTROL REGISTER MUXL[4:0] MUXL[9:5] MUXL[14:10] MUXL[20:16] MUXL[25:21] MUXL[30:26] MUXH[4:0] MUXH[9:5] MUXH[14:10] MUXH[20:16] MUXH[25:21] MUXH[30:26] SELECTOR VALUE (BINARY) 00100 00101 00110 00111 01000 01001 00011 01010 01011 00000 00001 00010 01100 01101 01110 01111 10000 10001 10010 10011 11111 INTERRUPT EVENT RESET Reserved Reserved EXT_INT4 EXT_INT5 EXT_INT6 EXT_INT7 DMA_INT0 DMA_INT1 SD_INT DMA_INT2 DMA_INT3 DSP_INT TINT0 TINT1 XINT0 RINT0 XINT1 RINT1 Reserved XINT2 RINT2 Reserved Reserved. use. Reserved. use. External interrupt External interrupt External interrupt External interrupt channel interrupt channel interrupt EMIF SDRAM timer interrupt channel interrupt channel interrupt Host-processor-to-DSP interrupt Timer interrupt Timer interrupt McBSP0 transmit interrupt McBSP0 receive interrupt McBSP1 transmit interrupt McBSP1 receive interrupt Reserved. used. McBSP2 transmit interrupt McBSP2 receive interrupt Reserved. use. INTERRUPT SOURCE
Interrupts INT_00 through INT_03 non-maskable fixed. Interrupts INT_04 through INT_15 programmable modifying binary selector values Interrupt Selector Control registers fields. Table shows default interrupt sources Interrupts INT_04 through INT_15. more detailed information interrupt sources selection, Interrupt Selector External Interrupts chapter TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
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signal groups description
CLKIN CLKOUT2 CLKOUT1 CLKMODE0 CLKMODE1 CLKMODE2 PLLV PLLG PLLF Clock/PLL RESET EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0
Reset Interrupts
TRST EMU1 EMU0
IEEE Standard 1149.1 (JTAG) Emulation Status
DMAC3 DMAC2 DMAC1 DMAC0
RSV4 RSV3 RSV2 RSV1 RSV0
Reserved
Power-Down Status
Control/Status
Figure (DSP Core) Signals
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signal groups description (continued)
ED[31:0] EA[21:2] Data
Asynchronous Memory Control
ARDY
Memory Space Select
Synchronous Memory Control
Word Address HOLD/ HOLDA EMIF (External Memory Interface)
SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE
Byte Enables
HOLD HOLDA
TOUT1 TINP1
Timer Timers
Timer
TOUT0 TINP0
McBSP1 CLKX1 FSX1 CLKR1 FSR1 CLKS1 Transmit
McBSP0 Transmit CLKX0 FSX0 CLKR0 FSR0 CLKS0
Receive
Receive
Clock
Clock
McBSP2 Transmit CLKX2 FSX2 CLKR2 FSR2 CLKS2
Receive
Clock
McBSPs (Multichannel Buffered Serial Ports)
Figure Peripheral Signals
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signal groups description (continued)
XD[31:0] Data Clocks
XCLKIN XFCLK
XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 XRDY
Byte-Enable Control/ Address Control Port Control
XHOLD XHOLDA Arbitration
XWE/XWAIT XCE3 XCE2 XCE1 XCE0
Expansion
Host Interface Control
XCNTL XW/R XBLAST XBOFF
Figure Peripheral Signals (Continued)
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Signal Descriptions
SIGNAL NAME CLOCK/PLL CLKIN CLKOUT1 CLKOUT2 CLKMODE0 CLKMODE1 CLKMODE2 PLLV PLLG PLLF TRST EMU1 EMU0 RESET EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 Active interrupt identification number Valid during IACK active interrupts (not just external) interrupt-service fetch-packet Encoding order follows interru t-service fetch- acket ordering I/O/Z I/O/Z Used synchronous memory interface Clock mode selects Selects what multiply factors input clock frequency frequency equals. more details CLKMODE pins ltipl factors C6203 device, multiply Clock section this data sheet. analog connection low-pass filter analog connection low-pass filter low-pass filter connection external components bypass capacitor JTAG EMULATION JTAG test-port mode select (features internal pullup) JTAG test-port data JTAG test-port data (features internal pullup) JTAG test-port clock JTAG test-port reset (features internal pulldown) Emulation pullup with dedicated 20-k Emulation pullup with dedicated 20-k RESET INTERRUPTS Device reset Nonmaskable interrupt Edge-driven (rising edge) External interrupts Edge-driven Polarity independently selected External Interrupt Polarity Register bits (EXTPOL.[3:0]) (EXTPOL Interrupt acknowledge active interrupts serviced Clock input Clock output full device speed Clock output half (1/2) device speed TYPE DESCRIPTION
INUM0 Input, Output, High Impedance, Supply Voltage, Ground PLLV, PLLG, PLLF part external voltage supply ground. clock section information connect these pins. Analog Signal (PLL Filter) emulation normal operation, pull EMU1 EMU0 with dedicated 20-k resistor. boundary scan, pull down EMU1 EMU0 with dedicated 20-k resistor.
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Signal Descriptions (Continued)
SIGNAL NAME POWER-DOWN STATUS XCLKIN XFCLK XD31 XD30 XD29 XD28 XD27 XD26 XD25 XD24 XD23 XD22 XD21 XD20 XD19 XD18 XD17 XD16 XD15 XD14 XD13 XD12 XD11 XD10 other expansion data pins listed should pulled down. proper operation, must pulled down with 10-k resistor. board design should wired eration, ulled such that pullup pulldown resistor used future applications. I/O/Z ansion Expansion data Used transfer data, address, control controls modes expansion reset Also initialization [Note: more information control boot configuration fields Boot Modes fields, Configuration chapter TMS320C6000 Peri herals Reference Guide (literature Peripherals number SPRU190)] XD[30:16]- XD13 XD12 XD11 XD10 XD[4:0] XCE[3:0] memory type olarity XBLAST polarity XW/R polarity Asynchronous synchronous host operation Arbitration mode (internal external) FIFO mode Little endian/big endian SCRT select Boot mode Power-down modes (active high) EXPANSION Expansion synchronous host interface clock input Expansion FIFO interface clock output TYPE DESCRIPTION
Input, Output, High Impedance, Supply Voltage, Ground
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Signal Descriptions (Continued)
SIGNAL NAME EXPANSION (CONTINUED) XCE3 XCE2 XCE1 XCE0 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 XWE/XWAIT XCNTL XW/R XRDY XBLAST XBOFF XHOLD XHOLDA Byte-enable control Decoded from lowest bits internal address Byte-write enables most types memory directly connected SDRAM read write mask signal (SDQM) Memory space enables Enabled bits word address Only asserted during external data access I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Expansion port output-enable Expansion port read-enable Expansion port write-enable host-port wait signals Expansion host-port chip-select input Expansion host-port address strobe Expansion host control. XCNTL selects between expansion address data register. Expansion host-port write/read-enable. XW/R polarity selected reset. Expansion host-port ready (active low) port ready (active high) Expansion host-port burst last-polarity selected reset Expansion back Expansion hold request Expansion hold acknowledge EMIF CONTROL SIGNALS COMMON TYPES MEMORY I/O/Z Expansion multiplexed byte-enable control/address signals byte enable host port operation byte-enable host-port operation address port eration Expansion port memory space enables Enabled bits word address Only asserted during port data access TYPE DESCRIPTION
Input, Output, High Impedance, Supply Voltage, Ground
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Signal Descriptions (Continued)
SIGNAL NAME EMIF ADDRESS EA21 EA20 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 ED15 EMIF DATA I/O/Z External ternal data External ternal address address) (word TYPE DESCRIPTION
ED14 AA10 Input, Output, High Impedance, Supply Voltage, Ground
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Signal Descriptions (Continued)
SIGNAL NAME EMIF DATA (CONTINUED) ED13 ED12 ED11 ED10 ARDY SDA10 SDCAS/SSADS SDRAS/SSOE SDWE/SSWE HOLD HOLDA TOUT0 TINP0 TOUT1 TINP1 DMAC3 DMAC2 DMAC1 AA13 EMIF ASYNCHRONOUS MEMORY CONTROL action complete Asynchronous memory read-enable Asynchronous memory output-enable Asynchronous memory write-enable Asynchronous memory ready input SDRAM address (separate deactivate command) SDRAM column-address strobe/SBSRAM address strobe SDRAM row-address strobe/SBSRAM output-enable SDRAM write-enable/SBSRAM write-enable EMIF ARBITRATION Hold request from host Hold-request-acknowledge host TIMER Timer general-purpose output Timer general-purpose input TIMER Timer general-purpose output Timer general-purpose input ACTION COMPLETE STATUS I/O/Z External ternal data TYPE DESCRIPTION
EMIF SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
DMAC0 Input, Output, High Impedance, Supply Voltage, Ground
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Signal Descriptions (Continued)
SIGNAL NAME MULTICHANNEL BUFFERED SERIAL PORT (McBSP0) CLKS0 CLKR0 CLKX0 FSR0 FSX0 CLKS1 CLKR1 CLKX1 FSR1 FSX1 CLKS2 CLKR2 CLKX2 FSR2 FSX2 RSV0 RSV1 RSV2 RSV3 RSV4 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z connect External clock source opposed internal) Receive clock Transmit clock Receive data Transmit data Receive frame sync Transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT (McBSP1) External clock source opposed internal) Receive clock Transmit clock Receive data Transmit data Receive frame sync Transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT (McBSP2) External clock source opposed internal) Receive clock Transmit clock Receive data Transmit data Receive frame sync Transmit frame sync RESERVED TEST Reserved testing, pullup with dedicated 20-k resistor Reserved testing, pullup with dedicated 20-k resistor Reserved testing, pullup with dedicated 20-k resistor Reserved (leave unconnected, connect power ground) Reserved (leave unconnected, connect power ground) TYPE DESCRIPTION
Input, Output, High Impedance, Supply Voltage, Ground
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Signal Descriptions (Continued)
SIGNAL NAME SUPPLY VOLTAGE PINS DVDD Input, Output, High Impedance, Supply Voltage, Ground 3.3-V supply oltage voltage (I/O) TYPE DESCRIPTION
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Signal Descriptions (Continued)
SIGNAL NAME SUPPLY VOLTAGE PINS (CONTINUED) CVDD Input, Output, High Impedance, Supply Voltage, Ground 1.5-V supply voltage (core) TYPE DESCRIPTION
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Signal Descriptions (Continued)
SIGNAL NAME SUPPLY VOLTAGE PINS (CONTINUED) CVDD Input, Output, High Impedance, Supply Voltage, Ground 1.5-V voltage (core) supply TYPE DESCRIPTION
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Signal Descriptions (Continued)
SIGNAL NAME SUPPLY VOLTAGE PINS (CONTINUED) CVDD AA11 AA12 AA15 AA17 AA19 GROUND PINS Input, Output, High Impedance, Supply Voltage, Ground Ground pins 1.5-V supply voltage (core) TYPE DESCRIPTION
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Signal Descriptions (Continued)
SIGNAL NAME GROUND PINS (CONTINUED) Input, Output, High Impedance, Supply Voltage, Ground Ground pins TYPE DESCRIPTION
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Signal Descriptions (Continued)
SIGNAL NAME GROUND PINS (CONTINUED) AA14 AA16 AA18 Input, Output, High Impedance, Supply Voltage, Ground Ground pins TYPE DESCRIPTION
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development support
offers extensive line development tools TMS320C6000 platform, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules. following products support development C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE) including Editor C/C++/Assembly Code Generation, Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides basic run-time target software needed support application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 multiprocessor system debug) (Evaluation Module) TMS320 Development Support Reference Guide (SPRU011) contains information about development-support products TMS320 family member devices, including documentation. this document further information TMS320 documentation TMS320 support products from Texas Instruments. additional document, TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320 DSP-related products from other companies industry. receive TMS320 literature, contact Literature Response Center 800/477-8924. complete listing development-support tools TMS320C6000 platform, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL) select "Find Development Tools". device-specific tools, under "Semiconductor Products" select "Digital Signal Processors", choose product family, select particular device. information pricing availability, contact nearest field sales office authorized distributor.
TMS320C6000, C6000, Code Composer Studio, DSP/BIOS, XDS, TMS320 trademarks Texas Instruments.
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development support (Continued)
device development-support tool nomenclature designate stages product development cycle, assigns prefixes part numbers SMJ320 devices support tools. Each SMJ320 commercial family member three prefixes: SMX, SMJ. Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (SMX/TMDX) through fully qualified production devices/tools (SMJ/TMDS). Device development evolutionary flow: Experimental device that necessarily representative final device's electrical specifications Final silicon that conforms device's electrical specifications completed quality reliability verification Fully qualified production device processed MIL-PRF-38535
Support tool development evolutionary flow: TMDX Development-support product that completed Texas Instruments internal qualification testing. Fully qualified development-support product
TMDS
devices TMDX development-support tools shipped against following disclaimer: "Developmental product intended internal evaluation purposes." devices TMDS development-support tools have been characterized fully, quality reliability device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (SMX have greater failure rate than standard production devices. Texas Instruments recommends that these devices used production system because their expected end-use failure rate still undefined. Only qualified production devices used. device nomenclature also includes suffix with device family name. This suffix indicates package type (for example, GLP), temperature range, device speed range megahertz (for example, MHz). Figure provides legend reading complete device name. C6203 device orderable part numbers (P/Ns), Texas Instruments site Worldwide http://www.ti.com URL, contact nearest field sales office, authorized distributor.
TMS320 trademark Texas Instruments.
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device development-support tool nomenclature (continued)
PREFIX SMX= Experimental device MIL-PRF-38535, Commercial Processing 6203 DEVICE SPEED RANGE
TEMPERATURE RANGE -55°C 125°C, military temperature DEVICE FAMILY TMS320t family PACKAGE TYPE 429-pin ceramic TECHNOLOGY CMOS DEVICE C6000 DSP: 6201B 6203 6701 Ball Grid Array
Figure SMJ320C6000 Platform Device Nomenclature
documentation support
Extensive documentation supports SMJ320 family devices from product announcement through applications development. types documentation available include: data sheets, such this document, with design specifications; complete user's reference guides devices tools; technical briefs; development-support tools; on-line help; hardware software applications. following brief, descriptive list support documentation specific C6000 devices: TMS320C6000 Instruction Reference Guide (literature number SPRU189) describes C6000 (DSP core) architecture, instruction set, pipeline, associated interrupts. TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes functionality peripherals available C6000 platform devices, such 64-/32-/16-bit external memory interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered serial ports (McBSPs), direct memory access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus, peripheral component interconnect (PCI), clocking phase-locked loop (PLL); power-down modes. This guide also includes information internal data program memories. TMS320C6000 Technical Brief (literature number SPRU197) gives introduction TMS320C62x/TMS320C67x devices, associated development tools, third-party support. tools support documentation electronically available within Code Composer Studio IDE. complete listing latest C6000 documentation, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL).
TMS320C67x trademark Texas Instruments.
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clock
Most internal C6203 clocks generated from single source through CLKIN pin. This source clock either drives PLL, which multiplies source clock frequency generate internal clock, bypasses become internal clock. generate clock, external filter circuit must properly designed. Figure Table through Table show external circuitry either (PLL bypass) multiply modes. Figure shows external circuitry system with ONLY (PLL bypass) mode. minimize clock jitter, single clean power supply should power both C6203 device external clock oscillator circuit. Noise coupling into PLLF directly impacts clock jitter. minimum CLKIN rise fall times should also observed. input clock timing requirements, input output clocks electricals section. Table lists some examples compatible CLKIN external clock sources: Table Compatible CLKIN External Clock Sources
COMPATIBLE PARTS EXTERNAL CLOCK SOURCES (CLKIN) PART NUMBER JITO-2 series, ST4100 series Oscillators SG-636
3.3V PLLV CLKMODE0 CLKMODE1 CLKMODE2 CLKIN
MANUFACTURER Electronix SaRonix Corporation Epson America Corning Frequency Control Integrated Circuit Systems
MK1711-S, ICS525-02
Filter
PLLMULT PLLCLK CLKIN LOOP FILTER
Internal C6203
CLOCK
(For Options CLKMODE pins setup, Table Table
NOTES: Keep lead length number vias between PLLF, PLLG, minimum. addition, place components (R1, Filter) close C6000 device possible. Best performance achieved with components single side board without jumpers, switches, components other than ones shown. reduced jitter, maximize spacing between switching signals external components (R1, Filter). 3.3-V supply filter must from same 3.3-V power plane supplying voltage, DVDD.
Figure External Circuitry Either Multiply Modes (Bypass) Mode
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PLLG
PLLF
SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
clock (continued)
3.3V PLLV CLKMODE0 CLKMODE1 CLKMODE2 PLLMULT
PLLCLK
Internal C6203
CLKIN
CLKIN LOOP FILTER
CLOCK
NOTES: system with ONLY (bypass) mode, short PLLF PLLG. 3.3-V supply PLLV must from same 3.3-V power plane supplying voltage, DVDD.
Figure External Circuitry (Bypass) Mode Only Table Multiply Bypass (x1) Options
(PIN NO.) CLKMODE2 (G12) Value f(CPU Clock) f(CLKIN) (PLL mode) CLKMODE1 (G10) CLKMODE0 (C12) DEVICES CLOCK OPTIONS C6203 (GLP) Bypass (x1)
Table SMJ320C6203 Component Selection Table
CLKMODE CLKIN RANGE (MHz) 32.5-75 21.7-50 18.6-42.9 16.3-37.5 14.4-33.3 13-30 130-300 65-150 45.3 CLOCK FREQUENCY RANGE (MHz) CLKOUT2 RANGE (MHz) [±1%] (Revision No.) [±10%] (Revision No.) [±10%] (Revision No.) TYPICAL LOCK TIME (µs)
11.8-27.3 Under some operating conditions, maximum lock time vary much 150% from specified typical value. example, typical lock time specified maximum value long
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PLLG
PLLF
SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
power-supply sequencing
DSPs require specific power sequencing between core supply supply. However, systems should designed ensure that neither supply powered extended periods time other supply below proper operating voltage. system-level design considerations System-level design considerations, such contention, require supply sequencing implemented. this case, core supply should powered same time prior (and powered down after), buffers. This ensure that buffers receive valid inputs from core before output buffers powered thus, preventing contention with other chips board. power-supply design considerations systems using C6000 platform devices, core supply required provide excess until supply powered This extra current condition result uninitialized logic within DSP(s) corrected once sees internal clock pulse. With enabled, supply powered clock pulse produced stopping extra current draw from supply. With disabled, many five external clock cycle pulses required stop this extra current draw. normal current state returns once power supply turned sees clock pulse. Decreasing amount time between core supply power supply power minimize effects this current draw. dual-power supply with simultaneous sequencing, such available with TPS563xx controllers PT69xx plug-in power modules, used eliminate delay between core power [see Using TPS56300 Power DSPs application report (literature number SLVA088)]. Schottky diode also used core rail rail, effectively pulling power supply level that help initialize logic within DSP. Core supply voltage regulators should located close array) minimize inductance resistance power delivery path. Additionally, when designing high-performance applications utilizing C6000 platform DSPs, board should include separate power planes core, I/O, ground, bypassed with high-quality low-ESL/ESR capacitors.
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absolute maximum ratings over operating case temperature ranges (unless otherwise noted)
Supply voltage range, CVDD (see Note Supply voltage range, DVDD (see Note -0.3 Input voltage range -0.3 Output voltage range -0.3 Operating case temperature ranges, -55_C 125_C Storage temperature range, Tstg -65_C 150_C Temperature cycle range, (1000-cycle performance) -55_C 125_C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect VSS.
recommended operating conditions
CVDD DVDD Supply voltage, Core Supply voltage, Supply ground High-level input voltage Low-level input High-level output current 1.43 3.14 1.57 3.46 UNIT
Low-level output current Operating case temperature production tested for: CLKMODE [2:0], CLKIN, XCLKIN, XCS. production tested for: CLKIN, TRST.
electrical characteristics over recommended ranges supply voltage operating case temperature (unless otherwise noted)
PARAMETER IDD2V IDD2V IDD3V High-level output Low-level output Input current# Off-state output current|| Supply current, memory accessk Supply current, peripheralsk Supply current, pinsk Input capacitance TEST CONDITIONS DVDD MIN, DVDD MIN, DVDD DVDD CVDD NOM, CVDD NOM, CVDD NOM, clock clock clock UNIT
Output capacitance production tested for: CLKOUT1, EMU0, EMU1. included internal pullups. TRST included internal pulldown. production tested. Measured with average activity (50% high power). more details CPU, peripheral, activity, TMS320C6000 Power Consumption Summary application report (literature number SPRA486).
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PARAMETER MEASUREMENT INFORMATION
Tester Electronics Output Under Test
Vcomm
Where:
Vcomm
15-pF typical load-circuit capacitance
Figure Test Load Circuit Timing Measurements
signal transition levels
input output timing parameters referenced both logic levels.
Vref
Figure Input Output Voltage Reference Levels Timing Measurements rise fall transition timing parameters referenced input clocks, output clocks.
Vref MIN)
Vref MAX)
Figure Rise Fall Transition Time Voltage Reference Levels
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PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters board routing analysis
timing parameter values specified this data sheet include delays board routings. good board design practice, such delays must always taken into account. Timing values adjusted increasing/decreasing such delays. recommends utilizing available buffer information specification (IBIS) models analyze timing characteristics correctly. needed, external logic hardware such buffers used compensate timing differences. inputs, timing most impacted round-trip propagation delay from external device from external device DSP. This round-trip delay tends negatively impact input setup time margin, also tends improve input hold time margins (see Table Figure 10). Figure represents general transfer between external device. figure also represents board route delays they perceived external device. Table IBIS Timing Parameters Example (see Figure
CLKOUT2 (Output from DSP) CLKOUT2 (Input External Device) Control Signals (Output from DSP) Control Signals (Input External Device) Data Signals (Output from External Device) Data Signals (Input DSP) Control signals include data Writes. Data signals generated during Reads from external device. DESCRIPTION Clock route delay Minimum hold time Minimum setup time External device hold time requirement External device setup time requirement Control signal route delay External device hold time External device access time hold time requirement setup time requirement Data route delay
Figure IBIS Input/Output Timings
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INPUT OUTPUT CLOCKS timing requirements CLKIN (PLL (see Figure
tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN Transition time, CLKIN *0.45C *0.45C *0.5 UNIT
*This parameter production tested. reference points rise fall transitions measured MIN. multiplier factor (x4, x10, x11). CLKIN cycle time example, when CLKIN frequency MHz,
timing requirements CLKIN [PLL bypassed (see Figure
tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN Transition time, CLKIN *0.45C *0.45C *0.6 UNIT
*This parameter production tested. reference points rise fall transitions measured MIN. CLKIN cycle time example, when CLKIN frequency MHz, maximum CLKIN cycle time bypass mode (x1) MHz.
CLKIN
Figure CLKIN Timings
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INPUT OUTPUT CLOCKS (CONTINUED) timing requirements XCLKIN (see Figure
tc(XCLKIN) tw(XCLKINH) Cycle time, XCLKIN Pulse duration, XCLKIN high *1.8P *1.8P UNIT
tw(XCLKINL) Pulse duration, XCLKIN *This parameter production tested. 1/CPU clock frequency nanoseconds (ns).
XCLKIN
Figure XCLKIN Timings
switching characteristics over recommended operating conditions (see Figure
tc(CKO2) tw(CKO2H) Cycle time, CLKOUT2 Pulse duration, CLKOUT2 high PARAMETER UNIT
tw(CKO2L) Pulse duration, CLKOUT2 *This parameter production tested. 1/CPU clock frequency reference points rise fall transitions measured MIN. CLKOUT2
Figure CLKOUT2 Timings
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INPUT OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions XFCLK (see Figure
tc(XFCK) tw(XFCKH) PARAMETER Cycle time, XFCLK Pulse duration, XFCLK high *(D/2) *(D/2) *(D/2) *(D/2) UNIT
tw(XFCKL) Pulse duration, XFCLK *This parameter production tested. 1/CPU clock frequency FIFO clock divide ratio, user-programmable XFCLK
Figure XFCLK Timings
ASYNCHRONOUS MEMORY TIMING timing requirements asynchronous memory (see Figure Figure
tsu(EDV-AREH) th(AREH-EDV) tsu(ARDYH-AREL) th(AREL-ARDYH) tsu(ARDYL-AREL) th(AREL-ARDYL) tw(ARDYH) tsu(ARDYH-AWEL) th(AWEL-ARDYH) tsu(ARDYL-AWEL) th(AWEL-ARDYL) Setup time, valid before high Hold time, valid after high Setup time, ARDY high before Hold time, ARDY high after Setup time, ARDY before Hold time, ARDY after Pulse width, ARDY high Setup time, ARDY high before Hold time, ARDY high after Setup time, ARDY before Hold time, ARDY after -[(RST (RST -[(RST (RST -[(WST (WST -[(WST (WST UNIT
*This parameter production tested. ensure data setup time, simply program strobe width wide enough. ARDY internally synchronized. ARDY does meet setup hold time, recognized current cycle next cycle. Thus, ARDY asynchronous input. Read Setup, Read Strobe, Read Hold, Write Setup, Write Strobe, Write Hold. These parameters programmed EMIF space control registers. 1/CPU clock frequency example, when running parts MHz, WST) must minimum order ARDY input extend strobe width.
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ASYNCHRONOUS MEMORY TIMING (CONTINUED) switching characteristics over recommended operating conditions asynchronous memory (see Figure Figure
tosu(SELV-AREL) toh(AREH-SELIV) tw(AREL) td(ARDYH-AREH) tosu(SELV-AWEL) toh(AWEH-SELIV) tw(AWEL) PARAMETER Output setup time, select signals valid Output hold time, high select signals invalid Pulse width, Delay time, ARDY high high Output setup time, select signals valid Output hold time, high select signals invalid Pulse width, UNIT
td(ARDYH-AWEH) Delay time, ARDY high high *This parameter production tested. Read Setup, Read Strobe, Read Hold, Write Setup, Write Strobe, Write Hold. These parameters programmed EMIF space control registers. 1/CPU clock frequency example, when running parts MHz, WST) must minimum order ARDY input extend strobe width. Select signals include: CEx, BE[3:0], EA[21:2], AOE; writes, include ED[31:0], with exception that stay active additional following cycle.
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup CLKOUT1 BE[3:0] EA[21:2] ED[31:0] Strobe Hold
ARDY
stays active seven minus value Read Hold cycles after last access (DMA transfer access). example, read HOLD then stays active more cycles. This does affect performance, merely reflects EMIF's overhead.
Figure Asynchronous Memory Read Timing (ARDY Used)
Setup CLKOUT1 BE[3:0] EA[21:2] ED[31:0] ARDY stays active seven minus value Read Hold cycles after last access (DMA transfer access). example, read HOLD then stays active more cycles. This does affect performance, merely reflects EMIF's overhead. Strobe Ready Hold
Figure Asynchronous Memory Read Timing (ARDY Used)
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup Strobe CLKOUT1 BE[3:0] EA[21:2] ED[31:0] ARDY write accesses scheduled next cycle write hold greater, then stays active three cycles after value programmed hold period. write hold then stays active four more cycles. This does affect performance, merely reflects EMIF's overhead. Hold
Figure Asynchronous Memory Write Timing (ARDY Used)
Setup Strobe CLKOUT1 BE[3:0] EA[21:2] ED[31:0] ARDY write accesses scheduled next cycle write hold greater, then stays active three cycles after value programmed hold period. write hold then stays active four more cycles. This does affect performance, merely reflects EMIF's overhead. Ready Hold
Figure Asynchronous Memory Write Timing (ARDY Used)
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SYNCHRONOUS-BURST MEMORY TIMING timing requirements synchronous-burst SRAM cycles (see Figure
tsu(EDV-CKO2H) th(CKO2H-EDV) Setup time, read valid before CLKOUT2 high Hold time, read valid after CLKOUT2 high UNIT
switching characteristics over recommended operating conditions synchronous-burst SRAM cycles (see Figure Figure
tosu(CEV-CKO2H) toh(CKO2H-CEV) tosu(BEV-CKO2H) toh(CKO2H-BEIV) tosu(EAV-CKO2H) toh(CKO2H-EAIV) PARAMETER Output setup time, valid before CLKOUT2 high Output hold time, valid after CLKOUT2 high Output setup time, valid before CLKOUT2 high Output hold time, invalid after CLKOUT2 high Output setup time, valid before CLKOUT2 high Output hold time, invalid after CLKOUT2 high UNIT
tosu(ADSV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high toh(CKO2H-ADSV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high tosu(OEV-CKO2H) toh(CKO2H-OEV) tosu(EDV-CKO2H) toh(CKO2H-EDIV) tosu(WEV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high Output hold time, SDRAS/SSOE valid after CLKOUT2 high Output setup time, valid before CLKOUT2 Output hold time, invalid after CLKOUT2 high Output setup time, SDWE/SSWE valid before CLKOUT2 high
toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high *This parameter production tested. 1/CPU clock frequency example, when running parts MHz, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE operate SSADS, SSOE, SSWE, respectively, during SBSRAM accesses. first write series more consecutive adjacent writes, write data generated CLKOUT2 cycle early accommodate enable time.
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SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
CLKOUT2 BE[3:0] ED[31:0] SDCAS/SSADS SDRAS/SSOE SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE operate SSADS, SSOE, SSWE, respectively, during SBSRAM accesses.
EA[21:2]
Figure SBSRAM Read Timing
CLKOUT2 ED[31:0] SDCAS/SSADS SDRAS/SSOE SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE operate SSADS, SSOE, SSWE, respectively, during SBSRAM accesses.
BE[3:0]
EA[21:2]
Figure SBSRAM Write Timing
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SYNCHRONOUS DRAM TIMING timing requirements synchronous DRAM cycles (see Figure
tsu(EDV-CKO2H) th(CKO2H-EDV) Setup time, read valid before CLKOUT2 high Hold time, read valid after CLKOUT2 high UNIT
switching characteristics over recommended operating conditions synchronous DRAM cycles C6203B Rev. (see Figure 21-Figure
tosu(CEV-CKO2H) toh(CKO2H-CEV) tosu(BEV-CKO2H) toh(CKO2H-BEIV) tosu(EAV-CKO2H) toh(CKO2H-EAIV) tosu(CASV-CKO2H) toh(CKO2H-CASV) tosu(EDV-CKO2H) toh(CKO2H-EDIV) tosu(WEV-CKO2H) toh(CKO2H-WEV) tosu(SDA10V-CKO2H) toh(CKO2H-SDA10IV) tosu(RASV-CKO2H) toh(CKO2H-RASV) PARAMETER Output setup time, valid before CLKOUT2 high Output hold time, valid after CLKOUT2 high Output setup time, valid before CLKOUT2 high Output hold time, invalid after CLKOUT2 high Output setup time, valid before CLKOUT2 high Output hold time, invalid after CLKOUT2 high Output setup time, SDCAS/SSADS valid before CLKOUT2 high Output hold time, SDCAS/SSADS valid after CLKOUT2 high Output setup time, valid before CLKOUT2 Output hold time, invalid after CLKOUT2 high Output setup time, SDWE/SSWE valid before CLKOUT2 high Output hold time, SDWE/SSWE valid after CLKOUT2 high Output setup time, SDA10 valid before CLKOUT2 high Output hold time, SDA10 invalid after CLKOUT2 high Output setup time, SDRAS/SSOE valid before CLKOUT2 high Output hold time, SDRAS/SSOE valid after CLKOUT2 high UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE operate SDCAS, SDRAS, SDWE, respectively, during SDRAM accesses. first write series more consecutive adjacent writes, write data generated CLKOUT2 cycle early accommodate enable time.
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ CLKOUT2 BE[3:0] EA[15:2]
READ
READ
ED[31:0] SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE
SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE operate SDCAS, SDRAS, SDWE, respectively, during SDRAM accesses.
Figure Three SDRAM READ Commands
WRITE CLKOUT2 BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE
WRITE
WRITE
SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE operate SDCAS, SDRAS, SDWE, respectively, during SDRAM accesses.
Figure Three SDRAM Commands
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV CLKOUT2 BE[3:0] Bank Activate/Row Address
EA[15:2] ED[31:0]
SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE operate SDCAS, SDRAS, SDWE, respectively, during SDRAM accesses. Address
Figure SDRAM ACTV Command
DCAB CLKOUT2 BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE operate SDCAS, SDRAS, SDWE, respectively, during SDRAM accesses.
Figure SDRAM DCAB Command
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR CLKOUT2 BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE operate SDCAS, SDRAS, SDWE, respectively, during SDRAM accesses.
Figure SDRAM REFR Command
CLKOUT2 BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE operate SDCAS, SDRAS, SDWE, respectively, during SDRAM accesses. Value
Figure SDRAM Command
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
HOLD/HOLDA TIMING timing requirements HOLD/HOLDA cycles (see Figure
toh(HOLDAL-HOLDL) Output hold time, HOLD after HOLDA *This parameter production tested. 1/CPU clock frequency example, when running parts MHz, UNIT
switching characteristics over recommended operating conditions HOLD/HOLDA cycles (see Figure
td(HOLDL-EMHZ) td(EMHZ-HOLDAL) td(HOLDH-EMLZ) td(EMLZ-HOLDAH) PARAMETER Delay time, HOLD EMIF high impedance Delay time, EMIF high impedance HOLDA Delay time, HOLD high EMIF impedance Delay time, EMIF impedance HOLDA high UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, EMIF consists CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10. pending EMIF transactions allowed complete before HOLDA asserted. worst case this asynchronous read write with external ARDY used minimum eight consecutive SDRAM reads writes when RBTR8 transactions occurring, then minimum delay time achieved. Also, hold indefinitely delayed setting NOHOLD Owns External Requestor Owns HOLD HOLDA C6203 EMIF consists CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10. C6203 EMIF Owns
Figure HOLD/HOLDA Timing
RESET TIMING timing requirements reset (see Figure
Width RESET pulse (PLL tw(RST) tsu(XD) th(XD) Width RESET pulse (PLL needs sync up)# Setup time, configuration bits valid before RESET high|| Hold time, configuration bits valid after RESET high|| *10P *250 UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, This parameter applies CLKMODE when CLKIN stable, applies CLKMODE x10, when CLKIN stable. This parameter applies CLKMODE x10, only does apply CLKMODE x1). RESET signal connected internally clock circuit. PLL, however, need stabilize following device power after configuration been changed. During that time, RESET must asserted ensure proper device operation. Clock section lock times. XD[31:0] boot configuration pins during device reset.
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
RESET TIMING (CONTINUED) switching characteristics over recommended operating conditions during reset (see Figure
td(RSTL-CKO2IV) td(RSTH-CKO2V) td(RSTL-HIGHIV) td(RSTH-HIGHV) td(RSTL-LOWIV) td(RSTH-LOWV) td(RSTL-ZHZ) td(RSTH-ZV) PARAMETER Delay time, RESET CLKOUT2 invalid Delay time, RESET high CLKOUT2 valid Delay time, RESET high group invalid Delay time, RESET high high group valid Delay time, RESET group invalid Delay time, RESET high group valid Delay time, RESET group high impedance Delay time, RESET high group valid UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, High group consists XFCLK, HOLDA group consists IACK, INUM[3:0], DMAC[3:0], TOUT0, TOUT1 group consists EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, XHOLDA CLKOUT1 RESET CLKOUT2 HIGH GROUP GROUP GROUP High group consists group consists group consists Boot Configuration
XFCLK, HOLDA IACK, INUM[3:0], DMAC[3:0], TOUT0, TOUT1 EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, XHOLDA XD[31:0] boot configuration pins during device reset.
Figure Reset Timing
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXTERNAL INTERRUPT TIMING timing requirements interrupt response cycles (see Figure
tw(ILOW) tw(IHIGH) Width interrupt pulse Width interrupt pulse high UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz,
switching characteristics over recommended operating conditions during interrupt response cycles (see Figure
tR(EINTH IACKH) td(CKO2L-IACKV) td(CKO2L-INUMV) td(CKO2L-INUMIV) PARAMETER Response time, EXT_INTx high IACK high Delay time, CLKOUT2 IACK valid Delay time, CLKOUT2 INUMx valid Delay time, CLKOUT2 INUMx invalid *-1.5 *-2.0 *-2.0 UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, When CLKOUT2 half (1/2) mode (see CLKOUT2 Signal Descriptions table), timings based falling edges CLKOUT2 (1/4) [C6203C only] CLKOUT2 (1/2) EXT_INTx,
Intr Flag IACK INUMx Interrupt Number
Figure Interrupt Timing
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION SYNCHRONOUS FIFO TIMING timing requirements synchronous FIFO interface (see Figure Figure Figure
tsu(XDV-XFCKH) th(XFCKH-XDV) Setup time, read valid before XFCLK high Hold time, read valid after XFCLK high UNIT
switching characteristics over recommended operating conditions synchronous FIFO interface (see Figure Figure Figure
td(XFCKH-XCEV) td(XFCKH-XAV) td(XFCKH-XOEV) td(XFCKH-XREV) td(XFCKH-XWEV) td(XFCKH-XDV) PARAMETER Delay time, XFCLK high XCEx valid Delay time, XFCLK high XBE[3:0]/XA[5:2] valid Delay time, XFCLK high valid Delay time, XFCLK high valid Delay time, XFCLK high XWE/XWAIT valid Delay time, XFCLK high valid *-1.5 *-1.5 *-1.5 *-1.5 *-1.5 *-1.5 UNIT
td(XFCKH-XDIV) Delay time, XFCLK high invalid *This parameter production tested. XBE[3:0]/XA[5:2] operate address signals XA[5:2] during synchronous FIFO accesses. XWE/XWAIT operates write-enable signal during synchronous FIFO accesses.
XFCLK XCE3 Note XBE[3:0]/XA[5:2] Note XWE/XWAIT Note XD[31:0] NOTES: FIFO read (glueless) mode only available XCE3. XBE[3:0]/XA[5:2] operate address signals XA[5:2] during synchronous FIFO accesses. XWE/XWAIT operates write-enable signal during synchronous FIFO accesses.
Figure FIFO Read Timing (Glueless Read Mode)
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION SYNCHRONOUS FIFO TIMING (CONTINUED)
XFCLK XCEx XBE[3:0]/XA[5:2] XWE/XWAIT XD[31:0]
XBE[3:0]/XA[5:2] operate address signals XA[5:2] during synchronous FIFO accesses. XWE/XWAIT operates write-enable signal during synchronous FIFO accesses.
Figure FIFO Read Timing
XFCLK XCEx XBE[3:0]/XA[5:2] XWE/XWAIT XD[31:0]
XBE[3:0]/XA[5:2] operate address signals XA[5:2] during synchronous FIFO accesses. XWE/XWAIT operates write-enable signal during synchronous FIFO accesses.
Figure FIFO Write Timing
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION ASYNCHRONOUS PERIPHERAL TIMING timing requirements asynchronous peripheral (see Figure 33-Figure
tsu(XDV-XREH) th(XREH-XDV) tsu(XRDYH-XREL) th(XREL-XRDYH) tsu(XRDYL-XREL) th(XREL-XRDYL) tw(XRDYH) tsu(XRDYH-XWEL) th(XWEL-XRDYH) tsu(XRDYL-XWEL) th(XWEL-XRDYL) Setup time, valid before high Hold time, valid after high Setup time, XRDY high before Hold time, XRDY high after Setup time, XRDY before Hold time, XRDY after Pulse width, XRDY high Setup time, XRDY high before Hold time, XRDY high after Setup time, XRDY before Hold time, XRDY after -[(RST (RST -[(RST (RST -[(WST (WST -[(WST (WST UNIT
*This parameter production tested. ensure data setup time, simply program strobe width wide enough. XRDY internally synchronized. XRDY does meet setup hold time, recognized current cycle next cycle. Thus, XRDY asynchronous input. Read Setup, Read Strobe, Read Hold, Write Setup, Write Strobe, Write Hold. These parameters programmed expansion space control registers. 1/CPU clock frequency example, when running parts MHz, WST) must minimum order XRDY input extend strobe width.
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED) switching characteristics over recommended operating conditions asynchronous peripheral (see Figure 33-Figure
tosu(SELV-XREL) toh(XREH-SELIV) tw(XREL) td(XRDYH-XREH) tosu(SELV-XWEL) toh(XWEH-SELIV) tw(XWEL) PARAMETER Output setup time, select signals valid Output hold time, select signals invalid Pulse width, Delay time, XRDY high high Output setup time, select signals valid Output hold time, select signals invalid Pulse width, UNIT
td(XRDYH-XWEH) Delay time, XRDY high high *This parameter production tested. Read Setup, Read Strobe, Read Hold, Write Setup, Write Strobe, Write Hold. These parameters programmed expansion space control registers. 1/CPU clock frequency example, when running parts MHz, WST) must minimum order XRDY input extend strobe width. Select signals include: XCEx, XBE[3:0]/XA[5:2], XOE; writes, include XD[31:0], with exception that XCEx stay active additional following cycle.
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
Setup CLKOUT1 XCEx XBE[3:0]/ XA[5:2] Strobe Hold
XD[31:0] XWE/XWAIT XBE[3:0]/XA[5:2] operate address signals XA[5:2] during expansion asynchronous peripheral accesses. XWE/XWAIT operates write-enable signal during expansion asynchronous peripheral accesses. XRDY operates active-high ready input during expansion asynchronous peripheral accesses.
Figure Expansion Asynchronous Peripheral Read Timing (XRDY Used)
Setup CLKOUT1 XCEx XBE[3:0]/ XA[5:2] XD[31:0] XWE/XWAIT XBE[3:0]/XA[5:2] operate address signals XA[5:2] during expansion asynchronous peripheral accesses. XWE/XWAIT operates write-enable signal during expansion asynchronous peripheral accesses. XRDY operates active-high ready input during expansion asynchronous peripheral accesses. Strobe Ready Hold
Figure Expansion Asynchronous Peripheral Read Timing (XRDY Used)
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
Setup CLKOUT1 XCEx XBE[3:0]/ XA[5:2] XD[31:0] XWE/XWAIT XBE[3:0]/XA[5:2] operate address signals XA[5:2] during expansion asynchronous peripheral accesses. XWE/XWAIT operates write-enable signal during expansion asynchronous peripheral accesses. XRDY operates active-high ready input during expansion asynchronous peripheral accesses. Strobe Hold
Figure Expansion Asynchronous Peripheral Write Timing (XRDY Used)
Setup Strobe CLKOUT1 XCEx XBE[3:0]/ XA[5:2] XD[31:0] XWE/XWAIT XBE[3:0]/XA[5:2] operate address signals XA[5:2] during expansion asynchronous peripheral accesses. XWE/XWAIT operates write-enable signal during expansion asynchronous peripheral accesses. XRDY operates active-high ready input during expansion asynchronous peripheral accesses. Ready Hold
Figure Expansion Asynchronous Peripheral Write Timing (XRDY Used)
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION SYNCHRONOUS HOST-PORT TIMING timing requirements with external device master (see Figure Figure
tsu(XCSV-XCKIH) th(XCKIH-XCS) tsu(XAS-XCKIH) th(XCKIH-XAS) tsu(XCTL-XCKIH) th(XCKIH-XCTL) tsu(XWR-XCKIH) th(XCKIH-XWR) tsu(XBLTV-XCKIH) th(XCKIH-XBLTV) tsu(XBEV-XCKIH) th(XCKIH-XBEV) tsu(XD-XCKIH) th(XCKIH-XD) Setup time, valid before XCLKIN high Hold time, valid after XCLKIN high Setup time, valid before XCLKIN high Hold time, valid after XCLKIN high Setup time, XCNTL valid before XCLKIN high Hold time, XCNTL valid after XCLKIN high Setup time, XW/R valid before XCLKIN high Hold time, XW/R valid after XCLKIN high Setup time, XBLAST valid before XCLKIN high Hold time, XBLAST valid after XCLKIN high Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN Setup time, valid before XCLKIN high UNIT
Hold time, valid after XCLKIN high XW/R input/output polarity selected boot. XBLAST input polarity selected boot XBE[3:0]/XA[5:2] operate byte-enables XBE[3:0] during host-port accesses.
switching characteristics over recommended operating conditions with external device (see Figure Figure
td(XCKIH-XDLZ) td(XCKIH-XDV) td(XCKIH-XDIV) td(XCKIH-XDHZ) td(XCKIH-XRY) td(XCKIH-XRYLZ) PARAMETER Delay time, XCLKIN high impedance Delay time, XCLKIN high valid Delay time, XCLKIN high invalid Delay time, XCLKIN high high impedance Delay time, XCLKIN high XRDY invalid# Delay time, XCLKIN high XRDY impedance UNIT
td(XCKIH-XRYHZ) Delay time, XCLKIN high XRDY high impedance# *This parameter production tested. 1/CPU clock frequency example, when running parts MHz, XRDY operates active-low ready input/output during host-port accesses.
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN XCNTL XW/R XW/R XBE[3:0]/XA[5:2] XD[31:0] XW/R input/output polarity selected boot XBE[3:0]/XA[5:2] operate byte-enables XBE[3:0] during host-port accesses. XBLAST input polarity selected boot XRDY operates active-low ready input/output during host-port accesses.
Figure External Host Master-Read
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN XCNTL XW/R XW/R XBE[3:0]/XA[5:2] XD[31:0] XBE1 XBE2 XBE3 XBE4
XW/R input/output polarity selected boot XBE[3:0]/XA[5:2] operate byte-enables XBE[3:0] during host-port accesses. XBLAST input polarity selected boot XRDY operates active-low ready input/output during host-port accesses.
Figure External Host Master-Write
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION SYNCHRONOUS HOST-PORT TIMING (CONTINUED) timing requirements with C62x master (see Figure Figure Figure
tsu(XDV-XCKIH) th(XCKIH-XDV) tsu(XRY-XCKIH) th(XCKIH-XRY) tsu(XBFF-XCKIH) th(XCKIH-XBFF) Setup time, valid before XCLKIN high Hold time, valid after XCLKIN high Setup time, XRDY valid before XCLKIN high Hold time, XRDY valid after XCLKIN high Setup time, XBOFF valid before XCLKIN high Hold time, XBOFF valid after XCLKIN high UNIT
XRDY operates active-low ready input/output during host-port accesses.
switching characteristics over recommended operating conditions with C62x master (see Figure Figure Figure
td(XCKIH-XASV) td(XCKIH-XWRV) td(XCKIH-XBLTV) td(XCKIH-XBEV) td(XCKIH-XDLZ) td(XCKIH-XDV) td(XCKIH-XDIV) td(XCKIH-XDHZ) PARAMETER Delay time, XCLKIN high valid Delay time, XCLKIN high XW/R Delay time, XCLKIN high XBLAST Delay time, XCLKIN high XBE[3:0]/XA[5:2] valid# Delay time, XCLKIN high impedance Delay time, XCLKIN high valid Delay time, XCLKIN high invalid Delay time, XCLKIN high high impedance Delay time, XCLKIN high XWE/XWAIT valid|| UNIT
td(XCKIH-XWTV) *This parameter production tested. 1/CPU clock frequency example, when running parts MHz, XW/R input/output polarity selected boot. XBLAST output polarity always active low. XBE[3:0]/XA[5:2] operate byte-enables XBE[3:0] during host-port accesses. XWE/XWAIT operates XWAIT output signal during host-port accesses.
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN XW/R XW/R XBLAST XD[31:0] XRDY XW/R input/output polarity selected boot XBLAST output polarity always active low. XBE[3:0]/XA[5:2] operate byte-enables XBE[3:0] during host-port accesses. XWE/XWAIT operates XWAIT output signal during host-port accesses.
Figure C62x Master-Read
XCLKIN XW/R XW/R XBLAST XD[31:0] XRDY XW/R input/output polarity selected boot XBLAST output polarity always active low. XBE[3:0]/XA[5:2] operate byte-enables XBE[3:0] during host-port accesses. XWE/XWAIT operates XWAIT output signal during host-port accesses. Addr
Figure C62x Master-Write
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN XW/R XW/R XBLAST XD[31:0] XRDY XBOFF XHOLD# XHOLDA# XW/R input/output polarity selected boot XBLAST output polarity always active low. XBE[3:0]/XA[5:2] operate byte-enables XBE[3:0] during host-port accesses. Internal arbiter enabled External arbiter enabled This diagram illustrates XBOFF timing. arbitration timing shown Figure Figure Addr
Figure C62x Master-BOFF Operation||
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION ASYNCHRONOUS HOST-PORT TIMING timing requirements with external device asynchronous master (see Figure Figure
tw(XCSL) tw(XCSH) tsu(XSEL-XCSL) th(XCSL-XSEL) th(XRYL-XCSL) tsu(XBEV-XCSH) th(XCSH-XBEV) tsu(XDV-XCSH) th(XCSH-XDV) Pulse duration, Pulse duration, high Setup time, expansion select signals valid before Hold time, expansion select signals valid after Hold time, after XRDY Setup time, XBE[3:0]/XA[5:2] valid before Hold time, XBE[3:0]/XA[5:2] valid after Setup time, valid before high Hold time, valid after high UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, Expansion select signals include XCNTL XR/W. XBE[3:0]/XA[5:2] operate byte-enables XBE[3:0] during host-port accesses.
switching characteristics over recommended operating conditions with external device asynchronous master (see Figure Figure
td(XCSL-XDLZ) td(XCSH-XDIV) td(XCSH-XDHZ) td(XRYL-XDV) PARAMETER Delay time, impedance Delay time, high invalid Delay time, high high impedance Delay time, XRDY valid UNIT
td(XCSH-XRYH) Delay time, high XRDY high *This parameter production tested. 1/CPU clock frequency example, when running parts MHz,
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
EXPANSION ASYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCNTL XBE[3:0]/XA[5:2] XR/W XR/W XD[31:0] Word XRDY XBE[3:0]/XA[5:2] operate byte-enables XBE[3:0] during host-port accesses. XW/R input/output polarity selected boot
Figure External Device Asynchronous Master-Read
XCNTL XBE[3:0]/XA[5:2] XR/W XR/W XD[31:0] XRDY XBE[3:0]/XA[5:2] operate byte-enables XBE[3:0] during host-port accesses. XW/R input/output polarity selected boot word Word
Figure External Device Asynchronous Master-Write
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
XHOLD/XHOLDA TIMING timing requirements expansion arbitration (internal arbiter enabled) (see Figure
toh(XHDAH-XHDH) Output hold time, XHOLD high after XHOLDA high *This parameter production tested. 1/CPU clock frequency example, when running parts MHz, UNIT
switching characteristics over recommended operating conditions expansion arbitration (internal arbiter enabled) (see Figure
td(XHDH-XBHZ) td(XBHZ-XHDAH) td(XHDL-XHDAL) td(XHDAL-XBLZ) PARAMETER Delay time, XHOLD high expansion high impedance Delay time, expansion high impedance XHOLDA high Delay time, XHOLD XHOLDA Delay time, XHOLDA expansion impedance UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, Expansion consists XBE[3:0]/XA[5:2], XAS, XW/R, XBLAST. pending expansion transactions allowed complete before XHOLDA asserted. Owns XHOLD (input) XHOLDA (output) Expansion C6203B/03C Expansion consists XBE[3:0]/XA[5:2], XAS, XW/R, XBLAST. C6203B/03C External Requestor Owns Owns
Figure Expansion Arbitration-Internal Arbiter Enabled
switching characteristics over recommended operating conditions expansion arbitration (internal arbiter disabled) (see Figure
td(XHDAH-XBLZ) td(XBHZ-XHDL) PARAMETER Delay time, XHOLDA high Expansion impedance Delay time, expansion high impedance XHOLD UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, Expansion consists XBE[3:0]/XA[5:2], XAS, XW/R, XBLAST. XHOLD (output) XHOLDA (input) Expansion Expansion consists XBE[3:0]/XA[5:2], XAS, XW/R, XBLAST. C6203B/03C
Figure Expansion Arbitration-Internal Arbiter Disabled
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements McBSP (see Figure
tc(CKRX) tw(CKRX) tsu(FRH-CKRL) th(CKRL-FRH) tsu(DRV-CKRL) th(CKRL-DRV) tsu(FXH-CKXL) th(CKXL-FXH) Cycle time, CLKR/X Pulse duration, CLKR/X high CLKR/X Setup time external high before CLKR time, Hold time, external high after CLKR time ternal Setup time, time valid before CLKR alid Hold time, valid after CLKR time alid Setup time ternal time, external high before CLKX Hold time external high after CLKX time, CLKR/X CLKR/X CLKR CLKR CLKR CLKR CLKR CLKR CLKR CLKR CLKX CLKX CLKX CLKX UNIT
*This parameter production tested. CLKRP CLKXP FSRP FSXP polarity signals inverted, then timing references that signal also inverted. 1/CPU clock frequency example, when running parts MHz, maximum rate C6203 device Mbps CPU/2 (the slower two). Care must taken ensure that timings specified this data sheet met. maximum rate McBSP-to-McBSP communications MHz; therefore, minimum CLKR/X clock cycle either twice cycle time (2P), (100 MHz), whichever value larger. example, when running parts ns), minimum CLKR/X clock cycle setting appropriate CLKGDV ratio external clock source). When running parts ns), MHz) minimum CLKR/X clock cycle. maximum rate McBSP-to-McBSP communications applies when serial port master clock frame syncs (with CLKR connected CLKX, connected FSX, CLKXM FSXM CLKRM FSRM data delay mode (R/XDATDLY 10b) other device McBSP communicates slave. minimum CLKR/X pulse duration either (P-1) whichever larger. example, when running parts ns), minimum CLKR/X pulse duration. When running parts ns), (P-1) minimum CLKR/X pulse duration.
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions McBSP (see Figure
td(CKSH-CKRXH) tc(CKRX) tw(CKRX) td(CKRH-FRV) td(CKXH-FXV) tdis(CKXH-DXHZ) td(CKXH-DXV) PARAMETER Delay time, CLKS high CLKR/X high internal CLKR/X generated from CLKS input Cycle time, CLKR/X Pulse duration, CLKR/X high CLKR/X Delay time, CLKR high internal valid Delay time, CLKX high internal valid Disable time, high impedance following last data from edance CLKX high Delay time, Dela time CLKX high valid alid Delay time, high valid ONLY applies when data delay (XDATDLY 00b) mode. CLKR/X CLKR/X CLKR CLKX CLKX CLKX CLKX CLKX CLKX UNIT
td(FXH-DXV)
*This parameter production tested. CLKRP CLKXP FSRP FSXP polarity signals inverted, then timing references that signal also inverted. Minimum delay times also represent minimum output hold times. 1/CPU clock frequency example, when running parts MHz, maximum rate C6203 device Mbps CPU/2 (the slower two). Care must taken ensure that timings specified this data sheet met. maximum rate McBSP-to-McBSP communications MHz; therefore, minimum CLKR/X clock cycle either twice cycle time (2P), (100 MHz), whichever value larger. example, when running parts ns), minimum CLKR/X clock cycle setting appropriate CLKGDV ratio external clock source). When running parts ns), MHz) minimum CLKR/X clock cycle. maximum rate McBSP-to-McBSP communications applies when serial port master clock frame syncs (with CLKR connected CLKX, connected FSX, CLKXM FSXM CLKRM FSRM data delay mode (R/XDATDLY 10b) other device McBSP communicates slave. sample rate generator input clock CLKSM 1/CPU clock frequency) sample rate generator input clock P_clks CLKSM (P_clks CLKS period) CLKX high pulse width (CLKGDV/2 CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKX pulse width (CLKGDV/2) CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKGDV should appropriately ensure McBSP rate does exceed 100-MHz limit.
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS CLKR (int) (ext) CLKX (int) (ext) (XDATDLY=00b) Bit(n-1) (n-2) (n-3) Bit(n-1) (n-2) (n-3)
Figure McBSP Timings
timing requirements when GSYNC (see Figure
tsu(FRH-CKSH) th(CKSH-FRH) Setup time, high before CLKS high Hold time, high after CLKS high UNIT
*This parameter production tested.
CLKS external CLKR/X need resync) CLKR/X (needs resync)
Figure Timing When GSYNC
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements McBSP master slave: CLKSTP 10b, CLKXP (see Figure
MASTER tsu(DRV-CKXL) th(CKXL-DRV) Setup time, valid before CLKX Hold time, valid after CLKX SLAVE UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV
switching characteristics over recommended operating conditions McBSP master slave: CLKSTP 10b, CLKXP (see Figure
th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) tdis(FXH-DXHZ) PARAMETER Hold time, after CLKX Delay time, CLKX high# Delay time, CLKX high valid Disable time, high impedance following last data from CLKX Disable time, high impedance following last data from high SLAVE UNIT
td(FXL-DXV) Delay time, valid *This parameter production tested. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV sample rate generator input clock CLKSM 1/CPU clock frequency) sample rate generator input clock P_clks CLKSM (P_clks CLKS period) CLKX period CLKGDV) CLKX high pulse width (CLKGDV/2 CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKX pulse width (CLKGDV/2) CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKGDV should appropriately ensure McBSP rate does exceed 100-MHz limit. FSRP FSXP master, inverted provide active-low slave-enable output. slave, active-low signal input inverted before being used internally. CLKXM FSXM CLKRM FSRM master McBSP CLKXM CLKRM FSXM FSRM slave McBSP should before rising edge clock enable slave devices then begin transfer rising edge master clock (CLKX).
CLKX Bit(n-1) Bit(n-1) (n-2) (n-3) (n-4) (n-2) (n-3) (n-4)
Figure McBSP Timing Master Slave: CLKSTP 10b, CLKXP
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements McBSP master slave: CLKSTP 11b, CLKXP (see Figure
MASTER tsu(DRV-CKXH) th(CKXH-DRV) Setup time, valid before CLKX high Hold time, valid after CLKX high SLAVE UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV
switching characteristics over recommended operating conditions McBSP master slave: CLKSTP 11b, CLKXP (see Figure
th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) tdis(CKXL-DXHZ) PARAMETER Hold time, after CLKX Delay time, CLKX high# Delay time, CLKX valid Disable time, high impedance following last data from CLKX SLAVE UNIT
td(FXL-DXV) Delay time, valid *This parameter production tested. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV sample rate generator input clock CLKSM 1/CPU clock frequency) sample rate generator input clock P_clks CLKSM (P_clks CLKS period) CLKX period CLKGDV) CLKX high pulse width (CLKGDV/2 CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKX pulse width (CLKGDV/2) CLKGDV even (CLKGDV 1)/2 CLKGDV zero maximum transfer rate mode limited above timing constraints. FSRP FSXP master, inverted provide active-low slave-enable output. slave, active-low signal input inverted before being used internally. CLKXM FSXM CLKRM FSRM master McBSP CLKXM CLKRM FSXM FSRM slave McBSP should before rising edge clock enable slave devices then begin transfer rising edge master clock (CLKX).
CLKX Bit(n-1) Bit(n-1) (n-2) (n-2) (n-3) (n-4) (n-3) (n-4)
Figure McBSP Timing Master Slave: CLKSTP 11b, CLKXP
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements McBSP master slave: CLKSTP 10b, CLKXP (see Figure
MASTER tsu(DRV-CKXH) th(CKXH-DRV) Setup time, valid before CLKX high Hold time, valid after CLKX high SLAVE UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV
switching characteristics over recommended operating conditions McBSP master slave: CLKSTP 10b, CLKXP (see Figure
th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) tdis(CKXH-DXHZ) tdis(FXH-DXHZ) PARAMETER Hold time, after CLKX Delay time, CLKX low# Delay time, CLKX valid Disable time, high impedance following last data from CLKX high Disable time, high impedance following last data from high SLAVE UNIT
td(FXL-DXV) Delay time, valid *This parameter production tested. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV sample rate generator input clock CLKSM 1/CPU clock frequency) sample rate generator input clock P_clks CLKSM (P_clks CLKS period) CLKX period CLKGDV) CLKX high pulse width (CLKGDV/2 CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKX pulse width (CLKGDV/2) CLKGDV even (CLKGDV 1)/2 CLKGDV zero maximum transfer rate mode limited above timing constraints. FSRP FSXP master, inverted provide active-low slave-enable output. slave, active-low signal input inverted before being used internally. CLKXM FSXM CLKRM FSRM master McBSP CLKXM CLKRM FSXM FSRM slave McBSP should before rising edge clock enable slave devices then begin transfer rising edge master clock (CLKX).
CLKX Bit(n-1) Bit(n-1) (n-2) (n-3) (n-4) (n-2) (n-3) (n-4)
Figure McBSP Timing Master Slave: CLKSTP 10b, CLKXP
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements McBSP master slave: CLKSTP 11b, CLKXP (see Figure
MASTER tsu(DRV-CKXL) th(CKXL-DRV) Setup time, valid before CLKX Hold time, valid after CLKX SLAVE UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV
switching characteristics over recommended operating conditions McBSP master slave: CLKSTP 11b, CLKXP (see Figure
th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) PARAMETER Hold time, after CLKX Delay time, CLKX low# Delay time, CLKX high valid Disable time, high impedance following last data from CLKX high SLAVE UNIT
td(FXL-DXV) Delay time, valid *This parameter production tested. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV sample rate generator input clock CLKSM 1/CPU clock frequency) sample rate generator input clock P_clks CLKSM (P_clks CLKS period) CLKX period CLKGDV) CLKX high pulse width (CLKGDV/2 CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKX pulse width (CLKGDV/2) CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKGDV should appropriately ensure McBSP rate does exceed 100-MHz limit. FSRP FSXP master, inverted provide active-low slave-enable output. slave, active-low signal input inverted before being used internally. CLKXM FSXM CLKRM FSRM master McBSP CLKXM CLKRM FSXM FSRM slave McBSP should before rising edge clock enable slave devices then begin transfer rising edge master clock (CLKX).
CLKX Bit(n-1) Bit(n-1) (n-2) (n-2) (n-3) (n-4) (n-3) (n-4)
Figure McBSP Timing Master Slave: CLKSTP 11b, CLKXP
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
DMAC, TIMER, POWER-DOWN TIMING switching characteristics over recommended operating conditions DMAC outputs (see Figure
PARAMETER *2P-3 UNIT tw(DMACH) Pulse duration, DMAC high *This parameter production tested. 1/CPU clock frequency example, when running parts MHz, DMAC[3:0]
Figure DMAC Timing
timing requirements timer inputs (see Figure
tw(TINPH) tw(TINPL) Pulse duration, TINP high Pulse duration, TINP UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz,
switching characteristics over recommended operating conditions timer outputs (see Figure
tw(TOUTH) tw(TOUTL) Pulse duration, TOUT high Pulse duration, TOUT PARAMETER *2P-3 *2P-3 UNIT
*This parameter production tested. 1/CPU clock frequency example, when running parts MHz, TINPx TOUTx
Figure Timer Timing
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED) switching characteristics over recommended operating conditions power-down outputs (see Figure
PARAMETER *2P-3 UNIT tw(PDH) Pulse duration, high *This parameter production tested. 1/CPU clock frequency example, when running parts MHz,
Figure Power-Down Timing
JTAG TEST-PORT TIMING timing requirements JTAG test port (see Figure
tc(TCK) tsu(TDIV-TCKH) Cycle time, Setup time, TDI/TMS/TRST valid before high UNIT
th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after high *This parameter production tested.
switching characteristics over recommended operating conditions JTAG test port (see Figure
PARAMETER *-4.5 *13.5 UNIT td(TCKL-TDOV) Delay time, valid *This parameter production tested.
TDI/TMS/TRST
Figure JTAG Test-Port Timing
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SMJ320C6203 FIXED POINT DIGITAL SIGNAL PROCESSOR
MECHANICAL DATA
(S-CBGA-N429)
27,20 26,80
CERAMIC BALL GRID ARRAY
25,40 1,27
1,27
1,22 1,00
3,30
Seating Plane 0,90 0,60 0,10 0,15 4164732/A 08/98
0,70 0,50
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MO-156 Flip chip application only
thermal resistance characteristics (S-CBGA package)
Junction-to-Board, measured soldering thermocouple middle traces board edge package RJMA Junction Moving Junction-to-Moving-Air Junction-to-Case, measured bottom solder ball Junction-to-Case, measured package Junction-to-Ambient °C/W 14.5 11.8 11.1 10.2 Flow
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device 5962-0051001QXA SM320C6203GLPM20 SMJ320C6203GLPM20
Status ACTIVE ACTIVE ACTIVE
Package Type FC/CSP FC/CSP FC/CSP
Package Drawing
Pins Package Plan None None None
Lead/Ball Finish Call Call Call
Peak Temp Call Call Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight.
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDECindustry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
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