Industry-standard pinouts, timing, functions packages High-performance

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Industry-standard pinouts, timing, functions packages High-performance

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MT4C16270 256K
Industry-standard pinouts, timing, functions packages High-performance CMOS silicon-gate process Single ±10% power supply* power, standby; 300mW active, typical device pins TTL-compatible 512-cycle refresh row- column addresses) Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) HIDDEN Extended Data-Out (EDO) PAGE MODE access cycle BYTE WRITE BYTE READ access cycles
256K PAGE MODE
ASSIGNMENT (Top View) 40-Pin (DA-6)
OPTIONS
Timing 40ns access 50ns access 60ns access Packages Plastic (400 mil)
MARKING
Part Number Example: MT4C16270DJ-4
*40ns 50ns access specifications limited range ±5%. Contact factory availability.
TIMING PARAMETERS
SPEED
tRAC tCAC tCAS
75ns 100ns 110ns
40ns 50ns 60ns
15ns 20ns 25ns
20ns 25ns 30ns
12ns 15ns 15ns
10ns
10ns
RAS#
DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 CASL# CASH#
GENERAL DESCRIPTION
MT4C16270 randomly accessed solid-state memory containing 4,194,304 bits organized configuration. MT4C16270 both BYTE WRITE WORD WRITE access cycles CAS# pins. MT4C16270 CAS# function timing determined first CAS# (CASL# CASH#) transition last transition back HIGH. CASL# CASH# function similar manner CAS# that either
MT4C16270 W06.pm5 Rev. 10/96
CASL# CASH# will generate internal CAS#. only results BYTE WRITE cycle. CASL# transitioning selects WRITE cycle lower byte (DQ1-DQ8) CASH# transitioning selects WRITE cycle upper byte (DQ9-DQ16). BYTE READ cycles achieved through CASL# CASH# same manner.
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K FUNCTIONAL BLOCK DIAGRAM
CASL# CASH#
CAS#
CONTROL LOGIC
DATA-IN BUFFER
CLOCK GENERATOR DATA-OUT BUFFER
DQ16
COLUMNADDRESS BUFFER REFRESH CONTROLLER
COLUMN DECODER
SENSE AMPLIFIERS GATING REFRESH COUNTER
DECODER
ROWADDRESS BUFFERS
MEMORY ARRAY
RAS#
CLOCK GENERATOR
FUNCTIONAL DESCRIPTION
Each uniquely addressed through address bits during READ WRITE cycles. These entered bits -A8) time. RAS# used latch first bits CAS# latter bits. CAS# control also determines whether cycle will refresh cycle (RAS#-ONLY) active cycle (READ, WRITE READ WRITE) once RAS# goes LOW. MT4C16270 CAS# controls, CASL# CASH#. CASL# CASH# inputs internally generate CAS# signal functioning similar manner single CAS# input other 256K DRAMs. difference that each CAS# controls corresponding tristate logic conjunction with RAS#). CASL# controls through CASH# controls through DQ16.
MT4C16270 W06.pm5 Rev. 10/96
MT4C16270 CAS# function determined first CAS# (CASL# CASH# transitioning last transitioning back HIGH. CAS# controls give MT4C16270 both byte READ byte WRITE cycle capabilities. (See Figure logic HIGH dictates READ mode while logic dictates WRITE mode. During WRITE cycle, data-in latched falling edge CAS# (CASL# CASH#), whichever occurs last. EARLY WRITE occurs when taken prior either CAS# falling. LATE WRITE READ-MODIFY-WRITE occurs when falls after CAS# (CASL# CASH#) taken LOW. During EARLY WRITE cycles, data-outputs will remain High-Z regardless state OE#. During LATE WRITE READ-MODIFY-WRITE cycles, must
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K WORD WRITE RAS# LOWER BYTE WRITE
CASL#
CASH#
STORED DATA
INPUT DATA
INPUT DATA
STORED STORED DATA DATA
INPUT DATA
INPUT DATA
STORED DATA
LOWER BYTE (DQ1-DQ8) WORD
UPPER BYTE (DQ9-DQ16) WORD
ADDRESS
ADDRESS EFFECTIVE (DON'T CARE)
Figure WORD BYTE WRITE EXAMPLE
WORD READ RAS# LOWER BYTE READ
CASL#
CASH#
LOWER BYTE (DQ1-DQ8) WORD
STORED DATA
OUTPUT DATA
OUTPUT DATA
STORED STORED DATA DATA
OUTPUT DATA
OUTPUT DATA
STORED DATA
UPPER BYTE (DQ9-DQ16) WORD
ADDRESS High-Z
ADDRESS
Figure WORD BYTE READ EXAMPLE
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K
FUNCTIONAL DESCRIPTION (continued)
taken HIGH disable data-outputs prior applying input data. LATE WRITE READ-MODIFYWRITE attempted while keeping LOW, write will occur, data-outputs will drive read data from accessed location. Additionally, both bytes must always same mode operation both bytes active. CAS# precharge must satisfied prior changing modes operation between upper lower bytes. example, EARLY WRITE byte LATE WRITE other byte allowed during same cycle. However, EARLY WRITE byte and, after CAS# precharge been satisfied, LATE WRITE other byte permissable. data inputs data outputs routed through pins using common I/O, direction controlled OE#, RAS#. PAGE MODE operations allow faster data operations (READ, WRITE READ-MODIFY-WRITE) within row-address-defined -A8) page boundary. PAGE MODE cycle always initiated with address strobed-in RAS# followed column address strobed-in CAS#. CAS# toggled holding RAS# strobing-in different column-addresses, thus executing faster memory cycles. Returning RAS# HIGH terminates PAGE MODE operation. BYTE ACCESS CYCLE BYTE WRITE cycle determined CASL# CASH#. Enabling CASL# will select lower BYTE WRITE cycle (DQ1-DQ8) while enabling CASH# will select upper BYTE WRITE cycle (DQ9-DQ16). Enabling both CASL# CASH# selects WORD WRITE cycle. MT4C16270 viewed 256K DRAMs which have common input controls. Figure illustrates MT4C16270 BYTE WRITE WORD WRITE cycles. BYTE READ accomplished same manner.
RAS#
CASL#/CASH#
ADDR
COLUMN
COLUMN
COLUMN
COLUMN
OPEN
VALID DATA
VALID DATA
VALID DATA OEHC
VALID DATA
VALID DATA
back Low-Z tOES met.
remain High-Z until next CAS# cycle tOEHC met.
remain High-Z until next CAS# cycle tOEP met. DON'T CARE UNDEFINED
Figure OUTPUT ENABLE DISABLE
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K
PAGE MODE DRAM READ cycles have traditionally turned output buffers (High-Z) with rising edge CAS#. CAS# goes HIGH, (active), output buffers will disabled. MT4C16270 offers accelerated PAGE MODE cycle eliminating output disable from CAS# HIGH. This option called allows CAS# precharge time (tCP) occur without output data going invalid (see READ EDO-PAGE-MODE READ waveforms). operates DRAM READ FAST-PAGEMODE READ, except data will held valid after CAS# goes HIGH, long RAS# held held HIGH. brought HIGH while CAS# RAS# LOW, will transition between valid data High-Z. Using OE#, there methods disable outputs keep them disabled during CAS# HIGH time. first method have HIGH when CAS# transitions HIGH keep HIGH tOEHC. This will tristate they will remain tristate, regardless OE#, until CAS# falls again. second method have when CAS#
transitions HIGH. Then pulse HIGH minimum tOEP anytime during CAS# HIGH period will tristate remain tristate, regardless OE#, until CAS# falls again (please reference Figure further detail toggling condition). During other cycles, outputs disabled tOFF time after RAS# CAS# HIGH, tWHZ after transitions LOW. tOFF time referenced from rising edge RAS# CAS#, whichever occurs last. also perform function turning output drivers under certain conditions, shown Figure Returning RAS# CAS# HIGH terminates memory cycle decreases chip current reduced standby level. chip also preconditioned next cycle during RAS# HIGH time. Memory cell data retained correct state maintaining power executing RAS# cycle (READ, WRITE) RAS# refresh cycle (RAS#-ONLY, CBR, HIDDEN) that combinations RAS# addresses (A0-A8) executed least every 8ms, regardless sequence. REFRESH cycle will also invoke refresh counter controller address control.
RAS#
CASL#/CASH#
ADDR
COLUMN
COLUMN
COLUMN
COLUMN
OPEN
VALID DATA
VALID DATA
INPUT DATA
High-Z falls, tWPZ met, will remain High-Z until CAS# goes with HIGH (i.e., until READ cycle initiated).
used disable prepare input data EARLY WRITE cycle. will remain High-Z until CAS# goes with HIGH (i.e., until READ cycle initiated).
DON'T CARE UNDEFINED
Figure OUTPUT ENABLE DISABLE WITH
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K
TRUTH TABLE
ADDRESSES FUNCTION Standby READ: WORD READ: LOWER BYTE READ: UPPER BYTE WRITE: WORD (EARLY WRITE) WRITE: LOWER BYTE (EARLY) WRITE: UPPER BYTE (EARLY) READ WRITE EDO-PAGEMODE READ EDO-PAGEEDO1st Cycle Cycle Cycle Cycle Cycle MODE WRITE Cycle PAGE-MODE Cycle READ-WRITE HIDDEN REFRESH READ WRITE RAS# CASL# CASH#
High-Z Data-Out Lower Byte, Data-Out Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data Data-In Lower Byte, Data-In Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-In Data-Out, Data-In Data-Out Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out Data-In High-Z High-Z
NOTES
RAS#-ONLY REFRESH REFRESH NOTE:
These WRITE cycles also BYTE WRITE cycles (either CASL# CASH# active). These READ cycles also BYTE READ cycles (either CASL# CASH# active). EARLY WRITE only. least CAS# signals must active (CASL# CASH#).
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage Relative Operating Temperature, (ambient) +70°C Storage Temperature (plastic) -55°C +150°C Power Dissipation 1.2W Short Circuit Output Current 50mA
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
(Notes: (VCC ±10%)** PARAMETER/CONDITION Supply Voltage Input High (Logic Voltage, inputs Input (Logic Voltage, inputs INPUT LEAKAGE CURRENT input +1.0V (All other pins under test OUTPUT LEAKAGE CURRENT disabled; VOUT VCC) OUTPUT LEVELS Output High Voltage (IOUT -2.5mA) Output Voltage (IOUT 2.1mA) SYMBOL VCC** -1.0 VCC+1 UNITS NOTES
PARAMETER/CONDITIONS STANDBY CURRENT: (TTL) (RAS# CAS# VIH) STANDBY CURRENT: (CMOS) (RAS# CAS# -0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: [MIN]) OPERATING CURRENT: PAGE MODE Average power supply current (RAS# VIL, CAS#, address cycling: [MIN]; tCP, tASC 10ns) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS#=VIH: [MIN]) REFRESH CURRENT: Average power supply current (RAS#, CAS#, address cycling: [MIN])
SYMBOL ICC1 ICC2
UNITS
NOTES
ICC3
ICC4
ICC5
ICC6
**40 50ns specifications limited range ±5%.
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K
CAPACITANCE
PARAMETER Input Capacitance: A0-A8 Input Capacitance: RAS#, CASL#, CASH#, WE#, Input/Output Capacitance: SYMBOL UNITS NOTES
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
(Notes: (VCC ±10%)*
CHARACTERISTICS PARAMETER Access time from column-address Column-address setup CAS# precharge during WRITE Column-address hold time (referenced RAS#) Column-address setup time Row-address setup time Column-address delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR REFRESH) Last CAS# going first CAS# returning HIGH CAS# output Low-Z Data output hold after CAS# CAS# precharge time Access time from CAS# precharge CAS# RAS# precharge time CAS# hold time CAS# setup time (CBR REFRESH) CAS# delay time Write command CAS# lead time Data-in hold time Data-in setup time Output disable time Output Enable time hold time from during READ-MODIFY-WRITE cycle HIGH hold time from CAS# HIGH HIGH pulse width CAS# HIGH setup time Output buffer turn-off delay from CAS# RAS# tACH
tASC tASR tAWD tCAC tCAH tCAS tCHR tCLCH tCLZ tCOH tCPA tCRP tCSH tCSR tCWD tCWL tOEH tOEHC tOEP tOES tOFF
10,000
UNITS NOTES
10,000
10,000
*40ns 50ns specifications limited range ±5%.
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
(Notes: (Vcc ±10%)*
CHARACTERISTICS PARAMETER setup prior RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# column-address delay time Row-address hold time Column-address RAS# lead time RAS# pulse width RAS# pulse width (EDO PAGE MODE) Random READ WRITE cycle time RAS# CAS# delay time Read command hold time (referenced CAS#) Read command setup time Refresh period (512 cycles) RAS# precharge time RAS# CAS# precharge time Read command hold time (referenced RAS#) RAS# hold time READ WRITE cycle time RAS# delay time Write command RAS# lead time Transition time (rise fall) Write command hold time Write command hold time (referenced RAS#) Write command setup time Output disable delay from Write command pulse width pulse widths disable outputs hold time (CBR REFRESH) setup time (CBR REFRESH) tORD
tPRWC tRAC tRAD tRAH tRAL tRAS tRASP tRCD tRCH tRCS tREF tRPC tRRH tRSH tRWC tRWD tRWL tWCH tWCR tWCS tWHZ tWPZ tWRH tWRP
UNITS NOTES
10,000 100,000
10,000 100,000
10,000 100,000
*40ns 50ns specifications limited range ±5%.
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K
NOTES
voltages referenced VSS. This parameter sampled. 4.75V; MHz. pins assumed left floating tested leakage. dependent output loading cycle rates. Specified values obtained with minimum cycle time output open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range (0°C 70°C) assured. initial pause 100µs required after power-up followed eight RAS# refresh cycles (RAS#-ONLY CBR) before proper device operation assured. eight RAS# cycle wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 2ns. (MIN) (MAX) reference levels measuring timing input signals. Transition times measured between between VIH). addition meeting transition rate specification, input signals must transit between between VIH) monotonic manner. CAS# RAS# data output High-Z. CAS# data output contain data from last valid READ cycle. Measured with load equivalent gate 50pF, 0.8V 2.0V. Assumes that tRCD tRCD (MAX). tRCD greater than maximum recommended value shown this table, tRAC will increase amount that tRCD exceeds value shown. Assumes that tRCD tRCD (MAX). CAS# falling edge RAS#, will maintained from previous cycle. initiate cycle clear buffer, CAS# RAS# must pulsed HIGH tCP. tRCD (MAX) limit longer specified. tRCD (MAX) specified reference point only. tRCD greater than specified tRCD (MAX) limit, then access time controlled exclusively tCAC [tRAC (MIN) longer applied]. With without tRCD (MAX) limit, (MIN), tRAC (MIN) tCAC (MIN) must always met. tRAD (MAX) limit longer specified. tRAD (MAX) specified reference point only. tRAD greater than specified tRAD (MAX) limit, then access time controlled exclusively [tRAC (MIN) tCAC (MIN) longer applied]. With without tRAD (MAX) limit, (MIN), tRAC (MIN) tCAC (MIN) must always met. Either tRCH tRRH must satisfied READ cycle. tOFF (MAX) defines time which output achieves open circuit condition; reference VOL. tWCS, tRWD, tAWD tCWD restrictive operating parameters LATE WRITE READMODIFY-WRITE cycles only. tWCS tWCS (MIN), cycle EARLY WRITE cycle data output will remain open circuit throughout entire cycle. tRWD tRWD (MIN), tAWD tAWD (MIN) tCWD tCWD (MIN), cycle READ-WRITE data output will contain data read from selected cell. neither above conditions met, state access time until CAS# RAS# back indeterminate. held HIGH taken after CAS# goes result LATE WRITE (OE#controlled) cycle. These parameters referenced CAS# leading edge EARLY WRITE cycles leading edge LATE WRITE READ-MODIFY-WRITE cycles. During READ cycle, then taken HIGH before CAS# goes HIGH, goes open. tied permanently LOW, LATE WRITE READMODIFY-WRITE operation possible. HIDDEN REFRESH also performed after WRITE cycle. this case, HIGH. other inputs -0.2V. Write command defined going LOW. LATE WRITE READ-MODIFY-WRITE cycles must have both tOEH (OE# HIGH during WRITE cycle) order ensure that output buffers will open during WRITE cycle. will provide previously written data CAS# remains taken back after tOEH met.
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K
NOTES (continued)
open during READ cycles once tOFF occur. first CAS#x edge transition LOW. last CAS#x edge transition HIGH. Output parameter (DQx) referenced corresponding CAS# input, DQ1-DQ8 CASL# DQ9-DQ16 CASH#. Last falling CAS#x edge first rising CAS#x edge. Last rising CAS#x edge next cycle's last rising CAS#x edge. Last rising CAS#x edge first falling CAS#x edge. First controlled first CAS#x LOW. Last controlled last CAS#x HIGH. Each CAS#x must meet minimum pulse width. Last CAS#x LOW. controlled, regardless CASL# CASH#. Column address changed once each cycle. minimum parameter guaranteed design.
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K READ CYCLE
tRAS
RAS#
tCSH tRSH tCRP tRCD tCAS tCLCH tRRH
CASH#/CASL#
tRAD tASR tRAH tASC tRAL tCAH
ADDR
tRCS
COLUMN tRCH
tRAC tCAC tCLZ NOTE tOFF
OPEN
VALID DATA
OPEN
DON'T CARE UNDEFINED
TIMING PARAMETERS
tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tOES
10,000 10,000
UNITS 10,000 tOFF
tRAC tRAD tRAH tRAL tRAS tRCD tRCH tRCS tRRH tRSH
UNITS
10,000
10,000
10,000
NOTE: tOFF referenced from rising edge RAS# CAS#, whichever occurs last.
MT4C16270 W06.pm5 Rev. 10/96 Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K EARLY WRITE CYCLE
tRAS
RAS#
tCSH tRSH tCRP tRCD tCAS tCLCH
CASL#/CASH#
tRAD tASR tRAH tASC tRAL tCAH tACH
ADDR
COLUMN tCWL tRWL tWCR tWCS tWCH
VALID DATA
DON'T CARE UNDEFINED
TIMING PARAMETERS
tACH
tASC tASR tCAH tCAS tCLCH tCRP tCSH tCWL tRAD
10,000 10,000
UNITS 10,000 tRAH
tRAL tRAS tRCD tRSH tRWL tWCH tWCR tWCS
UNITS
10,000
10,000
10,000
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K READ WRITE CYCLE (LATE WRITE READ-MODIFY-WRITE cycles)
tRWC tRAS
RAS#
tCSH tRSH tCRP tRCD tCAS tCLCH
CASL#/CASH#
tRAD tASR tRAH tASC tRAL tCAH tACH
ADDR
COLUMN tRWD tRCS tCWD tAWD tCWL tRWL
tRAC tCAC
OPEN
VALID
VALID tOEH
OPEN
DON'T CARE UNDEFINED
TIMING PARAMETERS
tACH tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tCWD tCWL
10,000 10,000
UNITS 10,000
tOEH tRAC tRAD tRAH tRAL tRAS tRCD tRCS tRSH tRWC tRWD tRWL
10,000
10,000
UNITS
10,000
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K EDO-PAGE-MODE READ CYCLE
tRASP
RAS#
tCSH tCRP tRCD tCAS, tCLCH (NOTE tCAS, tCLCH tRSH tCAS, tCLCH
CASH#/CASL#
tRAD tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRAL
ADDR
COLUMN
COLUMN
COLUMN
tRRH
tRCS tRAC tCAC tCLZ OPEN tOES tCOH VALID DATA VALID DATA tCPA tCAC tCLZ tCPA tCAC
tRCH
tOFF VALID DATA tOES OPEN
tOEHC
tOEP
DON'T CARE UNDEFINED
TIMING PARAMETERS
tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCOH tCPA tCRP tCSH
10,000
UNITS 10,000 tOEHC tOEP
tOES tOFF tRAC tRAD tRAH tRAL tRASP tRCD tRCH tRCS tRRH tRSH
100,000
100,000
UNITS 100,000
10,000
NOTE: measured from falling edge CAS# falling edge CAS#, from rising edge CAS# rising edge CAS#. Both measurements must meet specification.
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP
RAS#
tCSH tCRP tRCD tCAS, tCLCH tCAS, tCLCH tRSH tCAS, tCLCH
CASL#/CASH#
tRAD tASR tRAH tASC tACH tCAH tASC tACH tCAH tASC tACH tRAL tCAH
ADDR
COLUMN tCWL tWCS tWCH
COLUMN tCWL tWCS tWCH
COLUMN tCWL tWCS tWCH
tWCR tRWL
VALID DATA
VALID DATA
VALID DATA
DON'T CARE UNDEFINED
TIMING PARAMETERS
tACH tASC tASR tCAH tCAS tCLCH tCRP tCSH tCWL
UNITS
tRAD tRAH tRAL tRASP tRCD tRSH tRWL tWCH tWCR tWCS
100,000
100,000
UNITS 100,000
10,000
10,000
10,000
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE READ-MODIFY-WRITE cycles)
tRASP
RAS#
tCSH tCRP tRCD tCAS, tCLCH tPRWC NOTE tCAS, tCLCH tRSH tCAS, tCLCH
CAS#L/CASH#
tRAD tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRAL
ADDR
COLUMN tRWD tRCS tCWL tAWD tCWD
COLUMN
COLUMN tRWL tCWL
tAWD tCWD
tAWD tCWD
tCWL
tRAC tCAC tCLZ tCPA tCAC tCLZ VALID VALID VALID VALID tCPA tCAC tCLZ VALID VALID OPEN
OPEN
DON'T CARE UNDEFINED
TIMING PARAMETERS
tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCPA tCRP tCSH tCWD tCWL
10,000 10,000
UNITS 10,000
tOEH tPRWC tRAC tRAD tRAH tRAL tRASP tRCD tRCS tRSH tRWD tRWL
100,000
100,000
UNITS 100,000
NOTE: measured from falling edge falling edge CAS#, from rising edge rising edge CAS#. Both measurements must meet specification.
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY-WRITE)
RASP
RAS#
tASR
CASL#/CASH#
ADDR
COLUMN
COLUMN
COLUMN
OPEN
VALID DATA
VALID DATA
VALID DATA
DON'T CARE UNDEFINED
TIMING PARAMETERS
tACH tASC tASR tCAC tCAH tCAS tCOH tCPA tCRP tCSH
10,000
UNITS 10,000
tRAC tRAD tRAH tRAL tRASP tRCD tRCH tRCS tRSH tWCH tWCS tWHZ
100,000
100,000
UNITS 100,000
10,000
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K READ CYCLE (with WE#-controlled disable)
RAS#
tCSH tCRP tRCD tCAS
CASL#/CASH#
tRAD tASR tWRP tRAH tASC tCAH tASC
ADDR
tWRH tRCS
COLUMN tRCH tWPZ tRCS
COLUMN
NOTE
tRAC tCAC tCLZ tWHZ tCLZ
OPEN
VALID DATA
OPEN
DON'T CARE UNDEFINED
TIMING PARAMETERS
tASC tASR tCAC tCAH tCAS tCLZ tCRP tCSH
10,000
UNITS 10,000
tRAC tRAD tRAH tRCH tRCD tRCS tWHZ tWPZ tWRH tWRP
UNITS
10,000
NOTE: Although "don't care" RAS# time during access cycle (READ WRITE), system designer should implement HIGH tWRP tWRH. This design implementation will facilitate compatibility with future DRAMs.
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K RAS#-ONLY REFRESH CYCLE (OE#, DON'T CARE)
tRAS
RAS#
tCRP tASR tRAH tRPC
CASL#/CASH#
ADDR
OPEN tWRP tWRH NOTE tWRP tWRH
REFRESH CYCLE (Addresses; DON'T CARE)
RAS# tRPC CASH#, CASL# OPEN tCSR tCHR tRPC tCSR tCHR tRAS tRAS
DON'T CARE UNDEFINED
TIMING PARAMETERS
tASR tCHR
tCRP tCSR tRAH
UNITS tRAS
tRPC tWRH tWRP
10,000
10,000
10,000 UNITS
NOTE: Although "don't care" RAS# time during access cycle (READ WRITE), system designer should implement HIGH tWRP tWRH. This design implementation will facilitate compatibility with future DRAMs.
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K HIDDEN REFRESH CYCLE (WE# HIGH; LOW)
tRAS tRAS
RAS#
tCRP tRCD tRSH tCHR
CASL#/CASH#
tRAD tASR tRAH tASC tRAL tCAH
ADDR
COLUMN tRAC tCAC tCLZ NOTE tOFF
OPEN
VALID DATA
OPEN
tORD
DON'T CARE UNDEFINED
TIMING PARAMETERS
tASC tASR tCAC tCAH tCHR tCLZ tCRP
UNITS tOFF
tORD tRAC tRAD tRAH tRAL tRAS tRCD tRSH
10,000
10,000
UNITS
10,000
NOTE: tOFF referenced from rising edge RAS# CAS#, whichever occurs last.
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.
MT4C16270 256K 40-PIN PLASTIC (400 mil) DA-6
1.029 (26.14) 1.023 (25.98)
.405 (10.29) .399 (10.13) .445 (11.30) .435 (11.05)
INDEX
.050 (1.27) .950 (24.13)
.032 (0.81) .026 (0.66)
.150 (3.81) .138 (3.51)
.105 (2.67) .090 (2.29)
SEATING PLANE
.037 (0.94) DAMBAR PROTRUSION
.020 (0.51) .015 (0.38)
.380 (9.65) .360 (9.14)
.025 (0.64)
NOTE:
dimensions inches (millimeters) typical where noted. Package width length include mold protrusion; allowable mold protrusion .01" side.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900, Micron DataFax: 208-368-5800 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
MT4C16270 W06.pm5 Rev. 10/96
Micron Technology, Inc., reserves right change products specifications without notice. ©1996, Micron Technology, Inc.

Industry-standard pinouts, timing, functions packages High-performance

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