Preliminary CMOS SRAM 512K Super Power Voltage Full CMOS Static

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Preliminary CMOS SRAM 512K Super Power Voltage Full CMOS Static

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K6F8016R6D Family
Preliminary CMOS SRAM
512K Super Power Voltage Full CMOS Static
Revision History
Revision History
Initial draft Revised Updated parameters (ICC1, ICC2, ISB1, IDR) Deleted 55ns Speed
Draft Date
April 2004 September 2004
Remark
Preliminary Preliminary
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision September 2004
K6F8016R6D Family
FEATURES
Process Technology: Full CMOS Organization: 512K Power Supply Voltage: 1.65~1.95V Data Retention Voltage: 1.0V(Min) Three State Outputs Package Type: 48-FBGA-6.00x7.00
Preliminary CMOS SRAM
GENERAL DESCRIPTION
K6F8016R6D families fabricated SAMSUNGs advanced full CMOS process technology. families support industrial operating temperature ranges have chip scale package user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
512K Super Power Voltage Full CMOS Static
PRODUCT FAMILY
Power Dissipation Product Family K6F8016R6D-F Operating Temperature Industrial(-40~85°C) Range 1.65~1.95V Speed 70ns Standby (ISB1, Typ.) 0.5µA2) Operating (ICC1, Max) Type 48-FBGA-6.00x7.00
Typical value measured VCC=2.0V, TA=25°C 100% tested.
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
I/O9
I/O1
Addresses
select
I/O10
I/O11
I/O2
I/O3
Memory array 1024 rows columns
I/O12
I/O4
Data cont Data cont Data cont Circuit Column select
I/O13
I/O5
I/O1~I/O8
I/O9~I/O16
I/O15
I/O14
I/O6
I/O7
I/O16
I/O8 Column Addresses
48-FBGA: View (Ball Down)
Control Logic
Name
Function
Name
Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8)
CS1, Chip Select Inputs A0~A18 Output Enable Input Write Enable Input Address Inputs
I/O1~I/O16 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision September 2004
K6F8016R6D Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C) Part Name K6F8016R6D-FF70 Function 48-FBGA, 70ns, 1.8V
Preliminary CMOS SRAM
FUNCTIONAL DESCRIPTION
I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z
I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z
Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Standby Standby Active Active Active Active Active Active Active Active
means dont care. (Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT TSTG Ratings -0.2 VCC+0.3V(Max. 2.5V) -0.2 Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted used under recommended operating condition. Exposure absolute maximum rating conditions extended period affect reliability.
Revision September 2004
K6F8016R6D Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol 1.65 -0.2
Preliminary CMOS SRAM
1.95 Vcc+0.2
Unit
Note: TA=-40 85°C, otherwise specified. Overshoot: VCC+1.0V case pulse width 20ns. Undershoot: -1.0V case pulse width 20ns. Overshoot undershoot sampled, 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested.
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Average operating current Symbol ICC1 ICC2 Output voltage Output high voltage Standby Current(CMOS) ISB1 VIN=Vss CS1=VIH, CS2=VIL OE=VIH WE=VIL, VIO=Vss Cycle time=1µs, 100%duty, IIO=0mA, CS10.2V, CS2Vcc-0.2V, VIN0.2V VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL 0.1mA -0.1mA Other input =0~Vcc CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) 0VCS20.2V(CS2 controlled) Test Conditions Typ1) Unit
Typical values measured VCC=2.0V, TA=25°C 100% tested.
Revision September 2004
K6F8016R6D Family
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Input/Output Reference)
Input pulse level: Vcc-0.2V Input rising falling time: Input output reference voltage: 0.9V Output load(see right): CL=100pF+1TTL
Preliminary CMOS SRAM
VTM3) R12)
CL1)
R22)
Including scope capacitance R1=3070, R2=3150 V=1.8V
CHARACTERISTICS(Vcc=1.65~1.95V, Industrial product: TA=-40 85°C)
Speed Bins Parameter List Symbol Read Cycle Time Address Access Time Chip Select Output Output Enable Valid Output Access Time Read Chip Select Low-Z Output Enable Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output Disable High-Z Output Output Disable High-Z Output Output Hold from Address Change Write Cycle Time Chip Select Write Address Set-up Time Address Valid Write Valid Write Write Write Pulse Width Write Recovery Time Write Output High-Z Data Write Time Overlap Data Hold from Write Time Write Output Low-Z tBLZ tOLZ tBHZ tOHZ tWHZ 70ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CS1Vcc-0.2V
Typ2)
1.95
Unit
Vcc=1.2V, CS1Vcc-0.2V
data retention waveform
CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) 0CS20.2V(CS2 controlled) Typical value measured TA=25°C 100% tested.
Revision September 2004
K6F8016R6D Family
TIMING DIAGRAMS
Preliminary CMOS SRAM
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, or/and LB=VIL)
Address Data Previous Data Valid Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address
tBHZ tOLZ tBLZ Data
High-Z
tOHZ Data Valid
NOTES (READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision September 2004
K6F8016R6D Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tWR(4)
Preliminary CMOS SRAM
tWP(1) tAS(3) Data High-Z tWHZ Data Data Undefined Data Valid High-Z
TIMING WAVEFORM WRITE CYCLE(2) (CS1 Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision September 2004
K6F8016R6D Family
TIMING WAVEFORM WRITE CYCLE(3) (UB, Controlled)
Address tCW(2) tAS(3) tWP(1) Data Data Valid tWR(4)
Preliminary CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap(tWP) write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends with going high.
DATA RETENTION WAVE FORM
controlled
1.65V tSDR Data Retention Mode tRDR
1.4V CS1VCC 0.2V
controlled
1.65V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision September 2004
K6F8016R6D Family
PACKAGE DIMENSION
BALL FINE PITCH BGA(0.75mm ball pitch)
View Bottom View
Preliminary CMOS SRAM
Unit: millimeters
Detail Notes. Bump counts: 48(8 column) Bump pitch: (x,y)=(0.75 0.75)(typ.) tolerence ±0.050 unless specified beside figure. Typ: Typical coplanarity: 0.10(Max)
Side View
5.90 6.90 0.40 0.27 0.75 6.00 3.75 7.00 5.25 0.45 6.10 7.10 0.50 1.00 0.10
Revision September 2004

Preliminary CMOS SRAM 512K Super Power Voltage Full CMOS Static

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