8-Bit Serial-In, Parallel-Out Shift Wide Operating Voltage Range High-
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SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
8-Bit Serial-In, Parallel-Out Shift Wide Operating Voltage Range High-Current 3-State Outputs Drive
LSTTL Loads Power Consumption, 80-µA Typical ±6-mA Output Drive Input Current Shift Register Direct Clear
SN54HC595 PACKAGE SN74HC595 PACKAGE (TOP VIEW)
RCLK SRCLK SRCLR
description/ordering information
'HC595 devices contain 8-bit serial-in, parallel-out shift register that feeds 8-bit D-type storage register. storage register parallel 3-state outputs. Separate clocks provided both shift storage register. shift register direct overriding clear (SRCLR) input, serial (SER) input, serial outputs cascading. When output-enable (OE) input high, outputs high-impedance state. Both shift register clock (SRCLK) storage register clock (RCLK) positive-edge triggered. both clocks connected together, shift register always clock pulse ahead storage register. ORDERING INFORMATION
PDIP PACKAGE Tube Tube SOIC -40°C 85°C SOIC SSOP CDIP 125°C -55°C LCCC Reel 2500 Reel Tube Reel 2000 Reel 2000 Reel 2000 Tube Tube Tube ORDERABLE PART NUMBER SN74HC595N SN74HC595D SN74HC595DR SN74HC595DT SN74HC595DW SN74HC595DWR SN74HC595NSR SN74HC595DBR SNJ54HC595J SNJ54HC595W SNJ54HC595FK HC595 HC595 HC595 SNJ54HC595J SNJ54HC595W HC595 TOP-SIDE MARKING SN74HC595N SN54HC595 PACKAGE (TOP VIEW)
RCLK SRCLK
internal connection
SNJ54HC595FK Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
products compliant 38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
Copyright 2004, Texas Instruments Incorporated
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SRCLR
SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
FUNCTION TABLE INPUTS SRCLK SRCLR RCLK FUNCTION Outputs QA-QH disabled. Outputs QA-QH enabled. Shift register cleared. First stage shift register goes low. Other stages store data previous stage, respectively. First stage shift register goes high. Other stages store data previous stage, respectively. Shift-register data stored storage register.
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SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
logic diagram (positive logic)
RCLK SRCLR SRCLK
numbers shown packages.
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SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
timing diagram
SRCLK
RCLK
SRCLR
NOTE:
implies that output 3-State mode.
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SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input clamp current, VCC) (see Note Output clamp current, VCC) (see Note Continuous output current, VCC) Continuous current through Package thermal impedance, (see Note package 73°C/W package 82°C/W package 57°C/W package 67°C/W package 64°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD 51-7.
recommended operating conditions (see Note
SN54HC595 Supply voltage Low-level input voltage Input voltage Output voltage 3.15 1.35 1000 SN74HC595 3.15 1.35 1000 UNIT
High-level input voltage
Input transition rise/fall time
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004. this device used threshold region (from VILmax VIHmin there potential into wrong state from induced grounding, causing double clocking. Operating with inputs 1000 does damage device; however, functionally, inputs ensured while shift, count, toggle operating modes.
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SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS QA-QH, -5.2 QA-QH, -7.8 QA-QH, QA-QH, QA-QH 3.98 3.98 5.48 5.48 25°C 1.998 4.499 5.999 0.002 0.001 0.001 0.17 0.17 0.15 0.15 ±0.1 ±0.01 0.26 0.26 0.26 0.26 ±100 ±0.5 SN54HC595 ±1000 SN74HC595 3.84 3.84 5.34 5.34 0.33 0.33 0.33 0.33 ±1000 UNIT
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SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
fclock Clock frequency SRCLK RCLK high Pulse duration SRCLR before SRCLK SRCLK before RCLK Setup time SRCLR before RCLK SRCLR high (inactive) before SRCLK Hold time, after SRCLK SRCLK 25°C SN54HC595 SN74HC595 UNIT
This setup time allows storage register receive stable data from shift register. clocks tied together, which case shift register clock pulse ahead storage register.
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SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) fmax SRCLK RCLK QA-QH tPHL SRCLR QA-QH tdis QA-QH QA-QH 25°C SN54HC595 SN74HC595 UNIT
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) RCLK QA-QH QA-QH QA-QH 25°C SN54HC595 SN74HC595 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS load UNIT
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SN54HC595, SN74HC595 SHIFT REGISTERS WITH STATE OUTPUT REGISTERS
PARAMETER MEASUREMENT INFORMATION
PARAMETER tPZH tPZL tPHZ tPLZ Open Closed Open Closed Open Closed Open Closed Open Open
From Output Under Test (see Note
Test Point
tdis
LOAD CIRCUIT
High-Level Pulse
VOLTAGE WAVEFORMS PULSE DURATIONS
Reference Input Data Input
Low-Level Pulse
VOLTAGE WAVEFORMS SETUP HOLD INPUT RISE FALL TIMES
Input tPLH In-Phase Output tPHL Out-ofPhase Output tPLH tPHL
Output Control (Low-Level Enabling) tPZL Output Waveform (See Note tPZH Output Waveform (See Note
tPLZ tPHZ
VOLTAGE WAVEFORMS PROPAGATION DELAY OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES 3-STATE OUTPUTS
NOTES: includes probe test-fixture capacitance. Waveform output with internal conditions such that output low, except when disabled output control. Waveform output with internal conditions such that output high, except when disabled output control. Phase relationships between waveforms were chosen arbitrarily. input pulses supplied generators having following characteristics: MHz, clock inputs, fmax measured when input duty cycle 50%. outputs measured time, with input transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
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PACKAGE OPTION ADDENDUM
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28-Feb-2005
PACKAGING INFORMATION
Orderable Device 5962-86816012A 5962-8681601EA 5962-8681601VEA 5962-8681601VFA SN54HC595J SN74HC595D SN74HC595DBR SN74HC595DR SN74HC595DT SN74HC595DW SN74HC595DWR SN74HC595N SN74HC595NSR SNJ54HC595FK SNJ54HC595J SNJ54HC595W
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE
Package Type LCCC CDIP CDIP CDIP SOIC SSOP SOIC SOIC SOIC SOIC PDIP LCCC CDIP
Package Drawing
Pins Package Plan 2000 None None None None None Pb-Free (RoHS) Pb-Free (RoHS)
Lead/Ball Finish Call Call Call Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Call Call Call
Peak Temp Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-2-250C-1 YEAR Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-1-260C-UNLIM Level-2-250C-1 YEAR Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-NC-NC-NC Call
2500 Green (RoHS Sb/Br) 2000 2000 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) None None None
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight.
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDECindustry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release.
Addendum-Page
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MLCC006B OCTOBER 1996
(S-CQCC-N**)
TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
TERMINALS
0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 10/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with metal lid. terminals gold plated. Falls within JEDEC MS-004
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MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0,65 0,38 0,22 0,15
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 0,25 0,95 0,55
Seating Plane 2,00 0,05 0,10
PINS
6,50
6,50
7,50
8,50
10,50
10,50
12,90
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 12/01
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-150
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