Single-chip 16/32-bit microcontrollers; 128/256 ISP/IAP Flash with 10-
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LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers; 128/256 ISP/IAP Flash with 10-bit
Rev. December 2004 Product data
LPC2114/LPC2124 based 16/32 ARM7TDMI-SCPU with real-time emulation embedded trace support, together with 128/256 kilobytes (kB) embedded high speed flash memory. 128-bit wide memory interface unique accelerator architecture enable 32-bit code execution maximum clock rate. critical code size applications, alternative 16-bit ThumbMode reduces code more than with minimal performance penalty. With their compact package, power consumption, various 32-bit timers, 4-channel 10-bit ADC, channels GPIO lines with external interrupt pins these microcontrollers particularly suitable industrial control, medical systems, access control point-of-sale. With wide range serial communications interfaces, they also very well suited communication gateways, protocol converters embedded soft modems well many other general-purpose applications.
Features
features
16/32-bit ARM7TDMI-S microcontroller tiny LQFP64 package. on-chip Static RAM. 128/256 on-chip Flash Program Memory. 128-bit wide interface/accelerator enables high speed operation. In-System Programming (ISP) In-Application Programming (IAP) on-chip boot-loader software. Flash programming takes byte line. Single sector full chip erase takes EmbeddedICE-RT interface enables breakpoints watch points. Interrupt service routines continue execute whilst foreground task debugged with on-chip RealMonitorsoftware. Embedded Trace Macrocellenables non-intrusive high speed real-time tracing instruction execution. Four channel 10-bit converter with conversion time 2.44 32-bit timers (with capture compare channels), unit outputs), Real Time Clock Watchdog. Multiple serial interfaces including UARTs (16C550), Fast (400 kbits/s) SPIsTM. maximum clock available from programmable on-chip Phase-Locked Loop with settling time Vectored Interrupt Controller with configurable priorities vector addresses.
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
forty-six tolerant general purpose pins. nine edge level sensitive external interrupt pins available. On-chip crystal oscillator with operating range MHz. power modes, Idle Power-down. Processor wake-up from Power-down mode external interrupt. Individual enable/disable peripheral functions power optimization. Dual power supply: operating voltage range 1.65 1.95 (1.8 ±0.15 power supply range (3.3 with tolerant pads.16/32-bit ARM7TDMI-S processor.
Ordering information
Table Ordering information Package Name LPC2114FBD64 LPC2124FBD64 LQFP64 LQFP64 Description Version plastic profile quad flat package; leads; SOT314-2 body plastic profile quad flat package; leads; SOT314-2 body Type number
Ordering options
Table Part options Flash memory Temperature range (°C) Type number LPC2114FBD64 LPC2124FBD64
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Block diagram
TRST(1) TMS(1) TCK(1) TDI(1) TDO(1)
RTCK
XTAL1
XTAL2 V1.8 SCL* SDA* SCK* MOSI* MISO* SSEL*
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
system clock
SYSTEM FUNCTIONS
ARM7TDMI-S
BRIDGE ARM7 LOCAL
VECTORED INTERRUPT CONTROLLER
AMBA (Advanced High-performance Bus)
INTERNAL SRAM CONTROLLER
INTERNAL FLASH CONTROLLER BRIDGE DIVIDER
DECODER
SRAM
128/256 FLASH
EINT0* EINT1* EINT2* EINT3* EXTERNAL INTERRUPTS
SERIAL INTERFACE
CAP* MAT*
CAPTURE/ COMPARE TIMER0/TIMER1
SERIAL INTERFACE
TxD0,1* PWM1.6* PWM0 RxD0,1* UART0/UART1
MODEM CONTROL PINS)*
PINS) P1.31:16 GENERAL PURPOSE REAL TIME CLOCK
Ain3:0*
10-BIT CONVERTER
WATCHDOG TIMER
SYSTEM CONTROL
*Shared with GPIO
002aaa659
When test/debug interface used, GPIO/other functions sharing these pins available.
Block diagram.
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Pinning information
Pinning
P0.19/MAT1.2/MOSI1/CAP1.2 P0.18/CAP1.3/MISO1/MAT1.3 P0.20/MAT1.3/SSEL1/EINT3
VSSA_PLL
P1.30/TMS
P1.29/TCK
P1.27/TD0
P1.28/TDI
RESET
XTAL1
XTAL2
VSSA
V18A
handbook, full pagewidth
P0.21/PWM5/CAP1.3 P0.22/CAP0.0/MAT0.0 P0.23 P1.19/TRACEPKT3 P0.24 P1.18/TRACEPKT2
P1.20/TRACESYNC P0.17/CAP1.2/SCK1/MAT1.2 P0.16/EINT0/MAT0.2/CAP0.2 P0.15/RI1/EINT2 P1.21/PIPESTAT0 P0.14/DCD1/EINT1
LPC2114/LPC2124
P0.25 P0.27/AIN0/CAP0.1/MAT0.1 P1.17/TRACEPKT1 P0.28/AIN1/CAP0.2/MAT0.2 P0.29/AIN2/CAP0.3/MAT0.3 P0.30/AIN3/EINT3/CAP0.0 P1.16/TRACEPKT0
P0.0/TxD0/PWM1 P1.31/TRST P0.1/RxD0/PWM3/EINT0 P0.2/SCL/CAP0.0 P1.26/RTCK P0.3/SDA/MAT0.0/EINT1 P0.4/SCK0/CAP0.1 P1.25/EXTIN0 P0.5/MISO0/MAT0.1 P0.6/MOSI0/CAP0.2 P0.7/SSEL0/PWM2/EINT2 P1.24/TRACECLK
P1.22/PIPESTAT1 P0.13/DTR1/MAT1.1 P0.12/DSR1/MAT1.0 P0.11/CTS1/CAP1.1 P1.23/PIPESTAT2 P0.10/RTS1/CAP1.0 P0.9/RxD1/PWM6/EINT3 P0.8/TxD1/PWM4
002aaa660
Pinning.
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
description
Table Symbol P0.0 P0.31 description Type Description Port Port 32-bit bi-directional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins port available. TxD0 Transmitter output UART0. PWM1 Pulse Width Modulator output RxD0 Receiver input UART0. PWM3 Pulse Width Modulator output EINT0 External interrupt input clock input/output. Open drain output (for compliance). CAP0.0 Capture input Timer channel data input/output. Open drain output (for compliance). MAT0.0 Match output Timer channel EINT1 External interrupt input. SCK0 Serial clock SPI0. clock output from master input slave. CAP0.1 Capture input Timer channel MISO0 Master Slave SPI0. Data input master data output from slave. MAT0.1 Match output Timer channel MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0.2 Capture input Timer channel SSEL0 Slave Select SPI0. Selects interface slave. PWM2 Pulse Width Modulator output EINT2 External interrupt input. TxD1 Transmitter output UART1. PWM4 Pulse Width Modulator output RxD1 Receiver input UART1. PWM6 Pulse Width Modulator output EINT3 External interrupt input. RTS1 Request Send output UART1. CAP1.0 Capture input Timer channel CTS1 Clear Send input UART1. CAP1.1 Capture input Timer channel DSR1 Data Ready input UART1. MAT1.0 Match output Timer channel
P0.0 P0.1
P0.2 P0.3
P0.4 P0.5
P0.6
P0.7
P0.8 P0.9
P0.10 P0.11 P0.12
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Table Symbol P0.13 P0.14
description.continued Type Description DTR1 Data Terminal Ready output UART1. MAT1.1 Match output Timer channel DCD1 Data Carrier Detect input UART1. EINT1 External interrupt input. Note: this while RESET forces on-chip boot-loader take control part after reset.
P0.15 P0.16
Ring Indicator input UART1. EINT2 External interrupt input. EINT0 External interrupt input. MAT0.2 Match output Timer channel CAP0.2 Capture input Timer channel CAP1.2 Capture input Timer channel SCK1 Serial Clock SPI1. clock output from master input slave. MAT1.2 Match output Timer channel CAP1.3 Capture input Timer channel MISO1 Master Slave SPI1. Data input master data output from slave. MAT1.3 Match output Timer channel MAT1.2 Match output Timer channel MOSI1 Master Slave SPI1. Data output from master data input slave. CAP1.2 Capture input Timer channel MAT1.3 Match output Timer channel SSEL1 Slave Select SPI1. Selects interface slave. EINT3 External interrupt input. PWM5 Pulse Width Modulator output CAP1.3 Capture input Timer channel CAP0.0 Capture input Timer channel MAT0.0 Match output Timer channel General purpose bidirectional digital port only. General purpose bidirectional digital port only. General purpose bidirectional digital port only. AIN0 converter, input This analog input always connected pin. CAP0.1 Capture input Timer channel MAT0.1 Match output Timer channel
P0.17
P0.18
P0.19
P0.20
P0.21 P0.22 P0.23 P0.24 P0.25 P0.27
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Table Symbol P0.28
description.continued Type Description AIN1 converter, input This analog input always connected pin. CAP0.2 Capture input Timer channel MAT0.2 Match output Timer channel AIN2 converter, input This analog input always connected pin. CAP0.3 Capture input Timer Channel MAT0.3 Match output Timer channel AIN3 converter, input This analog input always connected pin. EINT3 External interrupt input. CAP0.0 Capture input Timer channel Port Port 32-bit bi-directional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins through port available. TRACEPKT0 Trace Packet, Standard port with internal pull-up. TRACEPKT1 Trace Packet, Standard port with internal pull-up. TRACEPKT2 Trace Packet, Standard port with internal pull-up. TRACEPKT3 Trace Packet, Standard port with internal pull-up. TRACESYNC Trace Synchronization. Standard port with internal pull-up. Note: this while RESET LOW, enables pins P1.25:16 operate Trace port after reset.
P0.29
P0.30
P1.0 P1.31
P1.16 P1.17 P1.18 P1.19 P1.20
P1.21 P1.22 P1.23 P1.24 P1.25 P1.26
PIPESTAT0 Pipeline Status, Standard port with internal pull-up. PIPESTAT1 Pipeline Status, Standard port with internal pull-up. PIPESTAT2 Pipeline Status, Standard port with internal pull-up. TRACECLK Trace Clock. Standard port with internal pull-up. EXTIN0 External Trigger Input. Standard with internal pull-up. RTCK Returned Test Clock output. Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bi-directional with internal pull-up. Note: this while RESET LOW, enables pins P1.31:26 operate Debug port after reset.
P1.27 P1.28 P1.29 P1.30 P1.31 RESET
Test Data JTAG interface. Test Data JTAG interface. Test Clock JTAG interface. Test Mode Select JTAG interface. TRST Test Reset JTAG interface. connected. External Reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input oscillator circuit internal clock generator circuits.
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XTAL1
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Table Symbol XTAL2 VSSA VSSA_PLL V18A
description.continued Type Description Output from oscillator amplifier. Ground: reference. Analog Ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. Analog Ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. Core Power Supply: This power supply voltage internal circuitry. Analog Core Power Supply: This power supply voltage internal circuitry. This should nominally same voltage should isolated minimize noise error. Power Supply: This power supply voltage ports. Analog Power Supply: This should nominally same voltage should isolated minimize noise error.
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Functional description
Details LPC2114/LPC2124 systems peripheral functions described following sections.
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. ARM® architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit Thumb set.
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-Chip Flash program memory
LPC2114/LPC2124 incorporate Flash memory system respectively. This memory used both code data storage. Programming Flash memory accomplished several ways. programmed System serial port. application program also erase and/or program Flash while application running, allowing great degree flexibility data storage field firmware upgrades, etc. When on-chip bootloader used, 120/248 Flash memory available user code. LPC2114/LPC2124 Flash memory provides minimum 100,000 erase/write cycles years data retention. On-chip bootloader revision 1.60) provides Code Read Protection (CRP) LPC2114/LPC2124 on-chip Flash memory. When enabled, JTAG debug port commands accessing either on-chip Flash memory
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
disabled. However, Flash Erase command executed time matter whether off). Removal achieved erasure full on-chip user Flash. With off, full access chip JTAG and/or restored.
On-Chip static
On-Chip static used code and/or data storage. SRAM accessed 8-bits, 16-bits, 32-bits. LPC2114/LPC2124 provide static RAM.
Memory
LPC2114/LPC2124 memory maps incorporate several distinct regions, shown following figures. addition, interrupt vectors re-mapped allow them reside either Flash memory (the default) on-chip static RAM. This described Section 6.19 "System control".
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
RESERVED ADDRESS SPACE
0xC000 0000
BOOT BLOCK (RE-MAPPED FROM ON-CHIP FLASH MEMORY
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
RESERVED ADDRESS SPACE 0x4004 0000 0x4000 3FFF KBYTE ON-CHIP STATIC 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0004 0000 0x0003 FFFF KBYTE ON-CHIP FLASH MEMORY (LPC2124) KBYTE ON-CHIP FLASH MEMORY (LPC2114) 0x0002 0000 0x0001 FFFF 0x0000 0000
002aaa661
LPC2114/LPC2124 memory map.
Interrupt controller
Vectored Interrupt Controller (VIC) accepts interrupt request inputs categorizes them FIQ, vectored IRQ, non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. Fast Interrupt reQuest (FIQ) highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt.
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest. Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs requesting, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active. 6.5.1 Interrupt sources Table lists interrupt sources each peripheral function. Each peripheral device interrupt line connected Vectored Interrupt Controller, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
Table Block Core Core Timer Timer UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved software interrupts only Embedded ICE, DbgCommRx Embedded ICE, DbgCommTx Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Match (MR0, MR1, MR2, MR3) Capture (CR0, CR1, CR2, CR3) Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) UART1 Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) PWM0 SPI0 SPI1 Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) (state change) SPIF, MODF SPIF, MODF Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) channel
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Interrupt sources.continued Flag(s) External Interrupt (EINT1) External Interrupt (EINT2) External Interrupt (EINT3) channel
Table Block
System Control External Interrupt (EINT0)
Converter
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined. Control Module contains three registers shown Table
Table Address 0xE002C000 0xE002C004 0xE002C014 Name PINSEL0 PINSEL1 PINSEL2 Description function select register function select register function select register Access Read/Write Read/Write Read/Write
function select register (PINSEL0 0xE002C000)
PINSEL0 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions, direction controlled automatically. Settings other than those shown Table reserved, should used
Table PINSEL0 function select register (PINSEL0 0xE002C000) name P0.0 Value P0.1 P0.2 Function GPIO Port (UART0) PWM1 Reserved GPIO Port (UART0) PWM3 EINT0 GPIO Port (I2C) Capture (Timer Reserved Value after Reset
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
function select register (PINSEL0 0xE002C000).continued name P0.3 Value Function GPIO Port (I2C) Match (Timer EINT1 GPIO Port (SPI0) Capture (Timer Reserved GPIO Port MISO (SPI0) Match (Timer Reserved GPIO Port MOSI (SPI0) Capture (Timer Reserved GPIO Port SSEL (SPI0) PWM2 EINT2 GPIO Port UART1 PWM4 Reserved GPIO Port (UART1) PWM6 EINT3 GPIO Port 0.10 (UART1) Capture (Timer Reserved GPIO Port 0.11 (UART1) Capture (Timer Reserved GPIO Port 0.12 (UART1) Match (Timer Reserved Value after Reset
Table PINSEL0
P0.4
11:10
P0.5
13:12
P0.6
15:14
P0.7
17:16
P0.8
19:18
P0.9
21:20
P0.10
23:22
P0.11
25:24
P0.12
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
function select register (PINSEL0 0xE002C000).continued name P0.13 Value Function GPIO Port 0.13 (UART1) Match (Timer Reserved GPIO Port 0.14 (UART1) EINT1 Reserved GPIO Port 0.15 (UART1) EINT2 Reserved Value after Reset
Table PINSEL0 27:26
29:28
P0.14
31:30
P0.15
function select register (PINSEL1 0xE002C004)
PINSEL1 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Settings other than those shown table reserved, should used.
Table PINSEL1 function select register (PINSEL1 0xE002C004) Name P0.16 Value P0.17 P0.18 P0.19 P0.20
9397 13145
Function GPIO Port 0.16 EINT0 Match (Timer Capture (Timer GPIO Port 0.17 Capture (Timer (SPI1) Match (Timer GPIO Port 0.18 Capture (Timer MISO (SPI1) Match (Timer GPIO Port 0.19 Match (Timer MOSI (SPI1) Capture (Timer GPIO Port 0.20 Match (Timer SSEL (SPI1) EINT3
Value after Reset
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
function select register (PINSEL1 0xE002C004).continued Name P0.21 Value Function GPIO Port 0.21 PWM5 Reserved Capture (Timer GPIO Port 0.22 Reserved Capture (Timer Match (Timer GPIO Port 0.23 Reserved Reserved Reserved GPIO Port 0.24 Reserved Reserved Reserved GPIO Port 0.25 Reserved Reserved Reserved Reserved Reserved Reserved Reserved GPIO Port 0.27 AIN0 (A/D input Capture (Timer Match (Timer GPIO Port 0.28 AIN1 (A/D input Capture (Timer Match (Timer GPIO Port 0.29 AIN2 (A/D input Capture (Timer Match (Timer GPIO Port 0.30 AIN3 (A/D input EINT3 Capture (Timer
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Table PINSEL1 11:10
Value after Reset
13:12
P0.22
15:14
P0.23
17:16
P0.24
19:18
P0.25
21:20
P0.26
23:22
P0.27
25:24
P0.28
27:26
P0.29
29:28
P0.30
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
function select register (PINSEL1 0xE002C004).continued Name P0.31 Value Function Reserved Reserved Reserved Reserved Value after Reset
Table PINSEL1 31:30
function select register (PINSEL2 0xE002C014)
PINSEL2 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Settings other than those shown table reserved, should used.
Table 31:4 31:30 function select register (PINSEL2 0xE002C014) Description Reserved When pins P1.31:26 GPIO pins. When P1.31:26 used Debug port. Reset value
PINSEL2 bits
When pins P1.25:16 used GPIO pins. When P1.25:16 used Trace port. Reserved
6.10 General purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins. 6.10.1 Features
Direction control individual bits. Separate control output clear. default inputs after reset. 6.11 10-bit converter
LPC2114/LPC2124 each contain single 10-bit successive approximation analog digital converter with four multiplexed channels. 6.11.1 Features
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Measurement range Capable performing more than 400,000 10-bit samples second. Burst conversion mode single multiple inputs. Optional conversion transition input Timer Match signal.
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Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
6.12 UARTs
LPC2114/LPC2124 each contain UARTs. UART provides full modem control handshake interface, other provides only transmit receive data lines. 6.12.1 Features
byte Receive Transmit FIFOs. Register locations conform `550 industry standard. Receiver FIFO trigger points bytes Built-in baud rate generator. Standard modem interface signals included UART1.
6.13 serial controller
bi-directional inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g. driver transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. multi-master bus, controlled more than master connected implemented LPC2114/LPC2124 supports rate kbit/s (Fast I2C). 6.13.1 Features
Standard compliant interface. Easy configure Master, Slave, Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption
serial data bus.
Serial clock synchronization allows devices with different rates communicate
serial bus.
Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
used test diagnostic purposes. 6.14 serial controller
LPC2114/LPC2124 each contain SPIs. full duplex serial interface, designed able handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master.
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Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
6.14.1
Features
Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, Serial, Full Duplex, Communication. Combined master slave. Maximum data rate eighth input clock rate. 6.15 General purpose timers
Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them. 6.15.1 Features
32-bit Timer/Counter with programmable 32-bit Prescaler. Four 32-bit capture channels timer that take snapshot timer value
when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Four external outputs timer corresponding match registers, with following
capabilities: match. HIGH match. Toggle match. nothing match.
6.16 Watchdog timer
purpose Watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, Watchdog will generate system reset user program fails `feed' reload) Watchdog within predetermined amount time. 6.16.1 Features
Internally resets chip periodically reloaded. Debug mode.
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Product data
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Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Enabled software requires hardware reset Watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate Watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (tpclk (tpclk multiples
tpclk
6.17 Real time clock
Real Time Clock (RTC) designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode). 6.17.1 Features
Measures passage time maintain calendar clock. Ultra power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Programmable reference clock divider allows adjustment match
various crystal frequencies.
6.18 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2114/LPC2124. Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. function also based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs.
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge). 6.18.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs.
Single edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive
going negative going pulses.
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit Prescaler. 6.19 System control
6.19.1 Crystal oscillator oscillator supports crystals range MHz. oscillator output frequency called fosc processor clock frequency referred cclk purposes rate equations, etc. fosc cclk same value unless running connected. Refer Section 6.19.2 "PLL" additional information.
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
6.19.2
accepts input clock frequency range MHz. input frequency multiplied into range with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle.The turned bypassed following chip Reset enabled software. program must configure activate PLL, wait Lock, then connect clock source. settling time
6.19.3
Reset wake-up timer Reset sources LPC2114/LPC2124: RESET Watchdog Reset. RESET Schmitt trigger input with additional glitch filter. Assertion chip Reset source starts Wake-up Timer (see Wake-up Timer description below), causing internal chip reset remain asserted until external Reset de-asserted, oscillator running, fixed number clocks have passed, on-chip Flash controller completed initialization. When internal Reset removed, processor begins executing address which Reset vector. that point, processor peripheral registers have been initialized predetermined values. wake-up timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power types Reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes Wake-up Timer. Wake-up Timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
6.19.4
External interrupt inputs LPC2114/LPC2124 include nine edge level sensitive External Interrupt Inputs selectable functions. When pins combined, external events processed four independent interrupt signals. External Interrupt Inputs optionally used wake processor from Power-down mode.
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
6.19.5
Memory Mapping Control Memory Mapping Control alters mapping interrupt vectors that appear beginning address 0x00000000. Vectors mapped bottom on-chip Flash memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
6.19.6
Power Control LPC2114/LPC2124 support reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either Reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses. Power-down mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either Reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. Power Control Peripherals feature allows individual peripherals turned they needed application, resulting additional power savings.
6.19.7
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside bus), default condition reset processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
6.20 Emulation debugging
LPC2114/LPC2124 support emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs Port This means that communication, timer interface peripherals residing Port available during development debugging phase they when application embedded system itself.
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
6.20.1
Embedded ICEStandard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts Remote Debug Protocol commands JTAG data needed access core. core Debug Communication Channel function built-in. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed co-processor program running ARM7TDMI-S core. debug communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICE logic.
6.20.2
Embedded trace Since LPC2114/LPC2124 have significant amounts on-chip memory, possible determine processor core operating simply observing external pins. Embedded Trace Macrocell provides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external trace port analyzer must capture trace information under software debugger control. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code traced because this restriction.
6.20.3
RealMonitor RealMonitor configurable software module, developed Inc., which enables real time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using (Debug Communications Channel), which present EmbeddedICE logic. LPC2114/LPC2124 contain specific configuration RealMonitor software programmed into on-chip Flash memory.
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol AVIN Tstg Parameter Supply voltage, internal rail Supply voltage, external rail Analog supply voltage Analog input voltage related pins input voltage, tolerant pins input voltage, other pins supply current supply ground current ground Storage temperature Power dissipation (based package heat transfer, device power consumption)
[2][3] [4][2]
Conditions
-0.5 -0.5 -0.5 -0.5 -0.5 -0.5
+2.5 +3.6
Unit
following applies Limiting values: Stresses above those listed under Limiting values cause permanent damage device. This stress rating only functional operation device these conditions other than those described Section "Static characteristics" Section "Dynamic characteristics" this specification implied. This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Including voltage outputs 3-state mode. Only valid when supply voltage present. exceed peak current limited times corresponding maximum current. Dependent package type.
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Static characteristics
Table Static characteristics Tamb commercial, unless otherwise specified. Symbol Parameter Supply voltage External rail supply voltage Analog supply voltage level input current, pull-up High level input current, pull down 3-state output leakage, pull-up/down latch-up current Input voltage[2][3][4] Output voltage, output active High level input voltage level input voltage Hysteresis voltage High level output voltage[5] V[7] V[7] cclk MHz, Tamb code while(1){} executed from FLASH, active peripherals Power-down Mode pins Vhys
9397 13145
Conditions
1.65
Typ[1]
1.95
Unit
Standard Port pins, RESET, RTCK Ilatchup Vhys -(0.5 (1.5
level output voltage[5] High level output current[5] level output current[5] High level short circuit current[6] level short circuit current[6] Pull-down current Pull-up current (applies P1.16 P1.25) active mode
Tamb Tamb
VTOL
VTOL
VTOL
High level input voltage level input voltage Hysteresis voltage
VTOL from VTOL from VTOL from
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Table Static characteristics.continued Tamb commercial, unless otherwise specified. Symbol Ilkg Parameter level output voltage[5] Input leakage Conditions Oscillator pins input Voltages output Voltages On-chip Flash program memory endurance (write erase) data retention
100,000
Typ[1]
Unit
cycles years
Typical ratings guaranteed. values listed room temperature (+25 °C), nominal supply voltages. capacitance characterized tested. Including voltage outputs 3-state mode. supply voltages must present. 3-state outputs into 3-state mode when grounded. Accounts voltage drop supply lines. Only allowed short time period. Minimum condition maximum condition
Table converter electrical characteristics unless otherwise specified; Tamb unless otherwise specified; converter frequency MHz. Symbol AVIN
Parameter Analog input voltage Analog input capacitance Differential non-linearity[1][2][3] Integral non-linearity[1][4] Offset Gain error[1][5] error[1][6]
±0.5
Unit
Absolute error[1][7]
Conditions: VSSA
monotonic, there missing codes. differential non-linearity (DLe) difference between actual step width ideal step width. Figure integral no-linearity (ILe) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (OSe) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (Ge) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute voltage error (Ae) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
(LSBideal) offset error
VDDA VSSA 1024
002aaa668
Example actual transfer curve. ideal transfer curve. Differential non-linearity (DLe). Integral non-linearity (ILe). Center step actual transfer curve.
conversion characteristics.
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Dynamic characteristics
Table Characteristics Tamb commercial, industrial, V18, over specified ranges[1] Symbol External Clock fosc Oscillator frequency supplied external oscillator (signal generator) External clock frequency supplied external crystal oscillator External clock frequency on-chip used External clock frequency used initial code download tCHCX tCLCX tCLCH tCHCL Port Pins tRISE tFALL pins Output fall time from Cb[2] Port output rise time (except P0.2, P0.3) Port output fall time (except P0.2, P0.3) Oscillator clock period Clock HIGH time Clock time Clock rise time Clock fall time 1000 Parameter Conditions Typ[1] Unit
Parameters valid over operating temperature range unless otherwise specified. capacitance from
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Timing
0.45
tCHCX
tCHCL
tCLCX
tCLCH
002aaa416
External clock timing.
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Package outline
LQFP64: plastic profile quad flat package; leads; body SOT314-2
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 10.1 0.75 0.45 0.12 1.45 1.05 1.45 1.05
12.15 12.15 11.85 11.85
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT314-2 REFERENCES 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
SOT314-2 (LQFP64).
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Revision history
Table Date 20041222 Revision history CPCN Description Product data (9397 13145) Modifications:
20040202 20031118
Section "On-Chip Flash program memory" page updated text. Section 6.19.2 "PLL" page updated text. Section 6.19.7 "VPB bus" page updated text. Table "Limiting values" page updated storage temperature specs. Table "Static characteristics" page adjusted typical value; added On-chip Flash program memory specs
Preliminary data (9397 12805) Preliminary data (9397 12327)
9397 13145
Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Data sheet status
Level Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Relevant changes will communicated Customer Product/Process Change Notification (CPCN).
Product data
Production
Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet data sheets describing multiple type numbers, highest-level product status determines data sheet status.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
performance. When product full production (status `Production'), relevant changes will communicated Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes responsibility liability these products, conveys licence title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
Licenses
Purchase Philips components Purchase Philips components conveys license under Philips' patent components system provided system conforms specification defined Philips. This specification ordered using code 9398 40011.
Disclaimers
Life support These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes products including circuits, standard cells, and/or software described contained herein order improve design and/or
Trademarks
registered trademark ARM, Inc. ARM7TDMI-S trademark ARM, Inc. EmbeddedICE trademark ARM, Inc. Embedded Trace Macrocell trademark ARM, Inc. RealMonitor trademark ARM, Inc. trademark Motorola, Inc. Thumb trademark ARM, Inc.
Contact information
additional information, please visit sales office addresses, send e-mail
9397 13145
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Koninklijke Philips Electronics N.V. 2004. rights reserved.
Product data
Rev. December 2004
Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
Contents
6.5.1 6.10 6.10.1 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 6.18 6.18.1 6.19 6.19.1 6.19.2 6.19.3 6.19.4 6.19.5 6.19.6 6.19.7 General description Features features Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-Chip Flash program memory On-Chip static Memory map. Interrupt controller Interrupt sources. connect block function select register (PINSEL0 0xE002C000). function select register (PINSEL1 0xE002C004). function select register (PINSEL2 0xE002C014). General purpose parallel I/O. Features 10-bit converter Features UARTs Features serial controller Features serial controller. Features General purpose timers Features Watchdog timer. Features Real time clock Features Pulse width modulator Features System control Crystal oscillator Reset wake-up timer External interrupt inputs Memory Mapping Control Power Control 6.20 6.20.1 6.20.2 6.20.3 Emulation debugging. Embedded ICE. Embedded trace. RealMonitor Limiting values Static characteristics Dynamic characteristics Timing Package outline Revision history Data sheet status. Definitions Disclaimers Licenses Trademarks
Koninklijke Philips Electronics N.V. 2004. Printed U.S.A.
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights. Date release: December 2004 Document order number: 9397 13145
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