Power Asynchronous Stereo Audio Codec with Integrated Power Amplifiers
|
|
|
Top Searches for this datasheet
STw5095
Power Asynchronous Stereo Audio Codec with Integrated Power Amplifiers
audio resolution, 8kHz 96kHz independent rate Asynchronous sampling DAC: they require oversampled clock information audio data sampling frequency (fs). Jitter tolerant Wide master clock range: from 4MHz 32MHz I2C/SPI compatible control Stereo headphones drivers, handsfree loudspeaker driver, line drivers Mixable analog line inputs Voice filters: 8/16kHz with voice channel filters Automatic gain control microphone linein inputs programmable master/slave serial audio data interfaces (I2S, SPI, compatible other formats) Frequency programmable clock outputs Multibit modulators with data weighted averaging functions bass-treble-volume control, mute, mono/stereo selection, voice channel filters, de-emphasis filter dynamic compression. dynamic range ADC, 0.001% with full scale output 2.7V dynamic range DAC, 0.02% performance 2.7V over load
STw5095
TFBGA64 pins)
Selectable stereo differential single-ended line inputs with range programmable gain
Analog output drivers
Stereo headphones outputs driving capability: (0.1% THD) over with range programmable gain Common mode voltage headphones driver (phantom ground) Balanced loudspeaker output driving capability: 500mW (VCCLS>3.5V; THD) over with 30dB range programmable gain Transient supression filter during power power down Balanced/unbalanced stereo line outputs driving capability
Applications
Analog inputs
Selectable stereo differential single-ended microphone amplifier inputs with 51dB range programmable gain microphone biasing output Microphone plug-in push-button detection input
Digital cellular telephones with player, stereo recorder, radio stereo listening recording functions, live music recording Portable digital players recorders
November 2005
This preliminary information product development undergoing evaluation. Details subject change without notice.
1/69
www.st.com
STw5095
Description
STw5095 power asynchronous stereo audio CODEC device with headphones amplifiers high quality audio listening recording. STw5095 control registers accessed through selectable I2C-bus compatible compatible interface. STw5095 asynchronous stereo audio CODEC designed easily most audio systems because supports extended master clock range (any value between MHz) same time supports audio data rate (independent paths) from from kHz, moreover tolerate jitter audio data without degrading performance. audio data serial interfaces (for Master Slave, compatible they support other formats that easily interface standard serial ports. audio interfaces used single bidirectional interface. frequency programmable clock sources available generate master clock audio sub-system other devices. internal converters work with resolution.
supply voltage same whole device, range differentiated digital (VCC: analog (VCCA: loudspeaker driver (VCCLS: VCCA obtain best performance maximum power loudspeaker mW). STw5095 multiple analog mixable inputs outputs. directly drive Stereo Headphones without external capacitors Loudspeaker driver that also used monophonic group listening. Stereo differential single ended microphones, auxiliary line stereo mono signals mixed connected directly drivers, mixed also with audio signals. STw5095 stereo audio Codec main applications include multimedia handheld devices such cellular phones with added low-power highquality and/ radio listening/recording features, battery powered equipment such PDAs, Camcorders, etc. that require Stereo Audio Codec with Headphones drivers.
Ordering codes
Part Number STw5095 STw5095T Details TFBGA Tray TFBGA Tape Reel
configuration (top view)
SCLK AD_OCK DA_OCK AD_CK AMCK AD_SYNC DA_DATA
HDET VCCA SDA/SDIN DA_CK AD_DATA DA_SYNC
AUX1L MICLN VCCA CMOD AS/CSB MBIAS
CAPMIC MICLP AUX3L GNDA VCCIO VCCA MICRN AUX1R
AUX2LN AUX2LP LINEINL CAPLS AUX3R GNDA CAPLINEIN MICRP
GNDCM VCMHPS LSPS LSNS LINEINR AUX2RP AUX2RN
GNDP VCMHP VCCP GNDP
VCCP VCCLS GNDP GNDP VCCLS
2/69
STw5095
Contents
Functional Block Diagram Description Functional Description
3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 Power supply Device programming Power Master clock Data rates Clock generators master mode function Audio digital interfaces Analog inputs Analog output drivers Analog mixer path path Analog-only operation Automatic Gain Control (AGC) Interrupt request: Headset plug-in push-button detection Microphone biasing circuit
Control Registers
Summary Supply power control
Gains control Analog functions Digital audio interfaces master mode clock generators Digital audio interfaces Digital filters, software reset master clock control
3/69
STw5095 4.10 Interrupt control control interface mode
Control Interface Master Clock
Control interface mode Control interface mode Master clock timing
Audio Interfaces Timing Specifications Operative Ranges
Absolute maximum ratings Operative supply voltage Power Dissipation Typical power dissipation
Electrical Characteristics
Digital interfaces AMCK with sinusoidal input Analog interfaces Headset plug-in push-button detector Microphone bias Power supply rejection ratio gain limiter
Analog Input/output Operative Ranges
10.1 10.2 10.3 10.4 10.5 10.6 Analog levels Microphone input levels Line input levels Line output levels Power output levels Power output levels
4/69
STw5095
Stereo Audio Specifications Stereo Audio Specifications Mixing (Sidetone) Specifications Stereo Analog-only Path Specifications (TX) (RX) Specifications With Voice Filters Selected Typical Performance Plots Application Schematics Package Outline Revision history
5/69
LINEINR Sample Rate Converter
LINEINL
Stereo Sing.E.
AUX1 AUX2 AUX3 MUTE ADLIN PreAmps
ADMIC
HPLG DA_SYNC
MIXMIC
MIXLIN
6/69
VCCA GNDA VCCP VCCLS GNDP GNDCM VCCIO (from DSP) LINLG LINRG -20:+18 Step Stereo Path Headset Detection HDET Amps
Note:
Figure
MICLP
MICLN
LINSEL
MICRP
Stereo Diff.
MICRN
AUX1L
Functional Block Diagram
AUX1R
Stereo Sing.E.
LINEIN AUX1 AUX2 AUX3 MUTE
STw5095
(from DSP) Power-On Reset Registers Control Logic Control
AUX2PL
SDA/SDIN SCLK AS/CSB CMOD
AUX2NL
AUX2PR MICLG MICRG 0÷39 Step MICLA MICRA -12÷0 Step
Stereo Diff.
MICSEL
AUX2NR
AUX3L
STw5095 block diagram
AUX3R
Stereo Sing.E.
Stereo
AD_DATA
CAPMIC
CAPLINEIN ADRTOL
Comm. Mode
ADMONO Digital AD-PLL Filter Audio/Voice
Audio AD-I/F
AD_CK AD_SYNC
AD_SYNC
MBIAS Digital Gain
Mic. Bias
2.1V Reference
(Mic&Lin)
Gen/ Master Mode
AD_OCK
Functional Block Diagram
LOG: -18:0 Step Oscillator
Bandgap
Left LineOut
MICLO
Mixing Gain
(Audio Only)
AMCK
CurrentBias
Right LineOut
Mixing Gain (sidetone)
Bass Treble
(Audio only)
DA_OCK Filter Audio/Voice Digital Gain Dyn.Comp. Gen/ Master Mode
Left Driver
-40:0 Step Transient Suppr. Filter Digital DA-PLL
VCMHP Analog Filter MIXDAC
Driver
Voltage Reference Modulator
DAMONO Audio DA-I/F
DA_SYNC DA_CK DA_DATA Sample Rate Converter
VCMHPS
-40:0 Step
Right Driver
Transient Suppr. Filter
HPRG
LSPS LSSEL (L+R)/2
-24:6 Step
Stereo
CAPLS
Mono Driver
Transient Suppr. Filter
This diagram shows functionality device some control registers bits does necessarily reflect exact hardware implementation.
STw5095
LSNS
STw5095
Description
Table
Description
description
Name MICLP MICLN MICRP MICRN MBIAS CAPMIC AUX1L AUX1R AUX2LP AUX2LN AUX2RP AUX2RN AUX3L AUX3R LINEINL LINEINR CAPLINEIN LSP, Type Description
Left Right channel differential pins microphone input.
Microphone Biasing Pin. Fixed voltage reference. capacitor must connected between CAPMIC Ground. Left Right channel single ended pins microphone line input.
Left Right channel differential pins microphone line input.
Left Right channel single ended pins microphone line input. Left Right channel single ended pins line input. capacitor must connected between CAPLINEIN Ground. Analog differential loudspeaker amplifier output Left channel Right channel both. This output drive 50nF (with series resistor) directly earpiece transductor deliver 500mW. LSPS, LSNS (sense) pins must connected application board LSP, pins respectively (see application note). connection must close possible pins. capacitor connected between this node Ground. application notes Audio single ended headphones amplifier outputs Left Right channels. outputs drive 50nF (with series resistor) directly earpiece transductor Common mode voltage headphones output. negative pins headphones left right speakers connected this avoid decoupling capacitors. VCMHPS (sense) must connected application board VCMHP (see application note). connection must close possible pins. Audio differential line amplifier Left Right channels. This outputs drive resistive load. used single ended outputs.
LSPS, LSNS CAPLS
VCMHP
VCMHPS
7/69
Description
STw5095
Table
description
Name CMOD SCLK SDA/SDIN Type DIOD Description Control interface type selector: I2C-bus mode mode. Control interface serial clock input. Control interface serial data input-output mode (SDA), Control interface serial data input mode (SDIN). Control interface address select mode (AS). Interface enable signal mode (CSB). Frame Sync stereo converter. Frame Sync stereo converter. Serial Data Clock stereo converter. Serial Data Clock stereo converter. Serial Data stereo converter. Serial Data stereo converter. Headset detection input (Microphone Plug-in Push-Button detection). Programmable Interrupt output. Active signal. Oversampled Clock from clock generator. Oversampled Clock from clock generator. Master Clock Input. Accepted range MHz. AMCK Digital square wave AMCK Analog sinewave (see AMCKSIN Section page Power Supply pins analog section. Standard Operating range: from Voltage (LV) Range: from Ground pins analog section. Ground analog reference. GNDCM connected GNDA. Power Supply pins left right output drivers (headphones line-out). Operating range: from VCCA 3.3V Power Supply pins mono differential output driver. Operating range: from VCCA 5.5V Ground pins left, right mono-differential output drivers. GNDP GNDA must connected together. Power Supply pins digital section. Operating range: from 1.71
AS/CSB AD_SYNC DA_SYNC AD_CK DA_CK AD_DATA DA_DATA HDET AD_OCK DA_OCK AMCK
VCCA
GNDA GNDCM
VCCP
VCCLS
GNDP
8/69
STw5095
Table
Description
description
Name Type Description Ground pins digital section. Power Supply Digital buffers. Operating ranges: from from 1.71
VCCIO
Note:
VCC, VCCA, VCCP, VCCLS connected together cost applications: Operating range: V-2.7
Type definitions
DIOD Analog input Analog Output Analog Input Output Digital Input Digital output Digital Input Output Digital Input Output Open Drain Power Supply Ground
9/69
Functional Description
STw5095
Functional Description
Power supply
STw5095 have different supply voltages different blocks, optimize performance, power consumption connectivity. Operative supply voltage page voltage definition. correct sequence apply supply voltage first (and unset last) digital supply (VCCIO). other supply voltages order disconnected individually, needed. Disconnection does cause harm device extra current pulled from supply during this operation. Moreover voltage conflict detected, like VCCA (not allowed), simply blocks connected VCCA power down extra current pulled from supply. When VCCIO (digital supply) set, digital output pins high impedance state, while digital inputs disconnected avoid power consumption input voltage value between VCCIO. Before disconnected device reset (SWRES CR30). When analog supply (VCCA) set, analog inputs high impedance state. control registers powered (digital supply) this disconnected information stored control registers lost. When digital supply voltage set, power-on-reset (POR) circuit sets registers content default value then generates signal writing bits PORMSK POREV CR31 CR32 respectively. supplies must during operation.
Device programming
STw5095 programmed writing Control Registers with compatible control interface (both slave). interface always active, there need have master clock running program device registers. choice between interfaces done input (CMOD): CMOD connected GND: compatible mode selected device address selected with pin:
connected GND: chip address 00110101(35hex) reading, 00110100 (34hex) writing connected VCCIO: chip address 00110111(37hex) reading, 00110110 (36hex) writing
When this mode selected control registers accessed through pins: SCLK (clock) (serial data out/in, open drain) CMOD connected VCCIO: compatible mode selected When this mode selected control registers accessed through: (chip select, active low) SCLK (clock) SDIN (serial data AD_OCK DA_OCK (serial data out, selected)
10/69
STw5095
Functional Description
Device Programming: I2C. Control Interface timing shown Section page interface internal counter that keeps current address control register read written. each write access interface address counter loaded with data register address field. value address counter increased after each data byte read write. possible access interface modes: single-byte mode which address data single register specified, multi-byte mode which address first register written read specified following bytes exchanged data successive registers starting from specified multi-byte mode internal address counter restart from register after last register 36). Using multi-byte mode possible write read registers with single access device bus. Device Programming: SPI. Control Interface timing shown Section page Bits SPIOSEL (SPI Output Select) CR33 control selection serial data (none, AD_OCK, DA_OCK IRQ), while SPIOHIZ=1 CR33 selects high impedance state serial data when idle. first sent SDIN, after falling edge, sets interface writing (SDIN=1) reading (SDIN=0), then 7-bit Control Register address follows. interface writing then last bits SDIN written control register. interface reading then after address STw5095 sends bits data selected with bits SPIOSEL CR33, while bits present SDIN ignored. SPIOSEL=00 selected) reading access interface still useful clear event bits CR32.
11/69
Functional Description
STw5095
Power
STw5095 internal blocks individually switched according user needs. general Power present CR0. following drawing select needed block desired function. fast-settling function activated quickly charge external capacitors when device switched (CAPLS, CAPLINEIN CAPMIC). Figure Power block diagram
ENANA ENMICL ENHSD MBIAS
POWERUP
ENMICR
ENADCL
STw5095
ENLINL
ENADCR
ENADCKGEN
ENLINR ADMAST ENADOCK
ENLOL
AUDIO
DAMAST ENHPL ENMIXL
ENDAOCK
ENLS ENMIXL
ENDACL
ENDACKGEN
ENHPR
ENDACR
ENPLL
ENLOR ENOSC=0 ENAMCK
ENOSC=1 ENHPVCM
ENOSC
Master clock
master clock (AMCK) accepts frequency from MHz. 4-32 range divided sub-ranges that have programmed bits CKRANGE CR30. jitter spectral properties this clock have direct impact performance because used directly integer division drive continuous-time sampled-time interfaces. Note that AMCK clock need have relation other digital analog input output.
12/69
STw5095
Functional Description
AMCK either squarewave sinewave, AMCKSIN CR30 selects proper input mode. When sinewave used input, AMCK must decoupled with capacitor. Specification sinusoidal input found Section 9.2: AMCK with sinusoidal input page AMCK clock needed when only analog functions used. this purpose internal oscillator with external components used operate device (see Analog-only operation page 17).
Data rates
STw5095 supports data rate ranges: kHz. range selected with bits DA96K AD96K CR29 paths respectively.
Note:
When AD96K=1 required have DA96K=1.
rates fully independent paths. Moreover rates have specified device they change fly, within range, while data flowing. audio data interfaces (for D/A) independently operate master slave mode.
Clock generators master mode function
STw5095 provides internal clock generators that drive, needed, audio interfaces (master mode), and/or independent master clocks. AMCK clock input frequency internally raised obtain clock (MCK) range MHz. ratio MCK/AMCK defined CR30 (see MCKCOEFF Section page 32). used obtain, fractional division, oversampled clock (OCK), word clock (SYNC) clock (CK), that will therefore have edges aligned with (the period have jitter period). frequency OCK, SYNC with DAOCKF CR21/20 interface, ADOCKF CR24/23 interface. ratio between SYNC clocks selected with DAOCK512 CR22 interface ADOCK512 CR25 interface. ratio between SYNC clocks depends selected interface format (see Audio digital interfaces paragraph below). Note that format only slave. ADOCK DAOCK output clocks activated bits ENADOCK ENDAOCK respectively, while master mode generation activated with bits: first ADMAST (DAMAST) sets ADSYNC ADCK (DASYNC DACK) pins outputs, then ADMASTGEN (DAMASTGEN) generates SYNC clocks. logical value SYNC pins before data generation depends interface selected format. description CR20 CR25 further details.
13/69
Functional Description
STw5095
Audio digital interfaces
separate audio data interfaces provided paths have maximum flexibility communicating with other devices. interfaces have different rates work different formats modes (i.e interface slave while 44.1 master). pins used interfaces are: AD_SYNC, AD_CK AD_DATA path word clock, clock data, respectively, DA_SYNC, DA_CK DA_DATA path word clock, clock data, respectively. Data exchanged with first left channel data first formats. Data word-length selected with bits DAWL CR26 ADWL CR27. AD_DATA pin, outside selected time slot, impedance condition selected ADHIZ CR28 data formats except Right-Aligned-Format. following paragraphs SYNC, DATA will used when distinction between relevant. When Master Mode selected (bits DAMAST ADMAST CR22 CR25 respectively) SYNC clocks generated internally. addition, oversampled clock generated each interface (AD_OCK DA_OCK). clock available Slave Mode also, needed. interfaces also used single bidirectional interface when they configured with same format (Delayed, DSP, etc.) AD_SYNC connected DA_SYNC DA_CK AD_CK. Master Mode still available selecting ADMAST DAMAST (not both). interfaces features controlled with control registers CR26, CR27 CR28. Supported operating formats:
Delayed-Format (I2S compatible) (DAFORM ADFORM =000): Audio Interface compatible (Figure page 45). number periods within SYNC period relevant, long enough periods used transfer data maximum frequency limit specified clock exceeded. either continuous clock sequence bursts. master mode there periods SYNC period (that means periods channel) when word length bit, while there periods SYNC period periods channel) when word length 18bit higher. Bits ADSYNCP, DASYNCP ADCKP, DACKP affect interface format inverting polarity SYNC pins respectively. Left-Aligned-Format (DAFORM ADFORM =001): this format equivalent Delayed-Format without clock delay beginning each frame (Figure page 45). Right-Aligned-Format (DAFORM ADFORM =010): this format equivalent Delayed-Format, except that Audio Data right aligned that number periods fixed each SYNC period (Figure page 45). DSP-Format (DAFORM ADFORM =011) this format Audio Interface starting from frame sync pulse SYNC receives (DA) sends (AD) Left Right data after other (Figure page 46). number periods within SYNC period relevant, long enough periods used transfer data maximum frequency limit specified clock exceeded. either continuous clock sequence bursts. Master Mode there periods SYNC period when word length bit, while there periods SYNC period when word length 18bit higher. (ADCKP DACKP) affects interface format inverting polarity pin. SYNCP (ADSYNCP DASYNCP) switches between
14/69
STw5095
delayed (SYNCP=0) delayed (SYNCP=1) formats. DSP-Format suited interface with Multi-Channel Serial Port.
Functional Description
SPI-Format (DAFORM ADFORM =100) this format Left Right data received with separate data burst. Every burst identified with level SYNC signal (Figure page 46). There timing difference between Left Right data burst: channels identified startup order: first burst after path path power-up identifies Left channel data, second Right channel data, then Left Right data repeat after other. must have periods channel case data word periods channel case data word. interface configured single-channel (mono) interface with SPIM (ADSPIM DASPIM). mono interface always exchanges left channel sample. SPI-Format only Slave: Master Mode selected SYNC pins (ADCKP DACKP) affects interface format inverting polarity pin. PCM-Format (DAFORM ADFORM =111): this format monophonic, only receive (DA) transmit (AD) single channel data (Figure page 46). mainly used when voice filters selected. audio filters used then same sample sent from DA-PCM interface both channel path, left channel sample from path sent AD-PCM interface. path right channel sent interface then following must set: ADRTOL=1 (CR27) ENADCL=0 (CR1). Master Mode number periods SYNC period between (see DAPCMF CR22 ADPCMF CR25, Section page details). (ADCKP DACKP) affects interface format inverting polarity pin. SYNCP (ADSYNCP DASYNCP) switches between delayed (SYNCP=0) delayed (SYNCP=1) formats.
Analog inputs
STw5095 stereo Microphone preamplifier stereo Line amplifier, with inputs selectable among (for Microphone preamplifier only), LINEIN (for Line amplifier only) different inputs (for Microphone Line amplifiers). inputs used simultaneously Line amplifiers Microphone preamplifiers.
Microphone preamplifier: very noise input, specifically designed amplitude signals. this reason high input gain keeping constant input impedance whole gain range. However also used line preamplifier because accept high dynamic input signal Vpp). There separate gain attenuation stages order improve ratio when preamplifier output range below full scale (volume control).The gain attenuation controls separate left right channel (CR3 respectively). Preamplifier input selected with bits MICSEL CR18, disconnected when MICMUTE=1. single ended input selected then preamplifier uses selected positive input connects negative input (for both left right channels) CAPMIC pin, which connected through capacitor noise ground (typically same reference ground input). stereo Microphone preamplifier powered with bits ENMICL ENMICR CR1. Line amplifier: designed high level input signal. input gain range Line amplifier input selected with bits LINSEL CR18, disconnected when LINMUTE=1. single ended input selected then amplifier uses selected positive input connects negative input (for both left right channels) CAPLINEIN pin, which connected through capacitor
15/69
Functional Description
STw5095
noise ground (typically same reference ground input). stereo Line amplifier powered with bits ENLINL ENLINR CR1.
Analog output drivers
STw5095 provides different analog signal outputs common mode reference output:
Line Drivers: stereo differential output, used single-ended output just using positive negative pin. drive resistive load. load connected between positive negative pins between ground through decoupling capacitor. output gain regulated with bits CR7, range simultaneously left right channels. When used single ended output effective gain lower. muted with MUTELO CR19. input signal this stereo output come from analog mixer directly from preamplifiers. output Common Mode Voltage level controlled with bits VCML CR19. supply voltage line drivers VCCP Line Drivers powered with bits ENLOL ENLOR CR1. output pins high impedance state with 180k pull-down resistor when Line Drivers powered down. Headphones Drivers: stereo single ended output. drive resistive load deliver output gain regulated with HPLG HPRG bits respectively, with range muted with MUTEHP CR19. input signal this stereo output comes from analog mixer.The output Common Mode Voltage controlled with bits VCML CR19. supply voltage headphones drivers VCCP Headphones Drivers powered with bits ENHPL ENHPR CR2.The output pins high impedance state when Headphones Drivers powered down. Common Mode Voltage Driver: single ended output with output voltage value selectable with bits VCML CR19, from 1.65 steps output voltage should value closest VCCP/2 optimize output drivers performance. Common Mode Voltage Driver designed connected common stereo headphones, that decoupling capacitors needed outputs. supply voltage common mode voltage driver VCCP Common Mode Voltage Driver powered with ENHPVCM CR2.The output high impedance state when Common Mode Voltage Driver powered down. Loudspeaker Driver: monophonic differential output. drive resistive load deliver load. output gain regulated with bits CR7, range input signal loudspeaker driver comes from analog mixers: bits LSSEL CR29 select left channel, right channel, (L+R)/2 (mono) mute. output Common Mode Voltage obtained with internal voltage divider from VCCLS connected CAPLS pin. supply voltage loudspeaker driver VCCLS. Loudspeaker Driver powered with ENLS CR2.The output high impedance state when Loudspeaker Driver powered down.
Note:
Note direct connection VCCLS battery: voltage batteries handheld devices during charging usually below making VCCLS supply suitable direct connection battery. this case STw5095 delivering maximum power load ambient temperature above then simultaneous charging battery overheat device. basic protection scheme implemented STw5095 (activated with LSLIM CR19): limits maximum gain
16/69
STw5095
Functional Description
loudspeaker when VCCLS above removes limit VCCLS below loudspeaker gain left unchanged below with bits LSG. This event (VCCLS generate, enabled (bit VLSMSK CR31), signal.
3.10
Analog mixer
STw5095 send output drivers stereo audio signals from different sources, path (bit MIXDAC CR17), Microphone Preamplifiers (bit MIXMIC CR17) Line Amplifiers (bit MIXLIN CR17). mixer does have gain control inputs, therefore user should reduce levels input signals within analog signal range. stereo Analog Mixer powered with bits ENMIXL ENMIXR CR2.
3.11
path
path converts audio signals from Microphone Preamplifiers (selected with ADMIC CR17) Line Amplifiers (bit ADLIN CR17) inputs digital domain. both inputs selected then converted. After conversion audio data resampled with sample rate converter then processed with internal DSP. different filters selectable (bit ADVOICE CR29): stereo Audio Filter, with offset removal image filtering; standard mono Voice-channel filter (uses left channel input feeds both channel output). path includes digital gain control (ADCLG, ADCRG CR12 CR13 respectively) range maximum gain from Preamplifier interface then When Audio filter selected both paths then audio data summed data sent Audio Interface (see DA2ADG CR15). Left Right channels independently switched save power, needed (bits ENADCL ENADCR CR1)
3.12
path
path converts digital data from digital audio interface analog domain feeds analog mixer. Incoming audio data processed with where different filters selectable (bit DAVOICE CR29): Audio Filter, stereo, with image filtering, bass treble controls (bits BASS TREBLE CR14), de-emphasis filter; standard Voice-channel filter, mono (uses left channel input feeds both channel output). dynamic compression function available both audio voice filters (bit DYNC CR14). path includes digital gain control (DACLG, DACRG CR10 CR11 respectively) range mixing (sidetone) enabled: CR16 details. Left Right channel independently switched save power, needed (bits ENDACL ENDACR CR1)
3.13
Analog-only operation
STw5095 operate without AMCK master clock analog-only functions used. possible Microphone Line preamplifiers signals listen through headphones, loudspeaker send them line-out. analog-only operation enabled with ENOSC CR0. When ENOSC=1 paths cannot used.
17/69
Functional Description
STw5095
Analog Mode STw5095 handle different stereo audio signals, used front external voice codec that does include microphone preamplifiers power drivers: signal sent through Microphone preamplifiers directly line drivers (Transmit path), while Receive signal sent through Line amplifiers selected power drivers.
3.14
Automatic Gain Control (AGC)
STw5095 provides digital Automatic Gain Control path. circuit control input gain preamplifier, Line amplifier both (bits ENAGCMIC ENAGCLIN CR35). When input selected, center gain value used input fixed with bits MICLG, MICRG, LINLG LINRG (like normal operation), then circuit adds gains value range -10.5 +10.5 (or, extended with AGCRANGE CR35, dB), order obtain average level digital interface output range (selected with bits AGCLEV CR35). added gain acts directly input gain, avoid input saturation improve ratio, cannot exceed input gain range. When Line-In inputs selected simultaneously control performed two, preserving balance fixed with input gains. Different values Attack Decay constants selected, depending kind signal control (i.e. voice, music). Attack Decay time constants related data rate (see bits AGCATT AGCDEL CR34).
3.15
Interrupt request:
STw5095 interrupt request feature signal control device occurrence particular events. control registers used choose behavior pin: first Status/ Event Register (CR32), where bits represent status internal function (i.e. voltage above below threshold) event (i.e. voltage changed crossing threshold); second Mask Register (CR31) where mask then corresponding Status/Event Register affect status. always active low. power interrupt request generated Power-On-Reset circuit that sets bits PORMSK CR31 POREV CR32. After this event PORMSK should cleared user IRQCMOS CR33 should according application (open drain CMOS). When event occurs control interface selected with serial output still possible identify event (and relative status) that generated interrupt request. This done setting mask/enable bits CR31) time (with successive writings) reading status. simple example this headset plug-in detection: first HSDETMSK=1 CR31 (with other bits there interrupt request then HSDETMSK=0 HSDETEN=1, read HSDET status pin. Then read CR32 clear content (even data sent out).
18/69
STw5095
Functional Description
3.16
Headset plug-in push-button detection
STw5095 detect plug-in microphone connector press/release event call/answer push-button. application example found below, while specifications found Section page Figure Plug-in push-button detection application note
HDET 200nF VCCA 1.5k Call/Answer Button 10µF 200nF CAPMIC AUX1L AUX1R
STw5095
From Driver Generic Connector
3.17
Microphone biasing circuit
Microphone Biasing Circuit drive mono stereo microphones switch them when needed order save current used microphone biasing network. bits control behavior microphone bias circuit: MBIAS CR17 enables circuit (fixed voltage MBIAS pin), while MBIASPD CR17 affects behavior MBIAS when function enabled. particular when MBIASPD=1 MBIAS pulled down, otherwise left tristate mode. specification microphone biasing circuit found Section page application note shown Section page
19/69
Control Registers
STw5095
(hex)
(00h) (01h) (02h) (03h) (04h) (05h) (06h) (07h) (08h) (09h) CR10 (0Ah) CR11 (0Bh) CR12 (0Ch) CR13 (0Dh) CR14 (0Eh) CR15 (0Fh) CR16 (10h) CR17 (11h) CR18 (12h) CR19 (13h) CR20 (14h) CR21 (15h) CR22 (16h) CR23 (17h) CR24 (18h) CR25 (19h)
Control Registers
Summary
Description
Supply Power Control Power Control Power Control Gain Left Gain Right Line Gain Left Line Gain Right gain gain Gain Gain Digital Gain Left Digital Gain Right Digital Gain Left Digital Gain Right Bass/Treble/De-emphasis mixing gain mix/sidetone gain Mixer Switches Bias Input Switches Drivers Control DAOCK Frequency byte DAOCK Frequency byte Clock Generator Control ADOCK Frequency byte ADOCK Frequency byte Clock Generator Control Data Control Data Control DAC&ADC Data Control Digital Filters Control Soft Reset AMCK Range interrupt Mask Interrupt Status Misc. Control Attack/Decay coeff. Control RESERVED ADMAST DAMAST DYNC MBIAS MBIASPD IN2VCM VCML(1:0) ADMIC LINMUTE ADLIN TREBLE(2:0)
POWERUP ENADCL ENLOL
ENANA ENADCR ENLOR MICLA(2:0) MICRA(2:0)
ENAMCK ENDACL ENHPL
ENOSC ENDACR ENHPR
ENPLL ENMICL ENHPVCM
ENHSD ENMICR ENLS MICLG(4:0) MICRG(4:0)
A24V ENLINL ENMIXL
D12V ENLINR ENMIXR
Def.
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1001 0000 1001 0000 0011 0000 0011 0000 0011 0000 0000 0000 0000 0000 1000 0000 1000
LOG(2:0)
LINLG(4:0) LINRG(4:0) LSG(3:0) HPLG(4:0) HPRG(4:0) DACLG(5:0) DACRG(5:0) ADCLG(5:0) ADCRG(5:0) BASS(3:0) DA2ADG(4:0) AD2DAG(5:0) MIXMIC MIXLIN MICMUTE LSLIM MIXDAC MICLO
0000 0000 0000 0000 0000 0000 0000 0000 0010 0100 0101 1000 0000 0000 0000 0000
LINSEL(1:0) MUTELO MUTEHP
MICSEL(1:0) LSSEL(1:0)
DAOCKF(7:0) DAOCKF(15:8) DAMASTGEN ENDAOCK DAOCK512 DAPCMF(1:0)
0000 0000 0000 0000 0000 0000
ADOCKF(7:0) ADOCKF(15:8) ADMASTGEN ENADOCK ADOCK512 ADPCMF(1:0)
0000 0000
CR26 (1Ah) CR27 (1Bh) CR28 (1Ch) CR29 (1Dh) CR30 (1Eh) CR31 (1Fh) CR32 (20h) CR33 (21h) CR34 (22h) CR35 (23h) CR36 (24h)
ADRTOL AMCKINV SWRES VLSHEN VLSH DACKP DAVOICE PUSHBEN PUSHB
DAFORM(2:0) ADFORM2:0) DASYNCP DA96K HSDETEN HSDET SPIOHIZ AGCATT(3:0) ENAGCLIN ENAGCMIC AGCRANGE DAMONO RXNH VLSHMSK VLSHEV
DASPIM ADSPIM ADCKP ADVOICE AMCKSIN PUSHBMSK PUSHBEV HSDETMSK HSDETEV IRQCMOS ADSYNCP AD96K
DAWL(2:0) ADWL(2:0) ADMONO ADNH CKRANGE(2:0) OVFMSK OVFEV OVFDA PORMSK POREV OVFAD ADHIZ TXNH
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
SPIOSEL(1:0)
AGCDEC(3:0) AGCLEV(3:0)
0000 0000
Note: reserved, write zero
20/69
STw5095
Control Registers
(hex)
(00h) (01h) (02h)
Supply power control
Description
Supply Power Control Power Control Power Control
POWERUP ENADCL ENLOL
ENANA ENADCR ENLOR
ENAMCK ENDACL ENHPL
ENOSC ENDACR ENHPR
ENPLL ENMICL ENHPVCM
ENHSD ENMICR ENLS
A24V ENLINL ENMIXL
D12V ENLINR ENMIXR
Def.
0000 0000 0000 0000 0000 0000
Bits
Name POWERUP ENANA ENAMCK
Val.
Description enabled analog digital blocks power device power down analog blocks enabled analog blocks power down AMCK clock input enabled AMCK clock input disabled Internal Oscillator enabled. analog blocks Oscillator clock Internal Oscillator power down enabled power down Headset Plug-in Detector enabled Headset Plug-in Detector disabled Analog Supply Pins voltage range 2.4V<VCCA<2.7V Analog Supply Pins voltage range 2.7V<VCCA<3.3V Digital Pins voltage range 1.2V<VCCIO<1.8V Digital Pins voltage range 1.71V<VCCIO<VCC
Def.
ENOSC
ENPLL ENHSD
A24V
D12V
21/69
Control Registers
STw5095
Bits
Name ENADCL ENADCR ENDACL ENDACR ENMICL ENMICR ENLINL ENLINR
Value Value
Description left channel converter enabled left channel converter power down right channel converter enabled right channel converter power down left channel converter enabled left channel converter power down right channel converter enabled right channel converter power down left channel microphone preamplifier enabled left channel microphone preamplifier power down right channel microphone preamplifier enabled right channel microphone preamplifier power down left channel line-in preamplifier enabled left channel line-in preamplifier power down right channel line-in preamplifier enabled right channel line-in preamplifier power down Description left channel line driver enabled left channel line driver power down (default) right channel line driver enabled right channel line driver power down (default) left channel headphones driver enabled left channel headphones driver power down (default) right channel headphones driver enabled right channel headphones driver power down (default) headphones reference voltage generator enabled headphones reference voltage generator power down (def) loudspeaker amplifier enabled loudspeaker amplifier power down (default) left channel analog output mixer enabled left channel analog output mixer power down (default) right channel analog output mixer enabled right channel analog output mixer power down (default)
Def.
Name ENLOL ENLOR ENHPL ENHPR ENHPVCM ENLS ENMIXL ENMIXR
Def.
22/69
STw5095
Control Registers
(hex)
(03h) (04h) (05h) (06h) (07h) (08h) (09h) CR10 (0Ah) CR11 (0Bh) CR12 (0Ch) CR13 (0Dh)
Gains
Description
Gain Left Gain Right Line Gain Left Line Gain Right gain gain Gain Gain Digital Gain Left Digital Gain Right Digital Gain Left Digital Gain Right
MICLA(2:0) MICRA(2:0)
MICLG(4:0) MICRG(4:0)
Def.
0000 0000 0000 0000 0000 1001 0000 1001 0000 0011 0000 0011 0000 0011 0000 0000 0000 0000 0000 1000 0000 1000
LOG(2:0)
LINLG(4:0) LINRG(4:0) LSG(3:0) HPLG(4:0) HPRG(4:0) DACLG(5:0) DACRG(5:0) ADCLG(5:0) ADCRG(5:0)
Bits
Name Name
Value
Description Left (CR3) Right (CR4) Channels Microphone Attenuation Gain (default) -1.5 Gain -3.0 Gain .step -9.0 Gain -12.0 Gain Left (CR3) Right (CR4) Channels Microphone Gain Gain (default) Gain Gain .step 39.0 Gain
Def.
MICLA(2:0) MICRA(2:0)
00000 00001 00010 11010
MICLG(4:0) MICRG(4:0)
00000
Bits
Name Name
Value
Description Left (CR5) Right (CR6) Channels Line Gain 18.0 Gain 16.0 Gain 14.0 Gain .step Gain (default) .step -20.0 Gain
Def.
LINLG(4:0) LINRG(4:0)
00000 00001 00010 01001 10011
01001
23/69
Control Registers
STw5095
Bits
Name
Value
Description Left Right Channel Line Drivers Gain
Def.
LOG(2:0)
Gain Differential Output -18.0 Gain (default) -15.0 Gain -12.0 Gain .step Gain Loudspeaker Gain Gain Gain Gain Gain (default) .step -24.0 Gain
Equivalent Single-Ended Gain -24.0 Gain (default) -21.0 Gain -18.0 Gain .step -6.0 Gain
LSG(3:0)
0000 0001 0010 0011 1111
0011
Bits
Name Name
Value
Description Left (CR8) Right (CR9) Channels Headphones Driver Gain Gain -2.0 Gain -4.0 Gain -6.0 Gain (default) .step -40.0 Gain
Def.
HPLG(4:0) HPRG(4:0)
00000 00001 00010 00011 10100
00011
24/69
STw5095
Control Registers
Bits
Name CR10 Name CR11
Value
CR10 CR11 Description Left (CR10) Right (CR11) Channels Digital Gain Gain (default) -1.0 Gain -2.0 Gain -3.0 Gain -4.0 Gain -5.0 Gain -6.0 Gain -7.0 Gain -8.0 Gain -9.0 Gain -10.0 Gain -11.0 Gain -12.0 Gain -13.0 Gain -14.0 Gain -15.0 Gain -16.0 Gain -17.0 Gain -18.0 Gain -20.0 Gain -22.0 Gain -24.0 Gain -26.0 Gain -28.0 Gain -30.0 Gain -32.0 Gain -34.0 Gain -36.0 Gain -38.0 Gain -41.0 Gain -44.0 Gain -47.0 Gain -50.0 Gain -53.0 Gain -56.0 Gain -59.0 Gain -65.0 Gain Gain
Def.
DACLG(5:0) DACRG(5:0)
000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101
000000
25/69
Control Registers
STw5095
Bits
Name CR12 Name CR13
Value
CR12 CR13 Description Left (CR12) Right (CR13) Channels Digital Gain Gain Gain Gain Gain Gain Gain Gain Gain Gain (default) -1.0 Gain -2.0 Gain -3.0 Gain -4.0 Gain -5.0 Gain -6.0 Gain -7.0 Gain -8.0 Gain -9.0 Gain -10.0 Gain -11.0 Gain -12.0 Gain -14.0 Gain -16.0 Gain -18.0 Gain -20.0 Gain -22.0 Gain -24.0 Gain -26.0 Gain -28.0 Gain -30.0 Gain -33.0 Gain -36.0 Gain -39.0 Gain -42.0 Gain -45.0 Gain -48.0 Gain -51.0 Gain -57.0 Gain Gain
Def.
ADCLG(5:0) ACDRG(5:0)
000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110
001000
26/69
STw5095
Control Registers
(hex)
CR14 (0Eh) CR15 (0Fh) CR16 (10h)
control
Description
Bass/Treble/De-emphasis mixing gain mix/sidetone gain
DYNC
TREBLE(2:0)
BASS(3:0) DA2ADG(4:0)
Def.
0000 0000 0000 0000 0000 0000
AD2DAG(5:0)
Bits
Name DYNC
Value
CR14 Description Audio Dynamic Compression path enabled Audio Dynamic Compression path disabled Treble Control path +6.0 Treble Gain +4.0 Treble Gain +2.0 Treble Gain Treble Gain -2.0 Treble Gain -4.0 Treble Gain -6.0 Treble Gain De-emphasis filter enabled Bass Control path +12.5 Bass Gain +10.0 Bass Gain +7.5 Bass Gain +5.0 Bass Gain +2.5 Bass Gain Bass Gain -2.5 Bass Gain -5.0 Bass Gain -7.5 Bass Gain -10.0 Bass Gain -12.5 Bass Gain
Def.
TREBLE(2:0)
0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011
BASS(3:0)
0000
27/69
Control Registers
STw5095
Bits
Name
Value
CR15 Description mixing (Audio filter path selected) mixing Disabled (default) +2.0 Gain Gain -2.0 Gain -4.0 Gain -6.0 Gain -8.0 Gain -10.0 Gain -12.0 Gain -14.0 Gain -16.0 Gain -18.0 Gain -20.0 Gain -22.0 Gain -24.0 Gain -26.0 Gain -28.0 Gain -30.0 Gain -32.0 Gain -34.0 Gain -36.0 Gain -38.0 Gain -40.0 Gain
Def.
DA2ADG(4:0)*
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110
00000
When Voice filter path selected this function disabled Note: mixing performed data rate, rates different then asynchronous sampling artifacts occur.
28/69
STw5095
Control Registers
Bits
Name
Value
CR16 Description mixing (sidetone) mixing Disabled (default) -1.0 Gain -2.0 Gain -3.0 Gain -4.0 Gain -5.0 Gain -6.0 Gain -7.0 Gain -8.0 Gain -9.0 Gain -10.0 Gain -11.0 Gain -12.0 Gain -13.0 Gain -14.0 Gain -15.0 Gain -16.0 Gain -17.0 Gain -18.0 Gain -19.0 Gain -20.0 Gain -21.0 Gain -22.0 Gain -23.0 Gain -24.0 Gain -25.0 Gain -26.0 Gain -27.0 Gain -28.0 Gain -29.0 Gain -30.0 Gain -31.0 Gain -32.0 Gain -33.0 Gain -34.0 Gain -35.0 Gain -36.0 Gain -37.0 Gain -38.0 Gain -39.0 Gain -40.0 Gain -41.0 Gain -42.0 Gain
Def.
AD2DAG(5:0)
000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010
000000
29/69
Control Registers
STw5095
(hex)
CR17 (11h) CR18 (12h) CR19 (13h)
Analog functions
Description
Mixer Switches Bias Input Switches Drivers Control
MBIAS
MBIASPD IN2VCM VCML(1:0)
ADMIC LINMUTE
ADLIN
MIXMIC
MIXLIN MICMUTE LSLIM
MIXDAC
MICLO
Def.
0000 0000 0010 0100 0101 1000
LINSEL(1:0) MUTELO MUTEHP
MICSEL(1:0) LSSEL(1:0)
Bits
Name MBIAS
Value
CR17 Description Microphone Bias Enabled (2.1V MBIAS Pin) Microphone Bias Disabled MBIAS pulled down when Microphone Bias disabled MBIAS High Impedance state when Microphone Bias disabled Microphone Preamplifiers connected path Microphone Preamplifiers connected path Line Preamplifiers connected path Line Preamplifiers connected path Microphone Preamplifiers connected Mixers Microphone Preamplifiers connected Mixers Line Preamplifiers connected Mixers Line Preamplifiers connected Mixers Stereo path connected Mixers Stereo path connected Mixers Microphone Preamplifiers connected Line Drivers Mixers connected Line Drivers
Def.
MBIASPD
ADMIC ADLIN MIXMIC MIXLIN MIXDAC MICLO
30/69
STw5095
Control Registers
Bits
Name IN2VCM LINMUTE
Value
CR18 Description Unused Analog input pins biased Common Mode voltage Unused Analog input pins high impedance state Line Preamplifiers muted Line Preamplifiers muted Input Pins connected Line Preamplifiers LINMUTE=0)
Def.
LINSEL(1:0)
LINEIN AUX1 AUX2 AUX3
(LINEINL, LINEINR) (AUX1L, AUX1R) (AUX2LP-AUX2LN, AUX2RP-AUX2RN)
(AUX3L, AUX3R)
MICMUTE
Microphone Preamplifiers muted Microphone Preamplifiers muted Input Pins connected Microphone Preamplifiers MICMUTE=0)
MICSEL(1:0)
AUX1 AUX2 AUX3
(MICLP-MICLN, MICRP-MICRN) (AUX1L, AUX1R) (AUX2LP-AUX2LN, AUX2RP-AUX2RN)
(AUX3L, AUX3R)
Bits
Name
Value
CR19 Description Common Mode Voltage Level Line Headphones drivers 1.20 1.35 (default) 1.50 1.65 Line Drivers muted Line Drivers muted Headphones Drivers (HP) muted Headphones Drivers (HP) muted Loudspeaker Driver (LS) gain limited when VCCLS above 4.2V Loudspeaker Driver (LS) gain limited Mute Right Left Mono Loudspeaker Driver (LS) muted Right Channel Mixer only connected Loudspeaker driver Left Channel Mixer only connected Loudspeaker driver (Left Right)/2 Channel Mixers connected Loudspeaker driver
Def.
VCML(1:0)
MUTELO MUTEHP
LSLIM
LSSEL(1:0)
31/69
Control Registers
STw5095
(hex)
CR20 (14h) CR21 (15h) CR22 (16h) CR23 (17h) CR24 (18h) CR25 (19h)
Digital audio interfaces master mode clock generators
Description
DAOCK Frequency byte DAOCK Frequency byte Clock Generator Control ADOCK Frequency byte ADOCK Frequency byte Clock Generator Control ADMAST DAMAST
Def.
0000 0000 0000 0000
DAOCKF(7:0) DAOCKF(15:8) DAMASTGEN ENDAOCK DAOCK512 DAPCMF(1:0)
0000 0000 0000 0000 0000 0000
ADOCKF(7:0) ADOCKF(15:8) ADMASTGEN ENADOCK ADOCK512 ADPCMF(1:0)
0000 0000
Bits
Name CR21-20 Name CR24-23
Value
CR21-20 CR24-23 Description following formulas used obtain value desired respectively clock generator
round
Def.
AMCK MCKCOEFF
round
AMCK MCKCOEFF
15-0
DAOCKF(15:0) ADOCKF(15:0)
OCK: AMCK: MCKCOEFF: OSR: Data Rate (DA_SYNC AD_SYNC frequency Master Mode) Oversampled Clock Frequency (DA_OCK AD_OCK) Input Master Clock Frequency CR30 definition CR22 CR25
0000h
Note: CR21-20 CR24-23 meaningful Master Mode Only.
32/69
STw5095
Control Registers
Bits
Name CR22 (Name CR25) DAMAST (ADMAST) DAMASTGEN (ADMASTGEN) ENDAOCK (ENADOCK)
Value
CR22 CR25 Description (AD) Audio interface Master Mode (low impedance output) (AD) Audio interface Slave Mode (high impedance input) (AD) Master Generator enabled (AD) Master Generator disabled DA_OCK (AD_OCK) Output Clock enabled DA_OCK (AD_OCK) Output Clock disabled Definition DA_OSR (AD_OSR) DA_OCK/DA_SYNC (AD_OCK/AD_SYNC) Ratio Master Mode DA_OCK/DA_SYNC (AD_OCK/AD_SYNC) Ratio Master Mode DA_CK/DA_SYNC (AD_CK/AD_SYNC) Ratio Master Mode when CR26 DAWL=000 (CR27 ADWL=000) when CR26 DAWL000 (CR27 ADWL000) when CR22 DAOCK512=0 (CR25 ADOCK512=0) when CR22 DAOCK512=1 (CR25 ADOCK512=1)
Def.
DAOCK512 (ADOCK512)
DAPCMF(1:0) (ADPCMF(1:0))
33/69
Control Registers
STw5095
(hex)
CR26 (1Ah) CR27 (1Bh) CR28 (1Ch)
Digital audio interfaces
Description
Data Control Data Control DAC&ADC Data Control
ADRTOL AMCKINV
DAFORM(2:0) ADFORM2:0)
DASPIM ADSPIM
DAWL(2:0) ADWL(2:0)
Def.
0000 0000 0000 0000
DACKP
DASYNCP
DAMONO
ADCKP
ADSYNCP
ADMONO
ADHIZ
0000 0000
Bits
Name
Value
CR26 Description Audio Interface Format Selection
Def.
DAFORM(2:0)
Delayed Format (I2S Compatible) Left Aligned Format Right Aligned Format Format Format Format (uses left channel) interface mode receives word both channels interface mode receives words (alternated, left channel first) interface word length CR27 Description Right Channel sent (must ENADCR=0 CR1) Normal Operation Audio Interface Format Selection Delayed Format (I2S compatible) Left Aligned Format Right Aligned Format Format Format Format (sends left channel) interface mode sends channel (left) interface mode sends channels (alternated, left first) interface word length
DASPIM
DAWL(2:0)
Value
Bits
Name ADRTOL
Def.
ADFORM(2:0)
ADSPIM
ADWL(2:0)
34/69
STw5095
Control Registers
Bits
Name AMCKINV DACKP
Value AMCK inverted AMCK inverted
CR28 Description
Def.
Clock (DA_CK) polarity inverted Clock (DA_CK) polarity inverted Formats Interface Delayed format Delayed Format
DASYNCP Delayed, Left-aligned, Right-aligned Formats Interface Sync (DA_SYNC) polarity inverted Sync (DA_SYNC) polarity inverted Mono Mode: (L+R)/2 from Audio Interface used both channels Stereo Mode Clock (AD_CK) polarity inverted Clock (AD_CK) polarity inverted Formats Interface Delayed format Delayed Format Delayed, Left-aligned, Right-aligned Formats Interface Sync (DA_SYNC) polarity inverted Sync (DA_SYNC) polarity inverted Mono Mode: (L+R)/2 from sent both channels Audio Interface Stereo Mode data (AD_DATA) high impedance state when data available data (AD_DATA) forced when data available
DAMONO
ADCKP
ADSYNCP
ADMONO
ADHIZ
35/69
Control Registers
STw5095
(hex)
CR29 (1Dh) CR30 (1Eh)
Digital filters, software reset master clock control
Description
Digital Filters Control Soft Reset AMCK Range
SWRES
DAVOICE
DA96K
RXNH
ADVOICE AMCKSIN
AD96K
ADNH CKRANGE(2:0)
TXNH
Def.
0000 0000 0000 0000
Bits
Name DAVOICE DA96K RXNH ADVOICE AD96K ADNH TXNH
Value Value
CR29 Description path Voice filter enabled (single channel, left used) path Audio filters enabled path data rate range path data rate range path High pass Voice filter disabled path High pass Voice filter enabled (300Hz 8kHz rate) path Voice filter enabled (single channel, left used) path Audio filters enabled path data rate range path data rate range path Audio filter disabled path Audio filter enabled path High pass Voice filter disabled path High pass Voice filter enabled (300Hz 8kHz rate) CR30 Description Software reset: registers content reset default value Control Register content left unchanged Signal AMCK sinusoid Signal AMCK square wave AMCK range 12.0 16.0 24.0 32.0 MCKCOEFF
Def.
Bits
Name SWRES AMCKSIN
Def.
CKRANGE(2:0)
12.0 16.0 24.0
36/69
STw5095
Control Registers
(hex)
CR31 (1Fh) CR32 (20h) CR33 (21h)
Interrupt control control interface mode
Description
interrupt Mask Interrupt Status Misc. Control
VLSHEN VLSH
PUSHBEN PUSHB
HSDETEN HSDET SPIOHIZ
VLSHMSK VLSHEV
PUSHBMSK PUSHBEV
HSDETMSK HSDETEV IRQCMOS
OVFMSK OVFEV OVFDA
PORMSK POREV OVFAD
Def.
0000 0000 0000 0000 0000 0000
SPIOSEL(1:0)
Bits
Name VLSHEN PUSHBEN HSDETEN VLSHMSK PUSHBMSK HSDETMSK OVFMSK PORMSK
Value
CR31 Description VLSH status seen output VLSH status masked PUSHB status seen output PUSHB status masked HSDET status seen output HSDET status masked VLSH event seen output VLSH event masked PUSHB event seen output PUSHB event masked HSDET event seen output HSDET event masked event seen output event masked event seen output event masked
Def.
Note:
Value
when (CR31 CR32) when (CR31 CR32)
37/69
Control Registers
STw5095
Bits
Name
Read only VCCLS above VCCLS below
CR32 Description
Def.
VLSH*
PUSHB* HSDET* VLSHEV PUSHBEV HSDETEV OVFEV POREV
Headset Button pressed Headset Button released Headset Connector inserted Headset Connector inserted VLSH changed VLSH changed Headset Button Status changed Headset Button Status changed Headset Connector Status changed Headset Connector Status changed Audio Data overflow occurred Audio Data overflow occurred Device reset Power-On-Reset Device reset Power-On-Reset
Note: content bits CR32 cleared after reading, while left unchanged accessed writing. *Bits represent status when Control register read, when event occurred.
Bits
Name
Val.
CR33 Description Control Interface high impedance state when inactive Control Interface zero when inactive Selection Control Interface output. Control registers cannot read mode Output sent Output sent DA_OCK Output sent AD_OCK Interrupt Request CMOS (active low) Interrupt Request Pull Down overflow (saturation) occurred path overflow occurred channel overflow (saturation) occurred path overflow occurred channel
Def.
SPIOHIZ
SPIOSEL(1:0)
IRQCMOS OVFDA OVFAD
Note: content bits CR33 cleared after reading, while left unchanged accessed writing.
38/69
STw5095
Control Registers
4.10
(hex)
CR34 (22h) CR35 (23h)
Description
Attack/Decay coeff. Control
Def.
0000 0000 0000 0000
AGCATT(3:0) ENAGCLIN ENAGCMIC AGCRANGE
AGCDEC(3:0) AGCLEV(3:0)
Bits
Name
Value
CR34 Description Attack Time Constant; FS=AD data rate
Def.
AGCATT(3:0)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101
Audio filter path 4096 2048 1365 1024
Voice filter path 8192 4096 2731 2048 1365 1024
0000
Decay Time Constant; FS=AD data rate 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Audio filter path 65536 32768 21845 16384 10923 8192 5461 4096 2731 2048 1365 1024 Voice filter path 131072/ 65536 43691 32768 21845 16384 10923 8192 5461 4096 2731 2048 1365 1024
AGCDEC(3:0)
0000
39/69
Control Registers
STw5095
Bits
Name ENAGCLIN ENAGCMIC AGCRANGE
Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
CR35 Description control path acts Line Gain control path does Line Gain control path acts Gain control path does Gain action range -21.0 +21.0 action range -10.5 +10.5 requested output level -30.0 Gain -30.0 Gain -27.0 Gain -24.0 Gain -21.0 Gain -18.0 Gain -15.0 Gain -12.0 Gain -9.0 Gain -6.0 Gain
Def.
AGCLEV(3:0)
0000
40/69
STw5095
Control Interface Master Clock
Control Interface Master Clock
Control interface mode
Figure Control interface format
DATA STOP DATA DATA data bytes STOP
WRITE SINGLE BYTE
START
DEVICE ADDRESS
ADDRESS
WRITE MULTI BYTE
START
DEVICE ADDRESS
ADDRESS
CURRENT ADDR READ SINGLE BYTE
START
DEVICE ADDRESS
Current DATA STOP
CURRENT ADDR READ MULTI BYTE
START
DEVICE ADDRESS
Current DATA
Curr REG+m DATA data bytes STOP
RANDOM ADDR READ SINGLE BYTE
START
DEVICE ADDRESS
DEVICE ADDRESS
DATA
ADDRESS START
STOP DEVICE ADDRESS
RANDOM ADDR READ MULTI BYTE
START
DATA
DATA
DEVICE ADDRESS
ADDRESS START
data bytes
STOP
Note:
CMOD tied
Figure Control interface: format timing
tBUF (STA) tLOW (DAT) tHIGH (DAT) (STA) (STA) (STO)
SCLK
STOP START START repeated
41/69
Control Interface Master Clock
STw5095
Control interface timing with format
Symbol fSCL tHIGH tLOW tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF Parameter Clock frequency Clock pulse width high Clock pulse width SCLK rise time SCLK fall time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time free time 1300 1300 1000 Test Condition Min. Typ. Max. Unit
Control interface mode
Figure Control Interface format(1)
SCLK SDIN
Address
Data
SPIOHIZ=1
Data
CMOD tied VCCIO; position selected with bits SPIOSEL CR33.
42/69
STw5095
Figure Control interface: format timing
Control Interface Master Clock
tHICS
tSCSF tPSCK tLSCK tHSCK tHCS tSCSR
SCLK
tSDI tHDI
SDIN
tDDOF
SPIOHIZ=1 SPIOHIZ=0
tDDO
tDDOL
Control interface signal timing with format
Symbol tHICS tSCSR tSCSF tHCS tSDI tHDI tDDOF tDDO tDDOL tPSCK tHSCK tLSCK Parameter pulse width high Setup time rising edge SCLK rising edge Setup time falling edge SCLK rising edge Hold time rising edge from SCLK rising edge Setup time SDIN SCLK rising edge Hold time SDIN from SCLK rising edge first Delay time from SCLK falling edge Delay time from SCLK falling edge Delay time from rising edge Period pulse width high pulse width Measured from Measured from Test Condition Min. Typ. Max. Unit
43/69
Control Interface Master Clock
STw5095
Master clock timing
AMCK timing
Symbol tCKDC Parameter AMCK duty cycle AMCK range MHz-8 MHz-32 Min. Typ. Max. Unit
44/69
STw5095
Audio Interfaces
Figure
Audio Interfaces
Audio interfaces formats: delayed, left right justified
format (delayed) with default polarity settings, ADHIZ=0
DA_SYNC/ AD_SYNC DA_CK/ AD_CK
AD_CK/DA_CK AD_CK/DA_CK
DA_DATA
n-bit word Left data
n-bit word Right data
AD_DATA
n-bit word Left data
n-bit word Right data
Left justified format with default polarity settings, ADHIZ=0
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA
n-bit word Left data
n-bit word Right data
AD_DATA
n-bit word Left data
n-bit word Right data
Right justified format with default polarity settings
AD_CK/DA_CK
AD_CK/DA_CK
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA
n-bit word Left data
n-bit word Right data
AD_DATA
n-bit word Left data
n-bit word Right data
45/69
Audio Interfaces
STw5095
Figure
Audio interfaces formats: DSP,
format delayed non-delayed (default AD_CK/DA_CK polarity, ADHIZ=0)
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA
SYNCP=0
SYNCP=1
n-bit word Left data
n-bit word Right data
AD_DATA
n-bit word Left data
n-bit word Right data
format (slave only) (default AD_CK/DA_CK polarity, ADHIZ=1 Stereo Mono)
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA
High impedance
n-bit word Left/Mono data
n-bit word Right/Mono data
AD_DATA
n-bit word Left/Mono data
n-bit word Right/Mono data
format (default AD_CK/DA_CK polarity, ADHIZ=1)
DA_SYNC/ AD_SYNC
SYNCP=0
SYNCP=1
DA_CK/ AD_CK DA_DATA
n-bit word Mono data n-bit word Mono data High impedance
AD_DATA
46/69
STw5095
Figure Audio interface timings: Master mode
DA_SYNC/ AD_SYNC
tDSY
Audio Interfaces
DA_CK/ AD_CK
CKP=0
CKP=1
tSDDA tHDDA
DA_DATA
tDAD ADHIZ=1 ADHIZ=0 tDAD ADHIZ=1 ADHIZ=0 ADHIZ=1 ADHIZ=0 tDAD tDADZ ADHIZ=1 ADHIZ=0
AD_DATA format only
AD_DATA other formats
Figure Audio interface timing: Slave mode
DA_SYNC/ AD_SYNC
tHSY tSSY
DA_CK/ AD_CK
CKP=0
tHCK tLCK
CKP=1
tSDDA tHDDA tPCK
DA_DATA
tDADST ADHIZ=1 ADHIZ=0 tDAD ADHIZ=1 ADHIZ=0 tDAD ADHIZ=1 ADHIZ=0 tDAD tDADZ ADHIZ=1 ADHIZ=0
AD_DATA format
AD_DATA other formats
47/69
Audio Interfaces
STw5095
Audio interface signals timing
Symbol Parameter Delay AD_SYNC/ DA_SYNC edge from AD_CK/DA_CK active edge Setup time DA_DATA DA_CK active edge Hold time DA_DATA from DA_CK active edge Delay AD_DATA edge from AD_CK active edge Delay first AD_DATA AD_SYNC active edge comes edge from AD_SYNC after AD_CK active edge active edge Delay AD_DATA high impedance from AD_SYNC inactive edge Setup time AD_SYNC/ DA_SYNC AD_CK/ DA_CK active edge Hold time AD_SYNC/ DA_SYNC from AD_CK/ DA_CK active edge Period AD_CK/DA_CK AD_CK/DA_CK pulse width high AD_CK/DA_CK pulse width format Test Condition Min. Typ. Max. Unit
tDSY
Master Mode
tSDDA tHDDA tDAD
tDADST
tDADZ
tSSY
Slave Mode
tHSY tPCK tHCK tLCK
Slave Mode Slave Mode Measured from Measured from
48/69
STw5095
Timing Specifications
Timing Specifications
Unless otherwise specified, VCCIO 1.71 V,Tamb -30°C 85°C, capacitive load typical characteristics specified VCCIO Tamb signals referenced GND, Note below figure timing definitions. Figure A.C. testing input-output waveform
INPUT OUTPUT
TEST POINTS
Testing: inputs driven logic logic `0'. Timing measurements made logic logic `0'.
Note:
signal valid above below invalid between VIH. purpose this specification following conditions apply (see Figure above): input signal defined VCCIO, VCCIO, 10ns, 10ns. Delay times measured from inputs signal valid output signal valid. Setup times measured from data input valid clock input invalid. Hold times measured from clock signal valid data input invalid. timing specifications subject change.
Note:
49/69
Operative Ranges
STw5095
Operative Ranges
Absolute maximum ratings
Parameter Value -0.5 -0.5 -0.5 GND-0.5 VCCA+0.5 GND-0.5 VCCIO+0.5 Unit
VCCIO VCCA VCCP VCCLS Voltage Analog Inputs (VCCA 3.3V) Maximum Power delivered load from LSP/N Peak Current HPR,HPL Current VCCP, VCCLS, GNDP Current digital output Voltage digital input (VCCIO 2.7V); limited 50mA Storage temperature range Operating temperature range(1)
some operating conditions temperature limited Loudspeaker Driver description from Section details.
Symbol VCCA VCCIO VCCP VCCLS
Operative supply voltage
Parameter Digital supply Analog supply Note: VCCA Digital supply Stereo power drivers supply Mono power driver supply Single supply voltage range VCC=VCCA=VCCIO=VCCP=VCCLS A24V=1 (bit CR0) A24V=0 (bit CR0) A24V=1 (bit CR0) D12V=0 (bit CR0) D12V=1 (bit CR0) Condition Min. 1.71 1.71 VCCA VCCA Max. Unit
50/69
STw5095
Operative Ranges
Power Dissipation
Unless otherwise specified, VCCP VCCLS VCCA 2.7V 3.3V, VCCIO 1.71V 2.7V, Tamb -30°C 85°C, analog outputs loaded; typical characteristics specified VCCIO 1.8V, VCCP VCCLS VCCA 2.7V, Tamb 25°C.
Symbol POFF PDAAD Parameter Power Down Dissipation Stereo power Stereo power Stereo ADC+DAC power Stereo Analog Path power Test Condition Master Clock AMCK=13MHz Min. Typ. 26.3 22.6 44.0 13.8 Max. Unit
Typical power dissipation
Tamb 25°C; Analog Supply: VCCP VCCLS VCCA 2.7V; Digital Supply:VCCIO 1.8V Full scale signal every path, load analog outputs.
Master Clock
Function CR0-CR2 setting CR0=0x00 CR1=0x00 CR2=0x00 CR0=0xD0 CR1=0x0C CR2=0xC0 CR0=0xD0; CR1=0x0C; CR2=0xC3 MICLO=1 MICSEL=2 MIXMIC=1 MICSEL=2 Other settings Supply Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Current 0.02 0.20 Power 0.05 0.36 0.41 11.6 11.6 14.6 14.6
Power Down
Stereo analog path (Mic-LO) Stereo analog path (Mic-Mixer-LO)
51/69
Operative Ranges
STw5095
Master clock AMCK
Function CR0-CR2 setting CR0=0x00 CR1=0x00 CR2=0x00 CR0=0xE8 CR1=0xCC CR2=0x00 CR0=0xE8 CR1=0x30 CR2=0x33 CR0=0xE8 CR1=0x0C CR2=0xC0 CR0=0xE8 CR1=0xFC CR2=0x33 CR0=0xE8 CR1=0xFF CR2=0xF3 CR0=0xE8 CR1=0xA8 CR2=0x06 MICSEL=1 ADMIC=1 Other settings Supply Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: VCCA,VCCP: VCCLS: Digital Total: Current 0.02 2.20 13.5 15.2 Power 0.05 3.96 4.01 21.3 26.3 16.5 23.3 13.0 13.8 36.5 10.4 46.9 41.0 10.4 51.4 18.4 28.4
Power Down
Stereo
Stereo
MIXDAC=1
Stereo analog path (Mic-LO) Stereo Stereo Stereo Stereo Stereo analog path
MICLO=1 MICSEL=2 MICSEL=2 ADMIC=1 MIXDAC=1 LINSEL=2; MICSEL=2 ADLIN=1;MIXDAC=1 MICLO=1 MICSEL=2; LSMODE=2 ADMIC=1 MIXDAC=1 ADVOICE=1 DAVOICE=1
Voice TX+RX
52/69
STw5095
Electrical Characteristics
Electrical Characteristics
Unless otherwise specified, VCCIO 1.71 Tamb -30°C 85°C; typical characteristic specified VCCIO Tamb 25°C; signals referenced GND.
Symbol
Digital interfaces
Parameter Input voltage Test Condition digital inputs 10µA 10µA VCCIO-0.1 VCCIO-0.4 Min. Typ. Max. Unit
Input high voltage
digital inputs, digital outputs
Output voltage
Output high voltage
digital outputs
Input current
digital input, digital input, VCCIO Tristate outputs
Input high current Output current high impedance (Tristate)
Note:
Figure A.C. testing input-output waveform page
Symbol CAMCK VAMCK
AMCK with sinusoidal input
Parameter Minimum External Capacitance AMCK sinusoidal voltage swing Test Condition AMCKSIN=1, CR30 AMCKSIN=1, CR30 Min. VCCIO Typ. Max. Unit
53/69
Electrical Characteristics
STw5095
Symbol IMIC RMIC RLIN RLHP CLHP
Analog interfaces
Parameter input leakage input resistance Line input resistance Headphones (HP) drivers load resistance Headphones (HP) drivers load capacitance Loudspeaker (LS) differential driver load resistance Loudspeaker (LS) differential driver load capacitance Differential offset voltage LSP, Line (OL) diff./singleended driver load resistance Line (OL) diff./singleended driver load capacitance HPL, GNDP VCMHP HPL, GNDP VCMHP Test Condition GND< VMIC< VCCA Min. -100 14.4 16/32 Typ. Max. +100 Unit
RLLS
CLLS
VOFFLS
OLP/ORP OLN/ORN OLP/ORP (decoupled) OLP/ORP OLN/ORN OLP/ORP
RLOL
CLOL
with series resistor
Symbol HDVL HDVH PBVL PBVH
Headset plug-in push-button detector
Parameter Plug-in detected Plug-in undetected Plug-in detector hysteresis Push-button pressed Push-button released Push-button de-bounce time Voltage HDET Voltage HDET Test Condition Voltage HDET Voltage HDET VCCA-0.5 Min. Typ. Max. VCCA-1 Unit
54/69
STw5095
Electrical Characteristics
Symbol VMBIAS IMBIAS RMBIAS CMBIAS PSRMB4 PSRMB20
Microphone bias
Parameter MBIAS output voltage MBIAS output current MBIAS output load MBIAS output capacitance MBIAS power supply rejection f<4kHz f<20kHz From MBIAS ground Test Condition Min. 1.95 Typ. Max. 2.25 Unit
Symbol PSRL20 PSRL200 PSRPH PSRPOS PSRPOD PSRAM PSRAL
Power supply rejection ratio
Parameter PSRR VCCLS Test Condition Each output(LSP, LSN) f<20kHz f<200kHz Headphones f<20kHz Line single ended f<20kHz Line differential f<20kHz input f<20kHz Line f<20kHz Min. Typ. Max. Unit
PSRR VCCP
PSRR VCCA
Symbol VLSLIMH VLSLIML VLSLIMD
gain limiter
Parameter High voltage VCCLS (VLSH=1) voltage VCCLS (VLSH=0) VCCLS Hysteresis Test Condition VCCLS raising VCCLS falling Min. Typ. Max. Unit
Note: CR32 VLSH definition. Loudspeaker driver description Section details.
55/69
Analog Input/output Operative Ranges
STw5095
10.1
Analog Input/output Operative Ranges
Analog levels
Reference full scale analog levels
Symbol Parameter 0dBFS level 0dBFS level voltage mode Test Condition 2.7V VCCA 3.3V Min. Typ. 3.18 Max. Unit dBVpp dBVpp
2.4V VCCA 2.7V
10.2
Microphone input levels
Absolute levels pins connected preamplifiers
Analog supply range: VCCA
Symbol Parameter Overload level, single ended Overload level,single ended, versus gain Overload level, differential Test Condition Min. Typ. (MIC_Gain) 1.41 (MIC_Gain) Max. Unit mVRMS dBFS dBFS mVRMS dBFS dBFS
gain
gain
gain
Overload level, differential, gain versus gain
Note: When VCCA voltage values reduced 2dB.
56/69
STw5095
Analog Input/output Operative Ranges
10.3
Line input levels
Absolute levels pins connected line-in amplifiers
Analog supply range: VCCA
Symbol Parameter Overload level, single ended Overload level (single ended) versus line gain Test Condition Line gain from 20dB Min. Typ. (Line_In_Gain) 1.41 (Line_In_Gain) Max. Unit mVRMS dBFS dBFS mVRMS dBFS dBFS
Line gain
20dB Overload level (differential) Line gain from Overload level (differential) Line gain versus line gain
Note: When VCCA values reduced
10.4
Line output levels
Absolute levels OLP/OLN, ORP/ORN
Analog supply range: VCCA
Symbol Parameter Test Condition gain Full scale digital input Gain Full scale digital input Min. Typ. 1.41 Max. Unit mVRMS dBFS mVRMS dBFS
Output level, single ended
Output level, differential
Note: When VCCA values reduced
57/69
Analog Input/output Operative Ranges
STw5095
10.5
Power output levels
Absolute levels
Analog supply range: VCCA
Symbol Parameter Test Condition -6dB gain Full scale digital input load VCCP Min. Typ. Max. Unit mVRMS dBFS
Output level
output power(1)
Note: When VCCA values reduced
10.6
Power output levels
Absolute levels (Differential)
Analog supply range: VCCA
Symbol Parameter Test Condition gain Full scale digital input load VCCLS Min. Typ. 1.41 Max. Unit VRMS dBFS
Output level
output power(1)
some operating conditions maximum output power limited. "Section 8.1: Absolute maximum ratings" "Loudspeaker Driver" description from Section 3.9: Analog output drivers details. Note: When VCCA values reduced
58/69
STw5095
Stereo Audio Specifications
Stereo Audio Specifications
Typical measures VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8 Tamb=25° C;13 AMCK
Symbol ADDRM ADDRLI Parameter Resolution 20Hz 20kHz, A-weighted Measured -60dBFS input, 21dB gain Line-In, gain level input, 21dB gain A-weighted Unweighted kHz) A-weighted Input referred noise input Gain input 21dB Gain input 39dB Gain Line input Gain Line input 18dB Gain level input, 21dB gain Measurement bandwidth 20Hz 20kHz, 48kHz. Combined digital analog filter characteristics Combined digital analog filter characteristics AD96K=0 Combined digital analog filter characteristics AD96K=0 Combined digital analog filter characteristics AD96K=0 Measurement bandwidth 3.45Fs. Combined digital analog filter characteristics, AD96K=0 Audio filters, 96kHz Audio filters, 48kHz Audio filters, 8kHz 0.55Fs 0.001 0.003 Test Condition Min. Typ. Max. Unit Bits
Dynamic range
ADSNA ADSN
Signal noise ratio
ADTHD
Total harmonic distortion Deviation from linear phase
ADfPB
Passband Passband ripple
0.45Fs
ADfSB
Stopband
Stopband Attenuation
ADtgd
Group delay Interchannel isolation Interchannel gain mismatch Gain error
0.11
Note: When VCCA values reduced
59/69
Stereo Audio Specifications
STw5095
Stereo Audio Specifications
Typical measures VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz AMCK
Symbol Parameter Resolution 20Hz 20kHz, A-weighted. Measured -60dBFS Differential line Single-ended line HPL/HPR VCMHP LSP-LSN Test Condition Min. Typ. Max. Unit Bits
DADR
Dynamic range
DASNA DASN
2Vpp output HPL, gain -6dB, load Signal noise ratio A-weighted Unweighted kHz) Total harmonic distortion Worst case load Total harmonic distortion Deviation from linear phase 2Vpp output HPL, gain -6dB, load 2Vpp output, HPL, gain -6dB, load Measurement bandwidth 20Hz 20kHz, 48kHz. Combined digital analog filter characteristics Combined digital analog filter characteristics, DA96K=0 Combined digital analog filter characteristics, DA96K=0 Combined digital analog filter characteristics, DA96K=0 Measurement bandwidth 3.45Fs. Combined digital analog filter characteristics, DA96K=0 0.55Fs
0.02 0.04
DATHDL
DATHD
0.004
DAfPB
Passband Passband ripple
0.45Fs
DAfSB
Stopband
Stopband attenuation Transient suppression filter cut-off frequency band noise
Measurement bandwidth kHz. Zero input signal Audio filters, 96kHz Audio filters, 48kHz Audio filters, 8kHz 2Vpp output HPR, unloaded HPR, with VCMHP
0.09
DAtgd
Group delay
Interchannel isolation
60/69
STw5095
Mixing (Sidetone) Specifications
Symbol
Parameter Interchannel gain mismatch Gain error
Test Condition
Min.
Typ.
Max.
Unit
Startup time from power
FS=48
Line HPL/R
Note: When VCCA values reduced
Symbol STDEL
Mixing (Sidetone) Specifications
Parameter mixing (sidetone) delay Test Condition Valid audio voice filters Min. Typ. Max. Unit
Typical measures VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz AMCK
Stereo Analog-only Path Specifications
Measured differential line-out, ENOSC=1, master clock. Typical measures VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25°
Symbol Parameter Test Condition 20Hz 20kHz, A-weighted. Measured -60dBFS input, 21dB gain Line-In, gain level line-in input, gain, A-weighted Unweighted kHz) 1kHz 0dBFS input, 21dB gain Line-in input, gain 0.003 0.004 0.01 0.02 Min. Typ. Max. Unit
AADRM AADRLI
Dynamic range
AASNA AASN
Signal noise ratio
AATHD
Total harmonic distortion
Note: When 2.4V<VCCA<2.7V, values reduced 2dB.
61/69
(TX) (RX) Specifications With Voice Filters Selected
STw5095
(TX) (RX) Specifications With Voice Filters Selected
Typical measures VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz AMCK
Symbol Parameter Test Condition 300Hz 3.4kHz; 1kHz -60dBFS Path, input, 21dB gain Path, Output, gain Min. Typ. Max. Unit
TXDR RXDR TXSN RXSN
Dynamic range
<0.001 0.005
300Hz 3.4kHz; 1kHz 0dBFS Signal noise ratio Path, input, 21dB gain Path, Output, gain 1kHz 0dBFS Path, input, 21dB gain Path, Output, gain f=60Hz f=100Hz f=200Hz f=300Hz f=400Hz-3000Hz f=3400Hz f=4000H f=4600Hzz f=8000Hz f=60Hz f=100Hz f=200Hz f=300Hz f=400Hz-3000Hz f=3400Hz f=4000Hz f=5000Hz Measurement bandwidth 4kHz 100kHz. Zero input signal path path
gain mask
-1.5 -0.5 -1.5
gain mask
-1.5 -0.5 -1.5
band noise Group delay
0.32 0.28
Note: When 2.4V<VCCA<2.7V, values reduced
62/69
STw5095
Typical Performance Plots
Typical Performance Plots
Figure Dynamic compressor transfer function
Output Amplitude [FS] Frequency [Hz] 0.75 0.25 -0.25 -0.5 -0.75 -0.75-0.5-0.25 0.25 0.75 Input Amplitude [FS] Audio signal transfer function when Dynamic Compressor active.
Figure Bass treble control, de-emphasis filter
Gain Fs=44.1 [dB]
Bass treble gains independently selectable combination. de-emphasis filter (thick line, alternative treble control) compensates pre-emphasis used some audio CDs. Gain error 0.1dB. Filter characteristics Fs=44.1kHz plotted
Figure audio path measured filter response
Gain [dB] Frequency [Hz] 100k
Figure band audio path measured filter response
-0.1 -0.2 -0.3 -0.4 -0.5
Gain [dB]
Frequency [Hz]
sample rate. Full path Frequency response kHz.
Sample Rate. band Frequency response
Figure digital audio filter characteristics
Gain [dB] Frequency [Hz] 100k
Figure band digital audio filter characteristics
-0.1 -0.2 -0.3 -0.4 -0.5 Frequency [Hz] Sample Rate band Frequency response
DA96K=0; Sample Rate Frequency response 166kHz (3.45 48kHz sampling rate)
Gain [dB]
63/69
Typical Performance Plots
STw5095
Figure audio in-band measured filter response
Figure audio path measured filter response
Gain [dB]
Gain [dB] Frequency [Hz] 100k Frequency [Hz]
plot extended down show high pass filter implemented sample rate, audio filter selected signal from input
sample rate, audio filter selected signal from input.
Figure voice path measured filter response
Gain [dB] Frequency [Hz]
Figure voice path measured inband filter response
-0.1 -0.2 -0.3 -0.4 -0.5
Gain [dB]
1500 2500 Frequency [Hz]
3500
Sample rate, voice filter selected. Signal from input
sample rate, voice filter selected signal from input.
Figure voice (RX) digital filter characteristics
Gain [dB] Frequency [Hz]
Figure voice (RX) in-band digital filter characteristics
-0.1 -0.2 -0.3 -0.4 -0.5
Gain [dB]
1500 2500 Frequency [Hz]
3500
sample rate, voice filter
sample rate, voice filter
64/69
STw5095
Figure path
Amplitude [dBFS] [dB] -100 -120 Frequency [Hz]
Typical Performance Plots
Figure versus input-level
Input Level [dBFS]
master clock. Differential input preamplifier, gain. sampling rate. Both channels active
master clock Differential input Line-In Amplifier, Gain. Sampling Rate A-Weighted, Both channels active
Figure path
Amplitude [dBFS]
Figure versus input-level
[dB]
-100 -120 Frequency [Hz]
Input Level [dBFS]
master clock. sampling rate Differential output line-out, load. Both channels active
master clock. Sampling Rate Differential output Line-Out, load.
A-Weighted, Both channels active
Figure Analog path
Amplitude [dBFS]
Figure Analog path versus input-level
[dB]
-100 -120 Frequency [Hz]
Input Level [dBFS]
Differential input Preamplifier, Gain. Direct Line-Out connection (MICLO=1) Differential output Line-Out, load. Both channels active
Differential input Line-In Amplifier, Gain. Line-In DA-Mixer Line-Out connection. Differential output Line-Out, load. A-weighted, both channels active
65/69
Application Schematics
STw5095
Application Schematics
Figure STw5095 application schematics
MBIAS 2.7k 100nF MIC1LP 10µF Electret 100nF MIC1LN VCCIO 2.7k 2.7k 100nF MIC1RP 10µF Electret 100nF MIC1RN 2.7k HDET
application example Section 3.16 page
Needed CMOS
200nF
OCKAD CAPMIC OCKDA
MasterClocks Other Digital Device Digital Audio Data Source
Line
100nF 100nF
LINEINL LINEINR AUX1L AUX1R AUX2LP AUX2RP AUX2LN AUX2RN AUX3L AUX3R
Melody
0.47µF
STw5095
AD_SYNC AD_DATA AD_CK
AD_Fs [8kHz-48kHz] [88kHz-96kHz] Audio Data AD_Data AD_Data Clock
0.47µF Voice 0.47µF
Interface
40mW Max.
0.47µF 0.47µF
have single bidirectional interface connect: AD_SYNC DA_SYNC AD_CK DA_CK
Differential Connector
10µF
CAPLINEIN DA_SYNC VCMHP VCMHPS DA_DATA DA_CK
DA_Fs
[8kHz-48kHz] [88kHz-96kHz]
DA_Data DA_Data
SENSE
Clock 100pF
Audio Data Interface
10µF Standard Connection
Close possible pins
CAPLS AMCK
System Clock
[4MHz-32MHz]
500mW Max.
Close possible pins
SENSE
LSPS LSNS SDA/SDIN SCLK AS/CSB Data
SENSE
compat.
Clock
Line GNDCM VCCLS
CMOD
compat. selected
Leave negative pins unconnected when used Single-Ended Configuration
100nF
VCCA VCCP
100nF
100nF
VCCD
VCCIO VCCIO 100nF
GNDA
10µF
66/69
GNDP
VCCA
VCCP
STw5095
Package Outline
Package Outline
Dimensions [mm] Ref. 0.450 0.600 4.850 0.250 4.850 Min. 1.010 0.150 0.820 0.300 5.000 3.500 5.000 3.500 0.500 0.750 0.550 0.900 0.080 TFBGA 5x5x1.20 F8x8 0.50 Thin Profile Fine Pitch Ball Grid Array 5.150 0.350 5.150 Typ. Max. 1.200 OUTLINE MECHANICAL DATA
total profile height measured from seating plane component. mounted height 1.12mm.Based 0.28mm ball diameter. Solder paste 0.15mm thickness 0.28mm diameter.
Figure Package mechanical data
SEATING PLANE
CORNER INDEX AREA BALLS)
Note
BOTTOM VIEW
Note: terminal corner must identified surface using corner chamfer, metallized markings, other feature package body integral heatslug. distinguishing feature allowable bottom surface package identify terminal corner. Exact shape each corner optional.
67/69
Revision history
STw5095
Revision history
Date 8-Nov-2005 Revision Initial release Changes
68/69
STw5095
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics. other names property their respective owners 2005 STMicroelectronics rights reserved STMicroelectronics group companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States America www.st.com
69/69
Other recent searches
SU3B1 - SU3B1 SU3B1 Datasheet
SAY-11 - SAY-11 SAY-11 Datasheet
S858TA3 - S858TA3 S858TA3 Datasheet
RE46C112 - RE46C112 RE46C112 Datasheet
KSR1113 - KSR1113 KSR1113 Datasheet
KSR2113 - KSR2113 KSR2113 Datasheet
CFAH1602A-YYH-JPE - CFAH1602A-YYH-JPE CFAH1602A-YYH-JPE Datasheet
ASPI-6045S - ASPI-6045S ASPI-6045S Datasheet
asd07 - asd07 asd07 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
