Skew Output Buffer Frequency range 60MHz. Internal phase locked l
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PLL102-15
Skew Output Buffer
Frequency range 60MHz. Internal phase locked loop will allow spread spec trum modulation reference clock pass outputs 33kHz modulation). Zero input output delay. Less than device device skew. Less than skew between outputs. Less than cycle cycle jitter. Output Enable function -state outputs. 3.3V operation. Available -Pin 150mil SOIC.
CONFIGURATION
CLK1 CLKOUT
CLK3 CLK2 REF_IN
PLL102-15
Remark
REF_IN clock stopped more than 10us after already been provided chip, after power-up, output clocks will disappear. that instance, full power-up reset required order reactivate output clocks.
DESCRIPTIONS
PLL102 high performance, skew, jitter zero delay buffer designed stribute high speed clocks available -pin SOIC TSSOP package. four outputs that synchronized with input. synchronization established CLKOUT feedback input PLL. Since skew etween input outpu less than ±350 device acts zero delay buffer.
BLOCK DIAGRAM
REF_IN
CLKOUT CLK1 CLK2 CLK3
47745 Fremont Blvd., Fremont, California 94538
(510) 492-0990 (510) 492-0991
05/06/03 Page
PLL102-15
Skew Output Buffer
DESCRIPTIONS
Name
CLK1 CLKOUT REF_IN CLK2 CLK3
Number
Type
3.3V Power Supply. Buffered clock output.
Description
Buffered clock output. Internal back this pin. Ground. Input reference frequency. Spread spectrum modulation this signal will passed output 33kHz modulation). Buffered clock output. Buffered clock output. connection.
Notes: Weak pull-down. Weak pull -down outputs.
47745 Fremont Blvd., Fremont, California 94538
(510) 492-0990 (510) 492-0991
05/06/03 Page
PLL102-15
Skew Output Buffer
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature Storage Temperature Ambient Operating Temperature Voltage
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
Electrical Characteristics
3.0~3.6V, unless otherwise stated
PARAMETERS
Supply Voltage Input Voltage Input High Voltage Input Current Input High Current Output Voltage Output High Voltage Power Down Supply Current Supply Current
SYMBOL
CONDITIONS
MIN.
2.97
TYP.
MAX.
3.63
UNITS
0.10 0.25 30.0
50.0 100.0
50mA 50mA 0MHz Unloaded outputs 60MHz, inputs
50.0 40.0
47745 Fremont Blvd., Fremont, California 94538
(510) 492-0990 (510) 492-0991
05/06/03 Page
PLL102-15
Skew Output Buffer
Switching Characteristics PARAMETERS
Output Frequency Duty Cycle Duty Cycle Rise Time Fall Time Output Output Skew Delay, Rising Edge CLKOUT Rising Edge Device Device Skew Cycle Cycle Jitter Lock Time Jitter; Absolute Jitter Jitter; sima
SYMBOL
skew delay -dsk -cyc jabs
DESCRIPTION
Measured 1.4V, =30pF, Fout 60MHz Measured 1.4V Measured between 0.8V 2.0V, =30pF Measured between 2.0V 0.8V, =30pF outputs equally loaded, =20p Measured 1.4V Measured CLKOUT pins devices Loaded outputs Stable power supply, valid clock presented 10,000 cycles, =30pF 10,000 cycles, =30pF
MIN.
40.0 45.0
TYP.
MAX.
UNITS
50.0 50.0
60.0 55.0
±350
SWITCHING WAVEFORMS
Duty Cycle Timing
1.4V 1.4V 1.4V
Output Output Skew
Output
1.4V
1.4V
Output
SKEW
47745 Fremont Blvd., Fremont, California 94538
(510) 492-0990 (510) 492-0991
05/06/03 Page
PLL102-15
Skew Output Buffer
SWITCHING WAVE FORMS
Outputs Rise/Fall Time
2.0V 2.0V 0.8V 3.3V
Output
0.8V
Input Output Propagation Delay
VDD/2
Input
VDD/2
Output
Tdelay
Device Device Skew
VDD/2
Device1 CLKOUT
VDD/2
Device2 CLKOUT
Tdsk
47745 Fremont Blvd., Fremont, California 94538
(510) 492-0990 (510) 492-0991
05/06/03 Page
PLL102-15
Skew Output Buffer
Output-Output Skew skew between CLKOUT CLK(1-3) outputs dynamically adjusted PLL. Since CLKOUT inputs PLL, zero phase difference maintained from REF_IN CLKOUT. outputs equally loaded, zero phase difference will maintained from REF_IN outputs. applications requiring zero output-output skew, outputs must equally loaded. CLK(1-3) outputs less loaded than CLKOUT, CLK(1-3) outputs will lead CLK(1-3) more loaded than CLKOUT, CLK(1-3) will CLKOUT. Since CLKOUT CLK(1-3) outputs identical, they start same time, difference loads cause them have different rise times different times crossing measurement thresholds.
REF_IN CLKOUT CLK(1-3) Zero Delay
REF_IN input outputs loaded equally
REF_IN CLKOUT CLK(1-3) Advanced
REF_IN CLK(1-3) outputs loaded equally, with CLK(1-3) less loaded than CLKOUT.
REF_IN CLKOUT CLK(1-3) Delayed
REF_IN input CLK(1-3) outputs loaded equally, with CLK(1-3) more loaded than CLKOUT.
47745 Fremont Blvd., Fremont, California 94538
(510) 492-0990 (510) 492-0991
05/06/03 Page
PLL102-15
Skew Output Buffer
PACKAGE INFORMATION
Narrow SOIC
SOIC Symbol Min. 1.55 0.15 0.35 0.19 4.80 3.81 5.84 0.41 1.27 Max. 1.73 0.18 0.49 0.25 4.98 3.99 6.20 0.89
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 0990 Fax: (510) 492- 0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL102-15
PART NUMBER TEMPERATURE C=COMMERCIAL (0°~70°C
PACKAGE TYPE S=SOIC
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's oducts authorized critical components life support devices systems without press written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538
(510) 492-0990 (510) 492-0991
05/06/03 Page
PLL102-15
Skew Output Buffer
REVISION HISTORY
06/20/01 10/23/01 11/07/01 11/29/01 10/08/02 01/13/03 Created from preliminary PLL102 PLL102-04 Document Removed Power Down mode absence (not supported final version). Added 3.3V Electrical Specs clarity. Added Remark clock absence page Change pass through modulation rate from 100kHz 33kHz. Changed Frequency range from "25-75MHz" "25-60MHz" Features section page Changed Supply Current from Unloaded outputs "66.67MHz" "60MHz" page Changed Max. Output Frequency from "75" "60" page Deleted "Fout 50.0MHz" Duty Cycle (Dt2) "Measured 60MHz" Cycle Cycle Jitter (Tcyc -cyc) Switching Characteristics section page Bonding diagram modification P102 (ICS553 compatible)
05/06/03
47745 Fremont Blvd., Fremont, California 94538
(510) 492-0990 (510) 492-0991
05/06/03 Page
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