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Preliminary Product Preview Skew Output Buffer General Descr


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ICS9112-28
Preliminary Product Preview
Skew Output Buffer
General Description
ICS9112-28 high performance, skew, jitter clock driver. designed distribute high speed clocks systems operating speeds from MHz. ICS9112-28 comes eight SOIC package. four output clocks.
Features
Frequency range (3.3V) Less than Jitter between outputs Skew controlled outputs Skew less than between outputs Available SOIC TSSOP packages. 3.3V ±10% operation
Block Diagram
CLK0 CLK1 CLK_IN CLK2
Configuration
CLK_IN CLK0 CLK1
ICS9112-28
CLK4 CLK3 CLK2
SOIC
CLK3 CLK4
Descriptions
NUMBER NAME CLK_IN CLK0 CLK11 CLK2
TYPE Input reference frequency. Buffered clock output Ground Buffered clock output Buffered clock output Buffered clock output Power Supply (3.3V) Buffered clock output
DESCRIPTION
CLK3 CLK4
Notes: Weak pull-down outputs
9112-28 01/09/06
PRODUCT PREVIEW documents contain information products sampling preproduction phase development. Characteristic data other specifications subject change without notice.
ICS9112-28
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage Logic Inputs Ambient Operating Temperature Storage Temperature -0.5 +0.5 +70°C -65°C +150°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only functional operation device these other conditions above those listed operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
Electrical Characteristics 3.3V
unless otherwise stated
Characte tics PARAMETER Input Voltage Input High Voltage Input Current Input High Current Output Voltage1 Output High Voltage1 Supply Current Supply Current SYMBOL VIN=0V VIN=VDD Unloaded outputs 66.66 50.0 40.0 50.0 100.0 TEST CONDITIONS UNITS
Notes: Guaranteed design characterization. subject 100% test. Skew specifications mesured with transmission line, load teminated with 1.4V. Duty cycle measured 1.4V. Skew measured 1.4V rising edges. Loading must equal outputs.
Switching Characteristics (3.3V Continued)
PARAMETER Propagation delay Rise Time1 Fall Time1 Output Output Skew1 Device Device Skew1 SYMBOL Tskew Tdsk-Tdsk Measured between 0.8V 2.0V: CL=30pF operating frequencies Measured between 2.0V 0.8V; CL=30pF operating frequencies outputs equally loaded, CL=20pF Measured VDD/2 CLKOUT pins devices CONDITION UNITS
Notes: Guaranteed design characterization. subject 100% test. CLK_IN input threshold voltage 1.4V parameters expected with loaded outputs
ICS9112-28
Preliminary Product Preview
INDEX AREA
SEATING PLANE (.004)
(Narrow Body) SOIC Millimeters Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS 1.35 1.75 .0532 .0688 0.10 0.25 .0040 .0098 0.33 0.51 .013 .020 0.19 0.25 .0075 .0098 VARIATIONS VARIATIONS 3.80 4.00 .1497 .1574 0.050 BASIC 1.27 BASIC 5.80 6.20 .2284 .2440 0.25 0.50 .010 .020 0.40 1.27 .016 .050 VARIATIONS VARIATIONS VARIATIONS 4.80 5.00 (inch) .1890 .1968
Reference Doc.: JEDEC Publication MS-012 10-0030
(Narrow Body) SOIC
Ordering Information
ICS9112yM-28LF-T
Example:
XXXX
Designation tape reel packaging
Lead Free, RoHS Compliant (Optional)
Pattern Number digit number parts with code patterns) Package Type M=SOIC
Revision Designator (will correlate with datasheet revision)
Device Type (consists digit numbers) Prefix Standard Device
PRODUCT PREVIEW documents contain information products sampling preproduction phase development. Characteristic data other specifications subject change without notice.

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